LM 7171

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LM7171

SNOS760D – MAY 1999 – REVISED FEBRUARY 2024

LM7171 Very High Speed, High Output Current, Voltage Feedback Amplifier

1 Features 3 Description
• Typical values unless otherwise noted The LM7171 is a high-speed voltage-feedback
• Easy-to-use voltage-feedback topology amplifier that has the slewing characteristic of a
• Very high slew rate: 4100V/μs current-feedback amplifier, but can be used in all
• Wide unity-gain bandwidth: 200MHz traditional voltage-feedback amplifier configurations.
• −3dB frequency at AV = +2: 220MHz The LM7171 is stable for gains as low as +2 or −1.
• Low supply current: 6.5mA The device provides a very high slew rate at 4100V/μs
• High open-loop gain: 85dB and a wide unity-gain bandwidth of 200MHz, while
• High output current: 100mA consuming only 6.5mA of supply current. The LM7171
• Differential gain and phase: 0.01%, 0.02º is an excellent choice for video and high-speed signal
• Specified for ±15V and ±5V operation processing applications, such as HDSL and pulse
amplifiers. With 100mA of output current, the LM7171
2 Applications is used for video distribution, as a transformer driver,
• HDSL and ADSL drivers or as a laser diode driver.
• Multimedia broadcast systems
Operation on ±15V power supplies allows for large
• Professional video cameras
signal swings and provides greater dynamic range
• Video amplifiers
and signal-to-noise ratio. The LM7171 offers low
• Copiers, scanners, fax
SFDR and THD, which is excellent for ADC/DAC
• HDTV amplifiers
systems. In addition, the LM7171 is specified for ±5V
• Pulse amplifiers and peak detectors
operation for portable applications.
• CATV and fiber optics signal processing
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
D (SOIC, 8) 4.90mm × 6mm
LM7171
P (PDIP, 8) 9.81mm × 9.43mm

(1) For more information, see Section 9.


(2) The package size (length × width) is a nominal value and
includes pins, where applicable.

Note: M1 and M2 are current mirrors.

Simplified Schematic Diagram

Large-Signal Pulse Response AV = +2, VS = ±15V

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM7171
SNOS760D – MAY 1999 – REVISED FEBRUARY 2024 www.ti.com

Table of Contents
1 Features............................................................................1 6 Application and Implementation.................................. 24
2 Applications..................................................................... 1 6.1 Application Information............................................. 24
3 Description.......................................................................1 6.2 Typical Applications.................................................. 25
4 Pin Configuration and Functions...................................2 6.3 Power Supply Recommendations.............................26
5 Specifications.................................................................. 3 6.4 Layout....................................................................... 29
5.1 Absolute Maximum Ratings........................................ 3 7 Device and Documentation Support............................30
5.2 ESD Ratings............................................................... 3 7.1 Receiving Notification of Documentation Updates....30
5.3 Recommended Operating Conditions.........................3 7.2 Support Resources................................................... 30
5.4 Thermal Information....................................................3 7.3 Trademarks............................................................... 30
5.5 Electrical Characteristics: ±15V.................................. 4 7.4 Electrostatic Discharge Caution................................30
5.6 Electrical Characteristics: ±5V.................................... 6 7.5 Glossary....................................................................30
5.7 Typical Characteristics: LM7171A...............................8 8 Revision History............................................................ 30
5.8 Typical Characteristics: LM7171B.............................15 9 Mechanical, Packaging, and Orderable Information.. 31

4 Pin Configuration and Functions

Figure 4-1. D Package, 8-Pin SOIC (Top View)

Table 4-1. Pin Functions


PIN
TYPE DESCRIPTION
NO. NAME
1 NC — No connection
2 –IN Input Inverting power supply
3 +IN Input Noninverting power supply
4 V– Input Supply voltage
5 NC — No connection
6 OUTPUT Output Output
7 V+ Input Supply voltage
8 NC — No connection

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VS Supply voltage (V+ – V–) 36 V
VI Differential input voltage(2) ±10 V
ISC Output current short to ground(3) Continuous A
TJ Junction temperature(4) 150 ℃

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Input differential voltage is applied at VS = ±15V.
(3) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result
in exceeding the maximum allowed junction temperature of 150°C.
(4) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX)–TA)/RθJA. All numbers apply for packages soldered directly into a PC board.

5.2 ESD Ratings


VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
±2500 V
JEDEC JS-001(1)
V(ESD) Electrostatic discharge
Charged device model (CDM), per ANSI/ESDA/
±1500 V
JEDEC JS-002(2)

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP155 states that 2500V HBM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions


over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VS Supply voltage 5.5 36 V
TA Ambient temperature −40 85 °C

5.4 Thermal Information


LM7171
THERMAL METRIC(1) D (SOIC) A Version D (SOIC) B Version P (PDIP) UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 122.5 172 108 ℃/W
RθJC(top) Junction-to-case (top) thermal resistance 64.7 62.4 52.4 ℃/W
RθJB Junction-to-board thermal resistance 65.9 55.7 51.9 ℃/W
ΨJT Junction-to-top characterization parameter 17.6 16.5 6.8 ℃/W
ΨJB Junction-to-board characterization parameter 65.1 55.1 51.1 ℃/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A ℃/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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5.5 Electrical Characteristics: ±15V


over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.2 1
LM7171A
TA = –40°C to +85°C 4
VOS Input offset voltage mV
0.2 3
LM7171B
TA = –40°C to +85°C 7
TCVOS Input offset voltage average drift 35 μV/°C
2.7 10
IB Input bias current μA
TA = –40°C to +85°C 12
0.1 4
IOS Input offset current μA
TA = –40°C to +85°C 6
Common mode 320
RIN Input resistance MΩ
Differential mode 18
RO Open-loop output resistance 19 Ω
VCM = ±10V 85 105
LM7171A VCM = ±10V, dB
80
TA = –40°C to +85°C
CMRR Common-mode rejection ratio
VCM = ±10V 75 105
LM7171B VCM = ±10V,
70
TA = –40°C to +85°C
VS = ±15V 85 90
LM7171A VS = ±15V, dB
80
TA = –40°C to +85°C
PSRR Power supply rejection ratio
VS = ±15V
LM7171B VS = ±15V,
TA = –40°C to +85°C
VCM Input common-mode voltage CMRR > 60dB ±13.35 V
RL = 1kΩ, VOUT = ±5V 80 85
RL = 1kΩ, VOUT = ±5V,
75
TA = –40°C to +85°C
LM7171A
RL = 100Ω, VOUT = ±5V 75 81
RL = 100Ω, VOUT = ±5V,
70
TA = –40°C to +85°C
AV Large-signal voltage gain dB
RL = 1kΩ, VOUT = ±5V 75 85
RL = 1kΩ, VOUT = ±5V,
70
TA = –40°C to +85°C
LM7171B
RL = 100Ω, VOUT = ±5V 70 81
RL = 100Ω, VOUT = ±5V,
66
TA = –40°C to +85°C
13 13.3
RL = 1kΩ
TA = –40°C to +85°C 12.7
–13 –13.2
RL = 1kΩ
TA = –40°C to +85°C –12.7
VO Output swing V
10.5 11.8
RL = 100Ω
TA = –40°C to +85°C 9.5
–9.5 –10.5
RL = 100Ω
TA = –40°C to +85°C –9

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5.5 Electrical Characteristics: ±15V (continued)


over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Sourcing, 105 118


RL = 100Ω TA = –40°C to +85°C 95
Output current (open loop)
Sinking, 95 105
RL = 100Ω TA = –40°C to +85°C 90
Sourcing, RL = 100Ω 100
Output current (in linear region) mA
Sinking, RL = 100Ω 100
Sourcing 140
ISC Output short-circuit current
Sinking 135
6.5 8.5
IS Supply current
9.5
AV = +2, VIN = 13VPP 4100
SR Slew rate V/μs
AV = +2, VIN = 10VPP 3100
LM7171A 160
Unity-gain bandwidth MHz
LM7171B 200
−3dB frequency AV = +2 220 MHz
φm Phase margin 50 Deg

AV = −1, VOUT = ±5V, LM7171A 16 ns


ts Settling time (0.1%)
RL = 500Ω LM7171B 42 ns
AV = −2, VIN = ±1V,
tp Propagation delay 5 ns
RL = 500Ω
fIN = 10kHz –123
LM7171A
fIN = 5MHz –75
HD2 Second harmonic distortion dBc
fIN = 10kHz –110
LM7171B
fIN = 5MHz –75
fIN = 10kHz –133
LM7171A
fIN = 5MHz –88
HD3 Third harmonic distortion dBc
fIN = 10kHz –115
LM7171B
fIN = 5MHz –55
LM7171A 8.5
en Input-referred voltage noise f = 10kHz nV/√Hz
LM7171B 14
LM7171A 1
in Input-referred current noise f = 10kHz pA/√Hz
LM7171B 1.5

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5.6 Electrical Characteristics: ±5V


over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.3 1.5
LM7171A
TA = –40°C to +85°C 4
VOS Input offset voltage mV
0.3 3.5
LM7171B
TA = –40°C to +85°C 7
TCVOS Input offset voltage average drift 35 μV/°C
3.3 10
IB Input bias current µA
TA = –40°C to +85°C 12
0.1 4
IOS Input offset current µA
TA = –40°C to +85°C 6
Common mode 250
RIN Input resistance MΩ
Differential mode 18
RO Open-loop output resistance 18 Ω
VCM = ±2.5V 80 104
LM7171A VCM = ±2.5V, TA = –40°C
75
to +85°C
CMRR Common-mode rejection ratio dB
VCM = ±2.5V 70 104
LM7171B VCM = ±2.5V, TA = –40°C
65
to +85°C
VS = ±5V 85 90
LM7171A VS = ±5V, TA = –40°C to
80
+85°C
PSRR Power supply rejection ratio dB
VS = ±5V 75 90
LM7171B VS = ±5V, TA = –40°C to
70
+85°C
VCM Input common-mode voltage range CMRR > 60dB ±3.2 V
RL = 1kΩ, VOUT = ±1V 75 78
RL = 1kΩ, VOUT = ±1V,
70
TA = –40°C to +85°C
LM7171A
RL = 100Ω, VOUT = ±1V 72 76
RL = 100Ω, VOUT = ±1V,
67
TA = –40°C to +85°C
AV Large-signal voltage gain dB
RL = 1kΩ, VOUT = ±1V 70 78
RL = 1kΩ, VOUT = ±1V,
65
TA = –40°C to +85°C
LM7171B
RL = 100Ω, VOUT = ±1V 68 76
RL = 100Ω, VOUT = ±1V,
63
TA = –40°C to +85°C
3.2 3.4
–3.2 –3.4
RL = 1kΩ
3
TA = –40°C to +85°C
–3
VO Output swing V
2.9 3.1
–2.9 –3
RL = 100Ω
2.8
TA = –40°C to +85°C
–2.8

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5.6 Electrical Characteristics: ±5V (continued)


over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Sourcing, 29 31
RL = 100Ω TA = –40°C to +85°C 28
Output current (open loop) mA
Sinking, 29 30
RL = 100Ω TA = –40°C to +85°C 28
Sourcing, RL = 100Ω 30
Output current (in linear region) mA
Sinking, RL = 100Ω 31
Sourcing 135
ISC Output short-circuit current mA
Sinking 100
6.2 8
IS Supply current mA
TA = –40°C to +85°C 9

AV = +2, LM7171A 1200


SR Slew rate V/μs
VIN = 3.2VPP LM7171B 950
LM7171A 125
Unity-gain bandwidth MHz
LM7171B 125
LM7171A 140
−3dB frequency AV = +2 MHz
LM7171B 140
LM7171A 68
φm Phase margin Deg
LM7171B 57

AV = −1, VOUT = ±1V, LM7171A 15


ts Settling time (0.1%) ns
RL = 500Ω LM7171B 56

AV = −2, VIN = ±1V, LM7171A 2.5


tp Propagation delay ns
RL = 500Ω LM7171B 6
fIN = 10kHz –125
LM7171A
fIN = 5MHz –72
HD2 Second harmonic distortion dBc
fIN = 10kHz –102
LM7171B
fIN = 5MHz –70
fIN = 10kHz –129
LM7171A
fIN = 5MHz –81
HD3 Third harmonic distortion dBc
fIN = 10kHz –110
LM7171B
fIN = 5MHz –51
LM7171A 8.5
en Input-referred voltage noise f = 10kHz nV/√Hz
LM7171B 14
LM7171A 1
in Input-referred current noise f = 10kHz pA/√Hz
LM7171B 1.8

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5.7 Typical Characteristics: LM7171A


at TA= 25°C (unless otherwise noted)

7 7
6.5
6 6.75
5.5
5
Supply Current (mA)

Supply Current (mA)


4.5 6.5
4
3.5 6.25
3
2.5 −55C 6
2 −40C
1.5 −25C
25C 5.75
1 50C VS = 5V
0.5 105C VS = 15V
0 5.5
0 5 10 15 20 25 30 35 40 -60 -40 -20 0 20 40 60 80 100 120 140
Supply Voltage (V) Temperature (C)

Figure 5-1. Supply Current vs Supply Voltage Figure 5-2. Supply Current vs Temperature
0.5 0.3
0.25
0.25 0.2
0.15
Input Bias Current (A)

0
Offset Voltage (mV)

0.1
-0.25 0.05
0
-0.5 -0.05
-0.1
-0.75
-0.15

-1 -0.2
VS = 5V VS = 5V
VS = 15V -0.25 VS = 15V
-1.25 -0.3
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (C) Temperature (C)

Figure 5-3. Input Offset Voltage vs Temperature Figure 5-4. Input Bias Current vs Temperature
140 -85
VS = 5V -90
135
VS = 15V
130 -95

125 -100
-105
120
Current (mA)

Current (mA)

-110
115
-115
110
-120
105
-125
100 -130
95 -135
VS = 5V
90 -140 VS = 15V
85 -145
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (C) Temperature (C)

Figure 5-5. Short Circuit Current vs Temperature (Sourcing) Figure 5-6. Short Circuit Current vs Temperature (Sinking)

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5.7 Typical Characteristics: LM7171A (continued)


at TA= 25°C (unless otherwise noted)

15
12.5
10
7.5
Output Voltage (V)

5
2.5
0
-2.5
-5
-7.5
-10 −40C
25C
-12.5 85C
-15
-100 -80 -60 -40 -20 0 20 40 60 80 100
Current (mA)
VS = ±15V VS = ±5V
Figure 5-7. Output Voltage vs Output Current Figure 5-8. Output Voltage vs Output Current
120 140
Common Mode Rejection Ratio (dB)

Power Supply Rejection Ratio (dB) 120


100

100
80
80
60
60
40
40

20 20
VS = 15 V Positive
VS = 5 V Negative
0 0
1 10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)
VS = 30V
Figure 5-9. CMRR vs Frequency Figure 5-10. PSRR vs Frequency
140 120 135

100 120
Power Supply Rejection Ratio (dB)

120
Open Loop Gain Magnitude (dB)

80 105
100
60 90

Phase Margin ()


80 40 75

60 20 60

0 45
40
-20 30
20 Positive Magnitude
-40 15
Negative Phase
0 -60 0
10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)

VS = 10V VS = ±15V
Figure 5-11. PSRR vs Frequency Figure 5-12. Open Loop Frequency Response

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5.7 Typical Characteristics: LM7171A (continued)


at TA= 25°C (unless otherwise noted)

120 135 144

100 120 143


Open Loop Gain Magnitude (dB)

80 105 142

Gain Bandwidth (MHz)


60 90 141

Phase Margin ()


40 75 140

20 60 139

0 45 138

-20 30 137

-40 Magnitude 15 136


Phase
-60 0 135
10 100 1k 10k 100k 1M 10M 100M 1G 5 10 15 20 25 30 35 40
Frequency (Hz) Supply Voltage (V)

VS = ±5V
Figure 5-13. Open Loop Frequency Response Figure 5-14. Gain-Bandwidth Product vs Supply Voltage
240 60
5V
220
200
Voltage Noise (nV/Hz)
Gain Bandwidth (MHz)

180
40
160
140
120
100
20
80
60
40
20 0
0 100 200 300 400 500 600 700 800 900 1000 10 100 1k 10k
Load Capacitance (pF) Frequency (Hz)

Figure 5-15. Gain-Bandwidth Product vs Load Capacitance Figure 5-16. Input Voltage Noise vs Frequency
20 4500
5V
4000

15 3500
Current Noise (pA/Hz)

Slew Rate (V/s)

3000

10 2500

2000

5 1500

1000

0 500
10 100 1k 10k 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30
Frequency (Hz) Supply Voltage (V )

Figure 5-17. Input Current Noise vs Frequency Figure 5-18. Slew Rate vs Supply Voltage

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5.7 Typical Characteristics: LM7171A (continued)


at TA= 25°C (unless otherwise noted)

4000 4500

4000
3500
3500
3000
3000
Slew Rate (V/s)

Slew Rate (V/s)


2500 2500

2000 2000

1500
1500
1000
1000
500

500 0
0 1 2 3 4 5 6 7 8 9 10 0 100 200 300 400 500 600 700 800 900 1000
Input Voltage (Vpp) Load Capacitance (pF)

Figure 5-19. Slew Rate vs Input Voltage Figure 5-20. Slew Rate vs Load Capacitance
25 25
Sourcing Sourcing
Sinking Sinking
Output Impedance ()

Output Impedance ()

20 20

15 15

10 10
1M 10M 100M 1G 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
VS = ±15V VS = ±5V
Figure 5-21. Open Loop Output Impedance vs Frequency Figure 5-22. Open Loop Output Impedance vs Frequency
7 4
6
5 3
4
2
3
Output Voltage (V)

Output Voltage (V)

2 1
1
0 0
-1
-2 -1
-3
-2
-4
-5 -3
-6
-7 -4
0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120
Time (ns) Time (ns)
AV = −1 VS = ±15V AV = −1 VS = ±5V
Figure 5-23. Large-Signal Pulse Response Figure 5-24. Large-Signal Pulse Response

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5.7 Typical Characteristics: LM7171A (continued)


at TA= 25°C (unless otherwise noted)

12 4
10
3
8
6 2

Output Voltage (V)


Output Voltage (V)

4
1
2
0 0
-2
-1
-4
-6 -2
-8
-3
-10
-12 -4
0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120
Time (ns) Time (ns)
AV = +2 VS = ±15V AV = +2 VS = ±5V
Figure 5-25. Large-Signal Pulse Response Figure 5-26. Large-Signal Pulse Response
0.15 0.15

0.1 0.1
Output Voltage (V)

Output Voltage (V)

0.05 0.05

0 0

-0.05 -0.05

-0.1 -0.1

-0.15 -0.15
0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120
Time (ns) Time (ns)
AV = −1 VS = ±15V AV = −1 VS = ±5V
Figure 5-27. Small-Signal Pulse Response Figure 5-28. Small-Signal Pulse Response
0.25 0.25
0.2 0.2
0.15 0.15
0.1 0.1
Output Voltage (V)

Output Voltage (V)

0.05 0.05
0 0
-0.05 -0.05
-0.1 -0.1
-0.15 -0.15
-0.2 -0.2
-0.25 -0.25
0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120
Time (ns) Time (ns)
AV = +2 VS = ±15V AV = +2 VS = ±5V
Figure 5-29. Small-Signal Pulse Response Figure 5-30. Small-Signal Pulse Response

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5.7 Typical Characteristics: LM7171A (continued)


at TA= 25°C (unless otherwise noted)

10 20

5 15
10
0
5
-5 0
Gain (dB)

Gain (dB)
-10 -5

-15 -10
-15 CL = 1.5pF
-20 VS = 2.75V CL = 50pF
VS = 5V -20 CL = 100pF
-25 VS = 10V -25 CL = 220pF
VS = 15V CL = 1000pF
-30 -30
1M 10M 100M 1M 10M 100M
Frequency (Hz) Frequency (Hz)
AV = +2 AV = +2 VS = ±5V
Figure 5-31. Closed-Loop Frequency Response vs Figure 5-32. Closed-Loop Frequency Response vs
Supply Voltage Capacitive Load
20 10
15 5
10
0
5
0 -5
Gain (dB)

Gain (dB)

-5 -10
-10 -15
-15 CL = 1.5pF
CL = 50pF -20
-20 CL = 100pF 20mV
-25 CL = 220pF -25 50mV
CL = 1000pF 500mV
-30 -30
1M 10M 100M 1M 10M 100M
Frequency (Hz) Frequency (Hz)
AV = +2 VS = ±15V AV = +2
Figure 5-33. Closed-Loop Frequency Response vs Figure 5-34. Closed-Loop Frequency Response vs
Capacitive Load Input Signal Level
10 -60
HD2
5 -70 HD3
-80
Harmonic Distortion (dBc)

0
-90
-5
Gain (dB)

-100
-10
-110
-15
-120
-20
-130
20mV
-25 50mV -140
500mV
-30 -150
1M 10M 100M 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)
AV = +2 VS = ±15V RL = 100Ω
Figure 5-35. Closed-Loop Frequency Response vs Figure 5-36. Total Harmonic Distortion vs Frequency
Input Signal Level

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5.7 Typical Characteristics: LM7171A (continued)


at TA= 25°C (unless otherwise noted)

-60 -60
HD2 HD2
-70 HD3 -70 HD3
-80 -80
Harmonic Distortion (dBc)

Harmonic Distortion (dBc)


-90 -90

-100 -100

-110 -110

-120 -120

-130 -130

-140 -140

-150 -150
10k 100k 1M 10M 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)
VS = ±5V RL = 100Ω VS = ±15V RL = 2.5kΩ
Figure 5-37. Total Harmonic Distortion vs Frequency Figure 5-38. Harmonic Distortion vs Frequency
-60
HD2
-70 HD3
-80
Harmonic Distortion (dBc)

-90

-100

-110

-120

-130

-140

-150
10k 100k 1M 10M
Frequency (Hz)
VS = ±5V RL = 2.5kΩ
Figure 5-39. Harmonic Distortion vs Frequency

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5.8 Typical Characteristics: LM7171B


at TA= 25°C (unless otherwise noted)

Figure 5-40. Supply Current vs Supply Voltage Figure 5-41. Supply Current vs Temperature

Figure 5-42. Input Offset Voltage vs Temperature Figure 5-43. Input Bias Current vs Temperature

Figure 5-44. Short Circuit Current vs Temperature (Sourcing) Figure 5-45. Short Circuit Current vs Temperature (Sinking)

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5.8 Typical Characteristics: LM7171B (continued)


at TA= 25°C (unless otherwise noted)

Figure 5-46. Output Voltage vs Output Current Figure 5-47. Output Voltage vs Output Current

Figure 5-48. CMRR vs Frequency Figure 5-49. PSRR vs Frequency

Figure 5-50. PSRR vs Frequency Figure 5-51. Open Loop Frequency Response

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5.8 Typical Characteristics: LM7171B (continued)


at TA= 25°C (unless otherwise noted)

Figure 5-52. Open Loop Frequency Response Figure 5-53. Gain-Bandwidth Product vs Supply Voltage

Figure 5-54. Gain-Bandwidth Product vs Load Capacitance Figure 5-55. Large Signal Voltage Gain vs Load

Figure 5-56. Large Signal Voltage Gain vs Load Figure 5-57. Input Voltage Noise vs Frequency

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5.8 Typical Characteristics: LM7171B (continued)


at TA= 25°C (unless otherwise noted)

Figure 5-58. Input Voltage Noise vs Frequency Figure 5-59. Input Current Noise vs Frequency

Figure 5-60. Input Current Noise vs Frequency Figure 5-61. Slew Rate vs Supply Voltage

Figure 5-62. Slew Rate vs Input Voltage Figure 5-63. Slew Rate vs Load Capacitance

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5.8 Typical Characteristics: LM7171B (continued)


at TA= 25°C (unless otherwise noted)

Figure 5-64. Open Loop Output Impedance vs Frequency Figure 5-65. Open Loop Output Impedance vs Frequency

AV = –1 VS = ±15V AV = –1 VS = ±5V
Figure 5-66. Large-Signal Pulse Response Figure 5-67. Large-Signal Pulse Response

AV = +2 VS = ±15V AV = +2 VS = ±5V
Figure 5-68. Large-Signal Pulse Response Figure 5-69. Large-Signal Pulse Response

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5.8 Typical Characteristics: LM7171B (continued)


at TA= 25°C (unless otherwise noted)

AV = –1 VS = ±15V AV = –1 VS = ±5V
Figure 5-70. Small-Signal Pulse Response Figure 5-71. Small-Signal Pulse Response

AV = +2 VS = ±15V AV = +2 VS = ±5V
Figure 5-72. Small-Signal Pulse Response Figure 5-73. Small-Signal Pulse Response

AV = +2 AV = +2
Figure 5-74. Closed-Loop Frequency Response vs Figure 5-75. Closed-Loop Frequency Response vs
Supply Voltage Capacitive Load

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5.8 Typical Characteristics: LM7171B (continued)


at TA= 25°C (unless otherwise noted)

AV = +2 AV = +2
Figure 5-76. Closed-Loop Frequency Response vs Figure 5-77. Closed-Loop Frequency Response vs
Capacitive Load Input Signal Level

AV = +2 AV = +2
Figure 5-78. Closed-Loop Frequency Response vs Figure 5-79. Closed-Loop Frequency Response vs
Input Signal Level Input Signal Level

AV = +2 AV = +4
Figure 5-80. Closed-Loop Frequency Response vs Figure 5-81. Closed-Loop Frequency Response vs
Input Signal Level Input Signal Level

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5.8 Typical Characteristics: LM7171B (continued)


at TA= 25°C (unless otherwise noted)

AV = +4 AV = +4
Figure 5-82. Closed-Loop Frequency Response vs Figure 5-83. Closed-Loop Frequency Response vs
Input Signal Level Input Signal Level

AV = +4 THD measurement at low frequency limited by test instrument

Figure 5-84. Closed-Loop Frequency Response vs Figure 5-85. Total Harmonic Distortion vs Frequency
Input Signal Level

THD measurement at low frequency limited by test instrument


Figure 5-86. Total Harmonic Distortion vs Frequency Figure 5-87. Undistorted Output Swing vs Frequency

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5.8 Typical Characteristics: LM7171B (continued)


at TA= 25°C (unless otherwise noted)

Figure 5-88. Undistorted Output Swing vs Frequency Figure 5-89. Undistorted Output Swing vs Frequency

THD measurement at low frequency limited by test instrument THD measurement at low frequency limited by test instrument
Figure 5-90. Harmonic Distortion vs Frequency Figure 5-91. Harmonic Distortion vs Frequency

Figure 5-92. Maximum Power Dissipation vs Ambient Temperature

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6 Application and Implementation


Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

6.1 Application Information


The LM7171 is a very high-speed, voltage-feedback amplifier (VFA). This device consumes only 6.5mA of
supply current while providing a unity-gain bandwidth of 200MHz and a slew rate of 4100V/μs. The LM7171 also
has other great features such as low differential gain and phase and high output current.
The LM7171 is a true VFA. Unlike a current-feedback amplifier (CFA) with a low inverting input impedance and
a high noninverting input impedance, both inputs of a VFA have high-impedance nodes. The low-impedance
inverting input of a CFA and a feedback capacitor create an additional pole that leads to instability. As a
result, CFAs cannot be used in traditional op-amp circuits such as photodiode amplifiers, I-to-V converters, and
integrators, where a feedback capacitor is required.
6.1.1 Circuit Operation
The class AB input stage in LM7171 is fully symmetrical and has a similar slewing characteristic to a CFA. In
the LM7171 simplified schematic, Q1 through Q4 form the equivalent of the current-feedback input buffer, RE
the equivalent of the feedback resistor, and stage A buffers the inverting input. The triple-buffered output stage
isolates the gain stage from the load to provide low output impedance.
6.1.2 Slew Rate Characteristic
The slew rate of LM7171 is determined by the current available to charge and discharge an internal high
impedance node capacitor. This current is the differential input voltage divided by the total degeneration resistor
RE. Therefore, the slew rate is proportional to the input voltage level, and the higher slew rates are achievable in
the lower gain configurations. A curve of slew rate versus input voltage level is provided in Section 5.8.
When a very fast large signal pulse is applied to the input of an amplifier, some overshoot or undershoot occurs.
By placing an external resistor such as 1kΩ in series with the input of LM7171, the bandwidth is reduced to help
lower the overshoot.
6.1.2.1 Slew-Rate Limitation
If the amplifier input signal amplitude is too large and the frequency too high, the amplifier is slew-rate limited.
This limiting can cause ringing in the time domain and peaking in the frequency domain at the output of the
amplifier.
For the AV = +2 curves, slight peaking occurs. This peaking at high frequency (> 100MHz) is due to a large input
signal at a high enough frequency that exceeds the amplifier slew rate. The peaking in the frequency response
does not limit the pulse response in the time domain, and the LM7171 is stable with a noise gain of ≥ +2.

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6.1.3 Compensation for Input Capacitance


The combination of an amplifier input capacitance with the gain setting resistors adds a pole that can cause
peaking or oscillation. To solve this problem, a feedback capacitor with a value of

CF > (RG × CIN) / RF (1)

can be used to cancel that pole. For LM7171, a feedback capacitor of 2pF is recommended. Figure 6-1
illustrates the compensation circuit.

Figure 6-1. Compensating for Input Capacitance

6.2 Typical Applications

Figure 6-2. Fast Instrumentation Amplifier

Figure 6-3. Multivibrator

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Figure 6-4. Pulse Width Modulator

Figure 6-5. Video Line Driver

6.3 Power Supply Recommendations


6.3.1 Power-Supply Bypassing
Bypassing the power supply is necessary to maintain low power-supply impedance across frequency. To bypass
both positive and negative power supplies individually, place 0.01μF ceramic capacitors directly to the power-
supply pins, and 2.2μF tantalum capacitors close to the power-supply pins.

Figure 6-6. Power-Supply Bypassing

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6.3.2 Termination
In high-frequency applications, reflections occur if signals are not properly terminated. Figure 6-7 shows a
properly terminated signal while Figure 6-8 shows an improperly terminated signal.

Figure 6-7. Properly Terminated Signal Figure 6-8. Improperly Terminated Signal

To minimize reflection, use coaxial cable with matching characteristic impedance to the signal source. Terminate
the other end of the cable with the same-value terminator or resistor. For commonly used cables, RG59 has a
75Ω characteristic impedance, and RG58 has a 50Ω characteristic impedance.
6.3.3 Driving Capacitive Loads
Amplifiers driving capacitive loads can oscillate or have ringing at the output. To eliminate oscillation or reduce
ringing, place an isolation resistor as shown in Figure 6-9. The combination of the isolation resistor and the load
capacitor forms a pole to increase stability by adding more phase margin to the overall system. The desired
performance depends on the value of the isolation resistor; the bigger the isolation resistor, the more damped
the pulse response becomes. For LM7171, a 50Ω isolation resistor is recommended for initial evaluation. Figure
6-10 shows the LM7171 driving a 150pF load with the 50Ω isolation resistor.

Figure 6-9. Isolation Resistor Used to Drive Capacitive Load

Figure 6-10. The LM7171 Driving a 150pF Load With a 50Ω Isolation Resistor

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6.3.4 Power Dissipation


The maximum power allowed to dissipate in a device is defined as:

PD = (TJ(MAX) − TA) / θJA (2)

where
• PD is the power dissipation in a device
• TJ(max) is the maximum junction temperature
• TA is the ambient temperature
• RθJA is the thermal resistance of a particular package
For example, for the LM7171 in a SOIC-8 package, the maximum power dissipation at 25°C ambient
temperature is 730mW.
Thermal resistance, R θJA, depends on parameters such as die size, package size and package material. The
smaller the die size and package, the higher RθJA becomes. The 8-pin DIP package has a lower thermal
resistance (108°C/W) than that of 8-pin SOIC (172°C/W). Therefore, for higher dissipation capability, use an
8-pin DIP package.
The total power dissipated in a device can be calculated as:

PD = PQ + PL (3)

where
• PQ is the quiescent power dissipated in a device with no load connected at the output. PL is the power
dissipated in the device with a load connected at the output; PL is not the power dissipated by the load.
Furthermore,
• PQ is the supply current × total supply voltage with no load
• PL is the output current × (voltage difference between supply voltage and output voltage of the same side of
supply voltage)
For example, the total power dissipated by the LM7171 with VS = ±15V and output voltage of 10V into 1kΩ is

PD= PQ + PL (4)

= (6.5mA) × (30V) + (10mA) × (15V − 10V) (5)

= 195mW + 50mW (6)

= 245mW (7)

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6.4 Layout
6.4.1 Layout Guidelines
6.4.1.1 Printed Circuit Board and High-Speed Op Amps
There are many things to consider when designing printed circuit boards (PCBs) for high-speed op amps.
Without proper caution, excessive ringing, oscillation, and other degraded ac performance can easily occur
in high-speed circuits. As a rule, keep signal traces short and wide to provide low inductance and low
impedance paths. Ground any unused board space to reduce stray signal pickup. Ground critical components at
a common point to eliminate voltage drop. Sockets add capacitance to the board and can affect high-frequency
performance. Soldering the amplifier directly into the PCB without using any socket is better.
6.4.1.2 Using Probes
Active (FET) probes are an excellent choice for taking high-frequency measurements because of the wide
bandwidth, high input impedance, and low input capacitance. However, the probe ground leads provide a long
ground loop that produces errors in measurement. Instead, ground the probes directly by removing the ground
leads and probe jackets and using scope probe jacks.
6.4.1.3 Component Selection and Feedback Resistor
In high-speed applications, keep all component leads short. For discrete components, choose carbon
composition-type resistors and mica-type capacitors. Surface-mount components are preferred over discrete
components for minimum inductive effect.
Large values of feedback resistors can couple with parasitic capacitance and cause undesirable effects. such
as ringing or oscillation in high-speed amplifiers. For LM7171, a feedback resistor of 510Ω gives optimized
performance.

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7 Device and Documentation Support


7.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
7.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
7.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
7.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

7.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

8 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2014) to Revision D (February 2024) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Updated Package Information ........................................................................................................................... 1
• Deleted footnote from Recommended Operating Conditions.............................................................................3
• Changed DC and AC specifications tables to Electrical Characteristics: ±15V .................................................4
• Changed LM7171A unity-gain bandwidth from 200MHz to 160MHz..................................................................4
• Changed LM7171A settling time from 42ns to 16ns...........................................................................................4
• Changed LM7171 A Input-referred voltage noise from 14nV/√Hz to 8.5nV/√Hz................................................4
• Changed LM7171 A Input-referred current noise from 1.5pA/√Hz to 1pA/√Hz.................................................. 4
• Changed DC and AC specifications tables to Electrical Characteristics: ±5V ...................................................6
• Changed LM7171A slew rate from 950V/µs to 1200V/µs.................................................................................. 6
• Changed LM7171A phase margin from 57° to 68°.............................................................................................6
• Changed LM7171A settling time from 56ns to 15ns...........................................................................................6
• Changed LM7171A propagation delay from 6ns to 2.5ns.................................................................................. 6
• Changed LM7171A input-referred voltage noise from 14nV/√Hz to 8.5nV/√Hz................................................. 6
• Changed LM7171A input-referred current noise from 1.8pA/√Hz to 1pA/√Hz................................................... 6
• Added new Typical Characteristics section for LM7171A...................................................................................8
• Deleted second paragraph in Slew-Rate Limitation ........................................................................................ 24

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Changes from Revision B (March 2013) to Revision C (September 2014) Page


• Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Device
Information Table, Application and Implementation; Layout; Device and Documentation Support; Mechanical,
Packaging, and Ordering Information ................................................................................................................1

Changes from Revision A (March 2013) to Revision B (March 2013) Page


• Changed layout of National Data Sheet to TI format........................................................................................25

9 Mechanical, Packaging, and Orderable Information


The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com 11-Sep-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM7171AIMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (L71AIM, LM71) Samples
71AIM
LM7171BIN/NOPB ACTIVE PDIP P 8 40 RoHS & Green NIPDAU Level-1-NA-UNLIM -40 to 85 LM7171 Samples
BIN

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 11-Sep-2024

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS


K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)


QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM7171AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM7171BIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM7171AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM7171BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal


Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LM7171AIM/NOPB D SOIC 8 95 495 8 4064 3.05
LM7171BIM/NOPB D SOIC 8 95 495 8 4064 3.05
LM7171BIN/NOPB P PDIP 8 40 502 14 11938 4.32

Pack Materials-Page 3
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK


METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE


BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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