VHDL:

Sequential Logic
Modeling

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 Goals

• To understand the use of VHDL in modeling sequential logic.

• To learn the different VHDL models for finite state machines.

• To know how to model the different sequential elements: counters,

parallel to serial converters, and registers.

• To learn how to model D flip-flops.

• To get familiar with flip-flop basic delay times.

• To get familiar with datapath concepts.

• To get an introduction to the concept clock skew.

• To learn how to model the different types of memories (ROMs and
RAMs).

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 Sequential Circuits

• The output of a combinational circuit depends only on the inputs.

• The output of a sequential circuit depends on the inputs and the
current state of the circuit.
• A sequential value thus is able to store digital data in special storage
elements.

• Sequential circuits can be classified by their function into three main

types:
1. Finite State Machines (FSM) or (simple controllers).
2. Storage or memory elements.
3. Other types of specialized circuits, such as counters, etc.

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 Finite State Machines (FSMs)
• We are going to discuss only synchronous
FSMs where all changes in the circuit Combinational Moore
logic (C/L) outputs
occur on the edge of a clock signal.
• There are two types of FSM Inputs
outputs: Combinational Mealy
logic (C/L) outputs
– Moore (state-based) FSM:
The output depends only on
the present state. Combinational
logic (C/L)
– Mealy (transition-based) FSM:
The output depends on the Present Next
state q d state
present state and on inputs.
qn clock
• A single FSM could have one or both reset
of these output types.

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 Finite State Machines (FSMs) (Cont.)
• An FSM is described by its state diagram or state table.
• A clock input is assumed for synchronous FSM.

• A reset input is assumed for each FSM.

• Transitions between states occur after a clock edge when the state
register is updated.

• Every state must have an outgoing transition for every input

combination. As a convention, if an input combination is ignored at a
certain state, it is considered a don’t care input.

• Depending on the FSM type, outputs are either associated to states or

transitions outgoing from them. Missing outputs should be set to
zeros.

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 Modeling Finite-State Machines (FSMs) (Cont.)
• Four issues must be decided upon when modeling an FSM in VHDL:
1. Moore or Mealy type outputs
2. VHDL coding style
3. Resets and fail safe operation
4. State encoding
• VHDL description of FSM requires four tasks:
1. Asynchronous reset (RS)
2. Update current state register (CS)
3. Determine next state (NS)
4. Determine outputs (OP)
• The architecture of a FSM is done using one, two, or three processes:
– One process is not a common option.
– It is best to model an FSM using two or three processes.

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 Modeling Finite-State Machines (FSMs) (Cont.)
No. of processes One Two Three
Process No. P1 P1 P2 P1 P2 P3
√ √ √
RS
√ √ √
Tasks CS
√ √ √
NS
√ √ √
OP
Mealy Clock Clock CSs Clock CSs CSs
Reset Reset Inputs Reset Inputs Inputs
CSs
Sensitive to Inputs
Moore Clock Clock CSs Clock CSs CSs
Reset Reset Inputs Reset Inputs
CSs

Note: Asynchronous reset.

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 Modeling Finite-State Machines (FSMs) (Cont.)

• FSM must be initialized to a known state before first clock cycle.

– Use asynchronous reset to ensure that FSM is initialized to a
known state before first clock transition.
– Asynchronous reset is modelled using IF statement.
– Synchronous reset is modelled using IF or WAIT statements.

• Current state update could use IF or WAIT to monitor the rising edge
of the clock.

• Next state logic is done using CASE statement.

• Any CASE statement must handle all possible input combinations.

• Any CASE statement must cover all possible state values to control
the behavior of the state machine in unreachable states.

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 FSM State Definition
• Defining the states as a new TYPE that could be declared as follows:
1. In a PACKAGE,
2. In an ENTITY, or
3. In the declaration part of an ARCHITECTURE
• Defining the states as a new TYPE could be declared as:
1. Enumerated data type,
2. A constant representing each state, or
3. An integer type

• State encoding can be defined by the programmer or the synthesis

tool. Programmers could totally ignore state encoding.

• State encoding methods: sequential, Gray, Johnson, one-hot, etc.

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 FSM State Definition (Cont.)
No. Sequential Gray Johnson One-Hot
0 0000 0000 0000 0000 0000 0000 0000 0001
1 0001 0001 0000 0001 0000 0000 0000 0010
2 0010 0011 0000 0011 0000 0000 0000 0100
3 0011 0010 0000 0111 0000 0000 0000 1000
4 0100 0110 0000 1111 0000 0000 0001 0000
5 0101 0111 0001 1111 0000 0000 0010 0000
6 0110 0101 0011 1111 0000 0000 0100 0000
7 0111 0100 0111 1111 0000 0000 1000 0000
8 1000 1100 1111 1111 0000 0001 0000 0000
9 1001 1101 1111 1110 0000 0010 0000 0000
10 1010 1111 1111 1100 0000 0100 0000 0000
11 1011 1110 1111 1000 0000 1000 0000 0000
12 1100 1010 1111 0000 0001 0000 0000 0000
13 1101 1011 1110 0000 0010 0000 0000 0000
14 1110 1001 1100 0000 0100 0000 0000 0000
15 1111 1000 1000 0000 1000 0000 0000 0000

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 FSM State Definition (Cont.)
Example: 1 (Class) Show how to define 8 states in a package using an
enumerated data type. Use Gray encoding for states.
PACKAGE enumerated gray encoding IS

ATTRIBUTE enum enconding: string;

TYPE state IS
(ang 0, ang 1, ang 2, ang 3, ang 4, ang 5, ang 6, ang 7);

ATTRIBUTE enum enconding OF state: TYPE IS

"000 001 011 010 110 111 101 100";

END PACKAGE enumerated gray encoding;

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 FSM State Definition (Cont.)
Example: 2 (Class) Show how to define 8 states in a package using a
constant for each state. Use Johnson state encoding for states.
LIBRARY ieee;
USE ieee.std logic 1164.ALL;
USE ieee.numeric std.ALL;

PACKAGE const johnson encoding IS

CONSTANT ang 0: unsigned (3 DOWNTO 0) := "0000";
CONSTANT ang 1: unsigned (3 DOWNTO 0) := "0001";
CONSTANT ang 2: unsigned (3 DOWNTO 0) := "0011";
CONSTANT ang 3: unsigned (3 DOWNTO 0) := "0111";
CONSTANT ang 4: unsigned (3 DOWNTO 0) := "1111";
CONSTANT ang 5: unsigned (3 DOWNTO 0) := "1110";
CONSTANT ang 6: unsigned (3 DOWNTO 0) := "1100";
CONSTANT ang 7: unsigned (3 DOWNTO 0) := "1000";
END PACKAGE const johnson encoding;

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 Modeling Finite-State Machines (FSMs) (Cont.)
Example: 3 (Class) Show how to define 8 states in a package using an
integer for each state.
PACKAGE integer encoding IS

SUBTYPE state IS integer RANGE 0 TO 7;

END PACKAGE integer encoding;

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 FSM Coding Style
0/0 0/1
Example: 4 (Class) We want 1/1
to model an odd parity checker
even odd
as an FSM using VHDL.

LIBRARY ieee; reset 1/0

USE ieee.std logic 1164.ALL;
MEALY

ENTITY fsm IS 0 0
PORT( clk, reset: IN std logic; 1
x: IN std logic;
y: OUT std logic); even odd
END ENTITY fsm; [0] [1]

reset MOORE
1

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 FSM Coding Style: One Process Mealy
Example 4: (Cont.)
ARCHITECTURE mealy 1p OF fsm IS
TYPE state type IS (even, odd);
SIGNAL current state: state type;
BEGIN
same: PROCESS (clk, reset, current state, x) BEGIN
IF reset = ’1’ THEN
current state <= even;
ELSIF rising edge (clk) THEN
CASE current state IS
WHEN even =>
IF x = ’1’ THEN
current state <= odd;
ELSE
current state <= even;
END IF;
WHEN odd =>
IF x = ’1’ THEN
current state <= even;
ELSE
.
.
.

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 FSM Coding Style: One Process Mealy (Cont.)
Example.4: (Cont.)
.
.
current state <= odd;
END IF;
END CASE;
END IF;
CASE current state IS
WHEN even =>
IF x = ’1’ THEN
y <= ’1’;
ELSE
y <= ’0’;
END IF;
WHEN odd =>
IF x = ’1’ THEN
y <= ’0’;
ELSE
y <= ’1’;
END IF;
END CASE;
END PROCESS same;
END ARCHITECTURE mealy 1p;

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 FSM Coding Style: Two Processes Mealy
Example 4: (Cont.)

ARCHITECTURE mealy 2p OF fsm IS

TYPE state type IS (even, odd);
SIGNAL current state: state type;
SIGNAL next state: state type;
BEGIN
cs: PROCESS (clk, reset)
BEGIN
IF reset = ’1’ THEN
current state <= even;
ELSIF rising edge (clk) THEN
current state <= next state;
END IF;
END PROCESS cs;
.
.
.

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 FSM Coding Style: Two Processes Mealy (Cont.)
Example 4: (Cont.)
.
.
.
ns: PROCESS (current state, x) BEGIN
CASE current state IS
WHEN even =>
IF x = ’1’ THEN
y <= ’1’; next state <= odd;
ELSE
y <= ’0’; next state <= even;
END IF;
WHEN odd =>
IF x = ’1’ THEN
y <= ’0’; next state <= even;
ELSE
y <= ’1’; next state <= odd;
END IF;
END CASE;
END PROCESS ns;
END ARCHITECTURE mealy 2p;

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 FSM Coding Style: Three Processes Mealy
Example 4: (Cont.)

ARCHITECTURE mealy 3p OF fsm IS

TYPE state type IS (even, odd);
SIGNAL current state: state type;
SIGNAL next state: state type;
BEGIN
cs: PROCESS (clk, reset)
BEGIN
IF reset = ’1’ THEN
current state <= even;
ELSIF rising edge (clk) THEN
current state <= next state;
END IF;
END PROCESS cs;
.
.
.

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 FSM Coding Style: Three Processes Mealy (Cont.)
Example 4: (Cont.)
.
.
.
ns: PROCESS (current state, x)
BEGIN
CASE current state IS
WHEN even =>
IF x = ’1’ THEN
next state <= odd;
ELSE
next state <= even;
END IF;
WHEN odd =>
IF x = ’1’ THEN
next state <= even;
ELSE
next state <= odd;
END IF;
END CASE;
END PROCESS ns;
.
.
.

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 FSM Coding Style: Three Processes Mealy (Cont.)
Example 4: (Cont.)
.
.
.
op: PROCESS (current state, x)
BEGIN
CASE current state IS
WHEN even =>
IF x = ’1’ THEN
y <= ’1’;
ELSE
y <= ’0’;
END IF;
WHEN odd =>
IF x = ’1’ THEN
y <= ’0’;
ELSE
y <= ’1’;
END IF;
END CASE;
END PROCESS OP;
END ARCHITECTURE mealy 3p;

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 FSM Coding Style: One Process Moore
Example 4: (Cont.)

ARCHITECTURE moore 1p OF fsm IS

TYPE state type IS (even, odd);
SIGNAL current state: state type;
BEGIN
same: PROCESS (clk, reset, current state)
BEGIN
IF reset = ’1’ THEN
current state <= even;
ELSIF rising edge (clk) THEN
CASE current state IS
WHEN even =>
IF x = ’1’ THEN
current state <= odd;
ELSE
current state <= even;
END IF;
.
.
.

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 FSM Coding Style: One Process Moore (Cont.)
Example 4: (Cont.)

.
.
.
WHEN odd =>
IF x = ’1’ THEN
current state <= even;
ELSE
current state <= odd;
END IF;
END CASE;
END IF;
CASE current state IS
WHEN even =>
y <= ’0’;
WHEN odd =>
y <= ’1’;
END CASE;
END PROCESS same;
END ARCHITECTURE moore 1p;

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 FSM Coding Style: Two Processes Moore
Example 4: (Cont.)

ARCHITECTURE moore 2p OF fsm IS

TYPE state type IS (even, odd);
SIGNAL current state: state type;
SIGNAL next state: state type;
BEGIN
cs: PROCESS (clk, reset)
BEGIN
IF reset = ’1’ THEN
current state <= even;
ELSIF rising edge (clk) THEN
current state <= next state;
END IF;
END PROCESS cs;
.
.
.

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 FSM Coding Style: Two Processes Moore (Cont.)
Example.4: (Cont.)
.
.
ns: PROCESS (current state, x)
BEGIN
CASE current state IS
WHEN even =>
y <= ’0’;
IF x = ’1’ THEN
next state <= odd;
ELSE
next state <= even;
END IF;
WHEN odd =>
y <= ’1’;
IF x = ’1’ THEN
next state <= even;
ELSE
next state <= odd;
END IF;
END CASE;
END PROCESS ns;
END ARCHITECTURE moore 2p;

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 FSM Coding Style: Three Processes Moore
Example 4: (Cont.)

ARCHITECTURE moore 3p OF fsm IS

TYPE state type IS (even, odd);
SIGNAL current state: state type;
SIGNAL next state: state type;
BEGIN
cs: PROCESS (clk, reset)
BEGIN
IF reset = ’1’ THEN
current state <= even;
ELSIF rising edge (clk) THEN
current state <= next state;
END IF;
END PROCESS cs;
.
.
.

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 FSM Coding Style: Three Processes Moore (Cont.)
Example 4: (Cont.)
.
.
.
ns: PROCESS (current state, x)
BEGIN
CASE current state IS
WHEN even =>
IF x = ’1’ THEN
next state <= odd;
ELSE
next state <= even;
END IF;
WHEN odd =>
IF x = ’1’ THEN
next state <= even;
ELSE
next state <= odd;
END IF;
END CASE;
END PROCESS ns;
.
.
.

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 FSM Coding Style: Three Processes Moore (Cont.)
Example 4: (Cont.)
.
.
.
op: PROCESS (current state)
BEGIN
CASE current state IS
WHEN even =>
y <= ’0’;
WHEN odd =>
y <= ’1’;
END CASE;
END PROCESS op;
END ARCHITECTURE moore 3p;

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 FSM Coding Style: Sample Testbench
Example 4: (Cont.)
LIBRARY ieee;
USE ieee.std logic 1164.ALL;
ENTITY fsm tb IS
END ENTITY fsm tb;
ARCHITECTURE tb arch OF fsm tb IS
COMPONENT fsm IS
PORT( clk, reset: IN std logic;
x: IN std logic;
y: OUT std logic);
END COMPONENT fsm;
SIGNAL clk, reset, x, y: std logic;
FOR fsm mealy 2p: fsm USE ENTITY work.fsm (mealy 2p);
BEGIN
clock: PROCESS IS
BEGIN
clk <= ’0’, ’1’ AFTER 10 ns;
WAIT FOR 20 ns;
END PROCESS clock;
.
.
.

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 FSM Coding Style: Sample Testbench (Cont.)
Example.4: (Cont.)
.
.
sg: PROCESS IS
BEGIN
reset <= ’1’;
WAIT FOR 10 ns;
ASSERT y = ’0’
REPORT "Error: Reset"
SEVERITY warning;
reset <= ’0’; x <= ’0’;
WAIT FOR 10 ns;
ASSERT y = ’0’
REPORT "Error: state even when x = 0"
SEVERITY warning;
WAIT FOR 10 ns;
x <= ’1’;
WAIT FOR 10 ns;
ASSERT y = ’1’
REPORT "Error: state even when x = 1"
SEVERITY warning;
.
.
.

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 FSM Coding Style: Sample Testbench (Cont.)
Example 4: (Cont.)
.
.
.
WAIT FOR 10 ns;
x <= ’0’;
WAIT FOR 10 ns;
ASSERT y = ’1’
REPORT "Error: state odd when x = 0"
SEVERITY warning;
WAIT FOR 10 ns;
x <= ’1’;
WAIT FOR 10 ns;
ASSERT y = ’0’
REPORT "Error: state odd when x = 1"
SEVERITY warning;
WAIT;
END PROCESS sg;
fsm mealy 2p: fsm PORT MAP (clk, reset, x, y);
END ARCHITECTURE tb arch;

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 FSM Coding Style: Sample Output
Example 4: (Cont.)

clk

reset

Next state even odd even odd

Current state even odd even

y (Mealy)

y (Moore)

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 Modeling Finite-State Machines (FSMs) (Cont.)
cw . ccw
Example: 5 (Class) Encode cw . ccw Inputs: cw, ccw
the shown FSM using VHDL. cw . ccw Output: angle
0
The machine has a
synchronous reset input. cw . ccw ang_0
7 1
ang_1
Use Johnson state ang_7
encoding for states
through the previously
6 ang_6 ang_2 2
defined package.
Use a three-process
coding style.
ang_5 ang_3
5 ang_4 3

ccw: counter clock wise cw: clock wise

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 Modeling Finite-State Machines (FSMs) (Cont.)
Example 5: (Cont.)
LIBRARY ieee;
USE ieee.std logic 1164.ALL;
USE ieee.numeric std.ALL;
USE work.const johnson encoding.ALL;
ENTITY angle IS
PORT( clk, reset, cw, ccw: IN std logic;
angle: OUT std logic vector (2 DOWNTO 0));
END ENTITY angle;
ARCHITECTURE angle OF angle IS
SIGNAL current state, next state: unsigned (3 DOWNTO 0);
BEGIN -- states have same number of bits as the encoding of ang 0, etc.
cs: PROCESS IS BEGIN
WAIT UNTIL rising edge (clk);
IF reset = ’1’ THEN -- synchronous reset
current state <= ang 0;
ELSE
current state <= next state;
END IF;
END PROCESS cs;
.
.
.

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 Modeling Finite-State Machines (FSMs) (Cont.)
Example 5: .(Cont.)
.
.
ns: PROCESS (current state, cw, ccw) IS BEGIN
CASE current state IS
WHEN ang 0 =>
IF cw = ’1’ AND ccw = ’0’ THEN
next state <= ang 1;
ELSIF cw = ’0’ AND ccw = ’1’ THEN
next state <= ang 7;
ELSE
next state <= ang 0;
END IF;
WHEN ang 1 =>
IF cw = ’1’ AND ccw = ’0’ THEN
next state <= ang 2;
ELSIF cw = ’0’ AND ccw = ’1’ THEN
next state <= ang 0;
ELSE
next state <= ang 1;
END IF;
.
.
.

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 Modeling Finite-State Machines (FSMs) (Cont.)
Example 5: (Cont.)
.
.
.
WHEN ang 7 =>
IF cw = ’1’ AND ccw = ’0’ THEN
next state <= ang 0;
ELSIF cw = ’0’ AND ccw = ’1’ THEN
next state <= ang 6;
ELSE
next state <= ang 7;
END IF;
WHEN OTHERS =>
next state <= ang 0;
END CASE;
END PROCESS ns;
.
.
.

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 Modeling Finite-State Machines (FSMs) (Cont.)
Example 5: (Cont.)
.
.
.
op: PROCESS (current state) IS
BEGIN
CASE current state IS
WHEN ang 0 => angle <= o"0";
WHEN ang 1 => angle <= o"1";
WHEN ang 2 => angle <= o"2";
WHEN ang 3 => angle <= o"3";
WHEN ang 4 => angle <= o"4";
WHEN ang 5 => angle <= o"5";
WHEN ang 6 => angle <= o"6";
WHEN ang 7 => angle <= o"7";
WHEN OTHERS => NULL;
END CASE;
END PROCESS op;
END ARCHITECTURE angle;

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 Counters
Example: 6 (Class) Model an n-bit binary up/down counter with
synchronous clear and preset.
LIBRARY ieee;
USE ieee.std logic 1164.ALL;
USE ieee.numeric std.ALL;

ENTITY bin counter IS

GENERIC( n: positive := 4);
PORT( clk, clear, preset, up down: IN std logic;
d in: IN unsigned (n-1 DOWNTO 0);
d out: OUT unsigned (n-1 DOWNTO 0));
END ENTITY bin counter;
ARCHITECTURE behav OF bin counter IS
SIGNAL counter: unsigned (n-1 DOWNTO 0);
BEGIN
.
.
.

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 Counters (Cont.)
Example 6: (Cont.)
.
.
.
ct: PROCESS (clk) IS BEGIN
IF rising edge (clk) THEN
IF clear = ’1’ THEN
counter <= (OTHERS => ’0’);
ELSIF preset = ’1’ THEN
counter <= d in;
ELSIF up down = ’1’ THEN
counter <= counter + 1;
ELSE
counter <= counter - 1;
END IF;
END IF;
END PROCESS ct;
d out <= counter;
END ARCHITECTURE behav;

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 Counters (Cont.)
Example: 7 (Class) Model an n-bit Gray up/down counter with
synchronous clear.
LIBRARY ieee;
USE ieee.std logic 1164.ALL;
USE ieee.numeric std.ALL;

ENTITY gray counter IS

GENERIC( n: positive := 4);
PORT( clk, clear, up down: IN std logic;
d out: OUT std logic vector (n-1 DOWNTO 0));
END ENTITY gray counter;
ARCHITECTURE behav OF gray counter IS
COMPONENT bin counter IS
GENERIC( n: positive := 4);
PORT( clk, clear, up down: IN std logic;
preset: IN std logic;
d in: IN unsigned (n-1 DOWNTO 0) := (OTHERS => ’0’);
d out: OUT unsigned (n-1 DOWNTO 0));
END COMPONENT bin counter;
.
.
.

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 Counters (Cont.)
Example.7: (Cont.)
.
.
FOR ALL: bin counter USE ENTITY WORK.bin counter (behav);

SIGNAL d bin: unsigned (n-1 DOWNTO 0);

BEGIN
bcount: bin counter GENERIC MAP( n => 4)
PORT MAP( clk => clk, clear => clear
up down => up down, preset => ’0’,
d in => OPEN, d out => d bin);
gray: PROCESS (d bin) IS
BEGIN
d out(n-1) <= d bin(n-1);
FOR j IN n-2 DOWNTO 0 LOOP
d out(j) <= d bin (j+1) XOR d bin (j);
END LOOP;
END PROCESS gray;
END ARCHITECTURE behav;

Notice that if an input port is to be left open, a default value must be

specified for it.

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 Parallel to Serial Converter
Example: 8 (Class) A parallel to serial converter that scans out the MSB first.
ENTITY p2s IS
GENERIC( n: positive := 4);
PORT( d in: IN bit vector (0 TO n-1);
clk, load, shift: IN bit;
d out: OUT bit);
END ENTITY p2s;
ARCHITECTURE shift OF p2s IS
SIGNAL save: bit vector (0 TO n-1);
BEGIN
ps: PROCESS (clk) IS BEGIN
IF clk = ’1’ AND clk’event THEN
IF load = ’1’ THEN
save <= d in;
ELSIF shift = ’1’ THEN
save <= save (1 TO n-1) & ’0’;
END IF;
END IF;
END PROCESS ps;
d out <= save(0);
END ARCHITECTURE shift;

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 Flip-Flops
Example: 9 (Class) Model a negative edge-triggered D flip-flop with
select input.
LIBRARY ieee;
USE ieee.std logic 1164.ALL;
ENTITY d ff sel IS
PORT( d1, d0, sd, clk: IN std logic;
q, qn: OUT std logic);
END ENTITY d ff sel; d1 q
ARCHITECTURE sel OF d ff sel IS
BEGIN
sl: PROCESS IS d0
BEGIN
WAIT UNTIL falling edge (clk);
IF sd = ’1’ THEN
q <= d1; qn < = NOT d1;
sd
ELSE
q <= d0; qn < = NOT d0;
clk qn
END IF;
END PROCESS sl;
END ARCHITECTURE sel;

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 Flip-Flops (Cont.)
Example: 10 (Class) Model a positive edge-triggered D flip-flop with
asynchronous clear and set.
LIBRARY ieee;
USE ieee.std logic 1164.ALL;
ENTITY d ff async IS
PORT( clk, clear, set: IN std logic;
d in: IN std logic;
d out: OUT std logic);
END ENTITY d ff async;
ARCHITECTURE async OF d ff async IS BEGIN
asr: PROCESS (clk, clear, set) IS BEGIN
IF clear = ’1’ THEN
d out <= ’0’;
ELSIF set = ’1’ THEN
d out <= ’1’;
ELSIF rising edge (clk) THEN
d out <= d in;
END IF;
END PROCESS asr;
END ARCHITECTURE async;

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 Flip-Flops (Cont.)
Example: 11 (Class) Repeat Example 10 with synchronous clear and set.
LIBRARY ieee;
USE ieee.std logic 1164.ALL;
ENTITY d ff sync IS
PORT( clk, clear, set: IN std logic;
d in: IN std logic;
d out: OUT std logic);
END ENTITY d ff sync;
ARCHITECTURE sync OF d ff sync IS BEGIN
ssr: PROCESS IS BEGIN
WAIT UNTIL rising edge (clk);
IF clear = ’1’ THEN
d out <= ’0’;
ELSIF set = ’1’ THEN
d out <= ’1’;
ELSE
d out <= d in;
END IF;
END PROCESS ssr;
END ARCHITECTURE sync;

Copyright © 2002-2020 VHDL: Sequential Logic Modeling 45 of 65

 Flip-Flops (Cont.)
• Setup time ts : Minimum time during which data must be stable
prior to a clock edge.
• Hold time th : Minimum time during which input data must be stable
after a clock edge. You cannot sample output date during this time.
Hold times are usually either 0 or very small.
setup time ts

clock
hold time th

Propagation delay td

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 Flip-Flops (Cont.)
• Propagation delay td : Time to produce correct result of the circuit
measured from the clock edge.

• Clock skew T cs: Arrival of a clock signal at the clock inputs of

different flip-flops at different times as a result of propagation delays.
• Given two adjacent flip-flops, i and j, the clock skew between them
(T csi,j ) is defined as T csi,j = T csi − T csj , where T csi and T csj
are the clock delays from the clock source to i and j, respectively.
Propagation delay
Register
Data in Data out

Combinational
logic

Clock, set, reset signals

Clock period >= td + combinational logic propagation delay + ts + 2 × T cs

Copyright © 2002-2020 VHDL: Sequential Logic Modeling 47 of 65
 Flip-Flops (Cont.)
Example: 12 (Class) Model a D flip-flop with setup, hold, and delay times.
ENTITY d ff IS
GENERIC( setup, hold: time := 0.1 ns; delay: time := 2 ns);
PORT( d, clk: IN bit;
q: OUT bit);
END ENTITY d ff;
ARCHITECTURE d ff OF d ff IS BEGIN
q <= d AFTER delay WHEN clk = ’1’ AND clk’event;
check setup: PROCESS IS BEGIN
WAIT UNTIL clk = ’1’ AND clk’event;
ASSERT d’last event >= setup -- Same as d’stable (setup)
REPORT "setup violation"
SEVERITY warning;
END PROCESS check setup;
check hold: PROCESS IS BEGIN
WAIT UNTIL clk’delayed (hold) = ’1’ AND clk’delayed (hold)’EVENT;
ASSERT d’stable (hold) -- Same as d’last event >= hold
REPORT "hold violation"
SEVERITY warning;
END PROCESS check hold;
END ARCHITECTURE d ff;

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 Flip-Flops (Cont.)
Example 12: (Cont.)
ENTITY dff test IS
END ENTITY dff test;
ARCHITECTURE test OF dff test IS
COMPONENT d ff IS
GENERIC( delay: time := 4 ns;
setup: time := 3 ns;
hold: time := 1 ns);
PORT( d, clk: IN bit;
q: OUT bit);
END COMPONENT d ff;
FOR gate: d ff USE ENTITY WORK.d ff (basic);
SIGNAL d in, clock, d out: bit;
BEGIN
gate: d ff GENERIC MAP( delay => 4 ns,
setup => 3 ns,
hold => 1 ns)
PORT MAP( d => d in,
clk => clock,
q => d out);
END ARCHITECTURE test;

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 Registers
Example: 13 (Class) Model a shift register to perform the operations in
the table below. A zero asynchronous clr signal resets all output bits.
Function Control inputs (s1, s0) q[3] q[2] q[1] q[0]
Hold value 00 q[3] q[2] q[1] q[0]
Shift left 01 q[2] q[1] q[0] r in
Shift right 10 l in q[3] q[2] q[1]
Load 11 d[3] d[2] d[1] d[0]

LIBRARY ieee;
USE ieee.std logic 1164.ALL;
ENTITY sr IS
GENERIC( width: positive := 4);
PORT( clk, clr, l in, r in, s0, s1: IN std logic;
d: IN std logic vector (width-1 DOWNTO 0);
q: INOUT std logic vector (width-1 DOWNTO 0));
END ENTITY sr;
.
.
.

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 Registers (Cont.)
Example 13: (Cont.)
.
.
.
ARCHITECTURE sr OF sr IS
BEGIN
shift: PROCESS (clk, clr) IS
VARIABLE sel: std logic vector (1 DOWNTO 0);
BEGIN
IF clr = ’0’ THEN
q <= (OTHERS => ’0’);
ELSIF rising edge (clk) THEN
sel := s1 & s0;
CASE sel IS
WHEN "00" => NULL;
WHEN "01" => q <= q(width-2 DOWNTO 0) & r in;
WHEN "10" => q <= l in & q(width-1 DOWNTO 1);
WHEN "11" => q <= d;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS shift;
END ARCHITECTURE sr;

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 ROMs
Example: 14 (Class) Show how to use a ROM component that was
designed using standard cells.
.
.
.
COMPONENT ROM IS
PORT( en: IN std logic;
address: IN unsigned (m-1 DOWNTO 0);
q: OUT std logic vector (n-1 DOWNTO 0));
END COMPONENT ROM;
SIGNAL enable: std logic;
SIGNAL address bus: unsigned (m-1 DOWNTO 0);
SIGNAL data bus: std logic vector (n-1 DOWNTO 0);
BEGIN
r1: ROM( en => enable, address => address bus, q => data bus);
.
.
.

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 ROMs (Cont.)
Example: 15 (Class) Use a ROM to build a squaring circuit. Use a flag
to ensure that the ROM is initialize only one time.

LIBRARY ieee;
USE ieee.std logic 1164.ALL;
USE ieee.numeric std.ALL;

ENTITY rom IS
GENERIC( n: integer := 3;
m: integer := 6);
PORT( enable: IN std logic;
address: IN unsigned (n-1 DOWNTO 0);
data: OUT unsigned (m-1 DOWNTO 0));
END ENTITY rom;
.
.
.

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 Example 15: (Cont.)
ROMs (Cont.)
.
.
.
ARCHITECTURE flag arch OF rom IS
TYPE rm IS ARRAY (0 TO 2**n-1) OF unsigned (m-1 DOWNTO 0);
SIGNAL word: rm;
SIGNAL initialized: boolean := false;
BEGIN
memory: PROCESS (enable, address) IS BEGIN
IF NOT initialized THEN
FOR index IN word’range LOOP
word(index) <= to unsigned(index*index, m);
END LOOP;
ASSERT FALSE REPORT "ROM init in flag arch" SEVERITY note;
initialized <= true;
END IF;
IF enable = ’1’ THEN
data <= word(to integer(address));
ELSE
data <= (OTHERS => ’Z’);
END IF;
END PROCESS memory;
END ARCHITECTURE flag arch;

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 ROMs (Cont.)
Example: 16 (Class) Repeat Example 15 using a LOOP statement.
ARCHITECTURE loop arch OF rom IS
TYPE rm IS ARRAY (0 TO 2**n-1) OF unsigned (m-1 DOWNTO 0);
SIGNAL word: rm;
BEGIN
memory: PROCESS IS
BEGIN
FOR index IN word’range LOOP
word(index) <= to unsigned(index*index, m);
END LOOP;
ASSERT FALSE REPORT "ROM init in loop arch" SEVERITY note;
LOOP
WAIT ON enable, address;
IF enable = ’1’ THEN
data <= word(to integer(address));
ELSE
data <= (OTHERS => ’Z’);
END IF;
END LOOP;
END PROCESS memory;
END ARCHITECTURE loop arch;

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 ROMs (Cont.)
Example: 17 (Class) Rewrite the architecture in Example 15 using a
separate process without a sensitivity list to initialize the ROM.

ARCHITECTURE init process arch OF rom IS

TYPE rm IS ARRAY (0 TO 2**n-1) OF unsigned (m-1 DOWNTO 0);
SIGNAL word: rm;
SIGNAL initialized: boolean := false;
BEGIN
init wait proc: PROCESS IS
BEGIN
FOR index IN word’range LOOP
word(index) <= to unsigned(index*index, m);
END LOOP;
ASSERT FALSE REPORT "ROM init in init wait proc" SEVERITY note;
initialized <= true;
WAIT;
END PROCESS init wait proc;
.
.
.

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 ROMs (Cont.)
Example 17: (Cont.)

.
.
.
memory: PROCESS (initialized, enable, address) IS
BEGIN
IF initialized THEN
IF enable = ’1’ THEN
data <= word(to integer(address));
ELSE
data <= (OTHERS => ’Z’);
END IF;
END IF;
END PROCESS memory;
END ARCHITECTURE init process arch;

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 ROMs (Cont.)
Example: 18 (Class) Rewrite the initializing process in Example 17
using a sensitivity list.
.
.
.
init sens proc: PROCESS (initialized) IS
BEGIN
IF NOT initialized THEN
FOR index IN word’range LOOP
word(index) <= to unsigned(index*index, m);
END LOOP;
ASSERT FALSE REPORT "ROM init in init sens proc" SEVERITY note;

initialized <= true;

END IF;
END PROCESS init sens proc;
.
.
.

Note: This process will actually run twice. But, the ROM itself will be
initialized only once.

Copyright © 2002-2020 VHDL: Sequential Logic Modeling 58 of 65

 ROMs (Cont.)
Example: 19 (Class) Repeat Example 15, initializing the ROM with a function.
ARCHITECTURE funct arch OF rom IS
TYPE rm IS ARRAY (0 TO 2**n-1) OF unsigned (m-1 DOWNTO 0);
FUNCTION rom fill RETURN rm IS
VARIABLE memory: rm;
BEGIN
FOR index IN memory’range LOOP
memory(index) := to unsigned(index*index, m);
END LOOP;
ASSERT FALSE REPORT "ROM init in funct arch" SEVERITY note;
RETURN memory;
END FUNCTION rom fill;
constant word: rm := rom fill;
BEGIN
memory: PROCESS (enable, address) IS BEGIN
IF enable = ’1’ THEN
data <= word(to integer(address));
ELSE
data <= (OTHERS => ’Z’);
END IF;
END PROCESS memory;
END ARCHITECTURE funct arch;

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 ROMs (Cont.)
Example: 20 (Class) Rewrite the function in Example 19, initializing the
ROM from a text file.
LIBRARY ieee;
USE std.textio.ALL;
USE ieee.std logic textio.ALL;
.
.
.
IMPURE FUNCTION rom fill RETURN rm IS
VARIABLE memory: rm;
FILE f: text OPEN READ MODE IS "rom.txt";
VARIABLE l: line;
VARIABLE read word: std logic vector (m-1 DOWNTO 0);
BEGIN
FOR index IN memory’range LOOP
readline (f, l);
read (l, read word); -- cannot read unsigned values from a file
memory(index) := unsigned(read word);
END LOOP;
ASSERT FALSE REPORT "ROM init in funct arch & file" SEVERITY note;
RETURN memory;
END FUNCTION rom fill;

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 ROMs (Cont.)
Example: 21 (Class) Repeat Example 15, initializing the ROM using a
generate statement.

ARCHITECTURE gen arch OF rom IS

TYPE rm IS ARRAY (0 TO 2**n-1) OF unsigned (m-1 DOWNTO 0);
SIGNAL word: rm;
BEGIN
contents: FOR index IN word’range GENERATE
word(index) <= to unsigned(index*index, m);
END GENERATE contents;

data <= word(to integer(address)) WHEN enable = ’1’ ELSE

(OTHERS => ’Z’);
END ARCHITECTURE gen arch;

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 RAMs
Example: 22 (Class) Show how to model an n-bit address, m-bit word
size, dual-port RAM. n
address_out
LIBRARY ieee;
n
USE ieee.std logic 1164.ALL; address_in m
m RAM data_out
USE ieee.numeric std.ALL;
data_in
ENTITY dual port ram IS
GENERIC( n: positive := 4; r
m: positive := 4); w
PORT( r, w: IN std logic;
address in: IN unsigned (n-1 DOWNTO 0);
address out: IN unsigned (n-1 DOWNTO 0);
data in: IN std logic vector (m-1 DOWNTO 0);
data out: OUT std logic vector (m-1 DOWNTO 0));
END ENTITY dual port ram;
.
.
.

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 RAMs (Cont.)
Example 22: (Cont.)
.
.
.
ARCHITECTURE behav OF dual port ram IS
BEGIN
memory: PROCESS (r, w, address in, address out, data in) IS
TYPE rm IS ARRAY (0 TO 2**n-1) OF std logic vector (m-1 DOWNTO 0);
VARIABLE word: rm;
BEGIN
IF w = ’1’ THEN -- write location in memory
word(to integer(address in)) := data in;
END IF;

IF r = ’1’ THEN -- read location in memory

data out <= word(to integer(address out));
END IF;
END PROCESS memory;
END ARCHITECTURE behav;

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 RAMs (Cont.)
Example: 23 (Class) Show how to model an n-bit address, m-bit word
size, single-port RAM.
LIBRARY ieee;
USE ieee.std logic 1164.ALL;
n
address
USE ieee.numeric std.ALL; m
RAM data
enable
ENTITY single port ram IS
GENERIC( n: positive := 4; rw
m: positive := 4);
PORT( rw, enable: IN std logic;
address: IN unsigned (n-1 DOWNTO 0);
data: INOUT std logic vector (m-1 DOWNTO 0));
END ENTITY single port ram;
.
.
.

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 RAMs (Cont.)
Example 23: (Cont.)
.
.
.
ARCHITECTURE behav OF single port ram IS BEGIN
memory: PROCESS (rw, enable, address, data) IS
TYPE rm IS ARRAY (0 TO 2**n-1) OF std logic vector (m-1 DOWNTO 0);
VARIABLE word: rm;
BEGIN
data <= (OTHERS => ’Z’);
IF enable = ’1’ THEN
IF rw = ’1’ THEN -- write location in memory
word(to integer(address)) := data;
ELSE -- read location in memory
data <= word(to integer(address));
END IF;
END IF;
END PROCESS memory;
END ARCHITECTURE behav;

Example: 24 (Home) Explain why data is all driven to Z at the

beginning of the process in Example 23.

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