Useful ECO Commands:

The very first command to analyze any cell's size/variant change behavior is estimate_eco. It is available
only in pt_shell. We can estimate what the trans/cap/timing will be if we change a particular cell's
size/variant.
estimate_eco gtfavdecpak11/aitunit1/U90 -lib_c e08nanb02ad2n01x3

The default estimate_eco cmd does not show the trans and cap of the cells, if you are fixing trans/cap,
make sure you enable them using the following cmd.
set eco_estimation_output_columns "transition max_transition area stage_delay arrival slack
max_capacitance"

Once we decide on any cell's size change or variant, we can use following cmd to actually change it. It
is used for both upsizing/downsizing and VT swaps.
size_cell gtlscbanktop1/lscl1bankunit1/prects_opt_HFSBUF_26651_669982 HDBULTLL06_BUF_CB3Q_6
A Word of caution: Make sure not to change any clock cells' VT variant while sizing the clock cell.

In tsmc n5, we have following swap cells available.

ult : fastest cell, highest power consumption (ultra low vt)
ultll : 2nd fastest cell, little lower power consumption than ult (ultra low vt, low leakage)
lvt : balanced cell in terms of power and speed (low vt)
lvtll : 2nd slowest cell, higher power consumption than svt (low vt, low leakage)
svt : slowest cell, lowest power consumption (standard vt)

Hence, we can size a buffer HDBULTLL06_BUF_CB3Q_6 to its fastest variant as follows:

size_cell gtlscbanktop1/lscl1bankunit1/prects_opt_HFSBUF_26651_669982 HDBULT06_BUF_CB3Q_6

Following insert buffer command is used for hold fixing or inserting a buffer in LV HSD.
insert_buffer
lscsbusxlator2/xlator_core1/autovector_ex_read_xpose_addr1_reg[7]_MBIT_ex_read_xpose_addr1_re
g[6]/SI HDBLVTLL06_BUF_1 \
-new_net_names ww31p5_lv_net1 \
-new_cell_names ww31p5_lv_cell_1 \
-location {20.1960 152.0400}

TIP: If you are writing an stcl to fix hold in next man eco, as this cmd inserts the buffer on specified pin
location, you can skip the -location switch and the tool will try to place the buffer on nearby legal
location.
A word of caution: this command disturbs the net's (which is connected to the specified pin) routing as
it does not add the buffer by splitting existing net. Instead, it adds the buffer at the end of current net.
Hence, it is not preferred for setup/trans fixing.

set_cell_location -coordinates {20.1960 152.0400} -orientation R0 [get_flat_cells *ww31p5_lv_cell_1*]

The set cell location cmd is used to specify the correct orientation of the new cell on the specified
location. If the orientation is wrong, we will end up with PG shorts.
The M0 grid, where power pins of a std cell are connected, is generally alternating between VCC-VSS-
VCC-VSS M0 horizontal metal layers. The orientation of the cell comes into play in deciding where the
power pins of the cell will fall. If VCC pin falls on VSS M0 track, we will end up shorting the VCC of the
cell with VSS of the circuit.

Adding a buffer on a net at specified intervals: Used in trans fixing of a net or improve setup delay by
splitting high-delay long nets.
Please avoid giving this cmd to LV HSD, instead use insert_buffer cmd.
add_buffer_on_route [get_nets gtlscpar_rptunit1/ropt_net_1265494] \
-punch_port \
-lib_cell HDBULT06_BUF_CAQDCY2_10 \
-repeater_distance_length_ratio 0.34 \
-first_distance_length_ratio 0.34

TIP: There are more number of ways with which we can provide the repeater distance spec in this
command, do man on this command to know the same.
A word of caution: In case of filing LV HSD, always make sure you give the net change commands if
needed or new net stcl along with the new cell locations.

To remove buffers from a path: instead of using remove_cells, this is a much cleaner way of removing
the buffers/inv-pair without disturbing the routing.
remove_buffers { daprssunit1/daprss_arb1/pr_pteco_hold1_PTECO_HOLD_BUF2161 }
To duplicate any cell and split the fanouts use following cmd: this is a generic cmd that can be used
either on clock or data signals. The connect loads is used to connect the existing loads from the original
driver to the new driver.
util::duplicate_cell -ref_cell gtlscbanktop1/lscl1bankunit0/clkgate_rtl_clk_gate_latch_icg_0 \
-location {234.1920 248.4300} \
-ref_name HDBULTLL06_CKGTPLT_CAQV5Y4_16 \
-connect_loads [get_pins
{{gtlscbanktop1/lscl1bankunit0/loop[0].gcl_clk_gate_and1_ctech_lib_clk_and_en_ctech_lib_dt_dcszo/
CK}
{gtlscbanktop1/lscl1bankunit0/loop[1].gcl_clk_gate_and1_ctech_lib_clk_and_en_ctech_lib_dt_dcszo/
CK} {gtlscbanktop1/lscl1bankunit0/pwc_clk_gate_wrdata_f_reg_0_latch_icg_0/CK}}]

set_cell_location [get_cells gtlscbanktop1/lscl1bankunit0/clkgate_rtl_clk_gate_latch_icg_0_split_1] -

coordinates {234.1920 248.4300} -orientation MX
set_fixed_objects [get_cells gtlscbanktop1/lscl1bankunit0/clkgate_rtl_clk_gate_latch_icg_0_split_1]

A word of Caution: While using the util::duplicate cmd, always give the connect loads list very carefully,
if a wrong pin is given in list, it will result in functional failure of the circuit (Gate2gate FEV will fail).

Alternative cmd to util::duplicate_cell for CTM

eco::split_ctm_drivers -help
Usage: eco::split_ctm_drivers # Split CTM driver.
-suffix suffix of split driver
-drivers drivers (collection of drivers (output pins))
[-dontuse_lib_cells dont_use_cells]
(dont_use lib cells list)
[-skip_fb_rebuild] (only splitting, don't rebuild fb)
[-nonctm] (insert buffers instead of splitting)

A word of Caution: eco::split_ctm_drivers may create an extra level in the clock path. Make sure to
check 1_26 and timing margins if using this cmd.

To reroute any clock nets using command:

eco::reroute_ctm_nets -check_slope -nets [get_nets
{gtlscbanktop1/lscl1bankunit0/lscl1_alloc_pipe1/lscl1_tagcmp1/gclk_tagram[17]
gtlscbanktop1/lscl1bankunit0/lscl1_alloc_pipe1/lscl1_tagcmp1/gclk_tagram[17]_split_1
gtlscbanktop1/lscl1bankunit0/lscl1_alloc_pipe1/lscl1_tagcmp1/gclk_tagram[26]_split_1
gtlscbanktop1/lscl1bankunit0/lscl1_alloc_pipe1/lscl1_tagcmp1/gclk_tagram[26]
dfddfxgtlscparunit1/split dfddfxgtlscparunit1/cfg_latch_gclk_161}]

To reroute signal nets using ctm router (very good router but can destroy routing of neighboring nets,
use with caution):
eco::reroute_ctm_nets -nets $all_nets -force

To restrict tool touching any net (useful when manually routed some nets and do not want to fix net
shapes):
set_attribute -class net -name physical_status -value minor_change -objects $nets
To RIP the metal layer routing from any net (A word of caution: Never RIP any spine nets/RP nets/DOP
output net)
remove_routes -nets {gtlscbanktop1/lscl1bankunit0/gclk_refcnt_2546
gtlscbanktop1/lscl1bankunit0/gt_ram_sv_Nwr_strg/ctmn_911} \
-detail_route \
-global_route \
-user_route

Shorts fixing strategies

1. ZRT shorts:
a. RIP and manual/tool-based reroute of nets with upper layer shorts (typically M4 and
above)
remove_routes -detail_route -global_route -user_route -nets [get_nets
gtlscbanktop1/lscl1bankunit1/lscl1_alloc_pipe1/lscl1_tagcmp1/copt_net_11318
12]
source -e -v
/nfs/site/disks/mtl_128_dssm_par_06/apaturka/21ww12p7_FSO2_inc2_FS_EC
O_CDTww15/dso_eco_runs/builds/net_tcls/short_cleanup_1.tcl
set_fixed_objects [get_shapes -of [get_nets
gtlscbanktop1/lscl1bankunit1/lscl1_alloc_pipe1/lscl1_tagcmp1/copt_net_11318
12]]
set_fixed_objects [get_vias -of [get_nets
gtlscbanktop1/lscl1bankunit1/lscl1_alloc_pipe1/lscl1_tagcmp1/copt_net_11318
12]]

2. For lower layer shorts: If there is no track available for reroute, move the cell (avoid moving any
sequential cell) with lower layer shorts out of congested area. RIP all the existing wiring of that
cell if moved very far, else manually reconnect the nets.

2. LVS shorts: Target these separately once ZRT shorts are clean. It becomes easier to clean these
after ZRT shorts are clean.
a. Check and correct any wrong orientation of cells causing PG shorts by using
set_cell_location cmd. Specify orientation using -orientation switch.
b. Check and incrementally correct any signal/clock nets causing shorts with PG grid. This
generally occurs due to the signal/clock net has fixed attribute and hence tool is not able
to move the shape by its own.

ECO rip and reroute using tool's eco router

remove_routes -nets {aprunit1/i_apr_ip_top/i_apr_ip_av1_filter/ropt_net_1263027
aprunit1/i_apr_ip_top/i_apr_ip_av1_filter/net_net_814762} \
-user_route \
-detail_route \
-global_route

set_routing_rule [get_nets {aprunit1/i_apr_ip_top/i_apr_ip_av1_filter/ropt_net_1263027

aprunit1/i_apr_ip_top/i_apr_ip_av1_filter/net_net_814762}] \
-min_routing_layer M7 \
-max_routing_layer M11

route_eco -nets {aprunit1/i_apr_ip_top/i_apr_ip_av1_filter/ropt_net_1263027

aprunit1/i_apr_ip_top/i_apr_ip_av1_filter/net_net_814762} \
-open_net_driven true \
-utilize_dangling_wires true \
-max_detail_route_iterations 10

A word of caution: Many times, the router may fix the shorts but create opens in order to resolve those.
Please make sure to check all the opens after running route_eco.

RICE ECO flow for shorts fixing

For shorts fixing, we can use rice_eco flow.
Make sure to check opens after the run. You have to first clean up all the
possible ZRT and LVS shorts, only then use the rice-eco flow.
You can add RICE flow as an ECO task from flow builder, under ECO section.
(Please refer to the images shown in "How to launch man-ECO in tsmc process"
section of this cheat sheet.)
It does not accept any PEO ECO stcl.
It will run a couple of route fixing rounds, and will finally save the lib from the
round which has least amount of shorts.
Once complete, you can use it's outputs into next ECO.
Make sure RICE ECO is NOT your last ECO.

Incremental legalization of selected cells

set_fixed_objects -unfix [get_cells {ftopt_p2_236 ftopt_p2_237}]
legalize_placement -post_route -incremental -cells [get_cells {ftopt_p2_236 ftopt_p2_237}]
set_fixed_objects [get_cells {ftopt_p2_236 ftopt_p2_237}]

Proper way of changing a net's logical connections (Caution: May result in FEV to fail if done
incorrectly):
set vpin [get_pins gtdssmpar3_rptunit1/gt_repeater_put_inf_16c70b0c062813e8e21eac1e807f5b08/
odata_reg[290]/SI]
set drvpin [get_pins
gtdssmpar3_rptunit1/gt_repeater_put_inf_16c70b0c062813e8e21eac1e807f5b08/
autovector_odata_reg[302]_MBIT_odata_reg[301]/Q2]
disconnect_net [get_nets -of_objects $vpin] $vpin
connect_pins -incremental $vpin -driver $drvpin

Following will fix missing via DRCs, if any.

set ::route::params(rv_dir_fix_missing_vias)
"/nfs/site/disks/mtl_128_dssm_par_06/apaturka/21ww12p7_FSO2_inc2_FS_ECO_CDTww15/
dso_eco_runs/builds/gtlscpar.dso_ro2_eco2_rice/10_eco/700_rv/work/rv/gtlscpar/gtlscpar.reliance/
staticir"
route::fix_missing_vias

Hold Fixing strategy - one of the manual ways.

Preparing the hold fix table
delay buffer delay
Vhigh085_t0c_ Vhigh085_hot vhigh_t0c_ vhigh_hot_ vhigh085_ vhvqk_hot_
min _min min min max (setup min
slack will
degrade)
e08bff000ac1 5 5 -5(slack will -5(slack will -5 5
n02x5 degrade) degrade)
e08bfm201ac1n 10 10 0 0 -15 10
02x3
e08bfm402ac1n 20 20 10 10 -25 15
02x5
e08bfm402ac1n 25 30 15 15 -40 20
02x3
e08bfm604ac1n 30 35 20 20 -45 25
02x5
e08bfm604ac1n 40 45 30 30 -65 35
02x3

1. For 1st hold iteration, dump the setup and hold slack for the worst min corner
along with the unique endpoint in xls.
2. Prepare a tcl by inserting the appropriate buffer.
3. Leave out any paths with min-max conflict at endpoint. Also leave out any
violations while blind fixing which belong to a fub/unit which is congested. See
step 7 for their fixing strategy.
4. Fix them at and by analyzing the full path from violating startpoint.
5. This will fix most of the violations.
6. For second iteration, carefully check and fix the left out violations considering
start-endpoint pair to avoid setup degradation.
7. For the violations which were intentionally left out that belonged to a congested
fub/unit, try to downsize/backswap the buffers/cells already present in the timing
path which have enough trans & cap margins. You can also intentionally degrade
a net's routing to increase its delay, but do it with caution and do not violate any
other parameters like trans/DRCs while doing it. You may also find available
white space and manually insert hold buffers there without disturbing any other
cells.
8. Do not do blind fixing in 2nd iteration unless absolutely necessary. Try to
downsize/backswap the buffers/cells already present in the timing path which
have enough trans & cap margins. Else, Insert hold buffers very carefully.

RV fixing strategies
1. To fix IR,
a. space out the violating combo cells if there is a cluster
b. downsize the violating flops/clock-gates/latches, even if not in cluster.
c. maybe you have to then duplicate the cell after downsizing to meet the
trans/cap requirements (you can use the util::duplicate_cell or
eco::split_ctm_drivers to do the same)
 d. make sure duplicated and original cells are not sharing the same M1 PG
track.
e. we can also make use of the metal densification script to densify M1 layer,
if not already densified.
f. If still it does not help, we can try for M2/M3 densification as a last resort.
(Caution: this may result in additional shorts)
2. To fix SIGEM,
a. we need to add a parallel stripe to the violating net
b. make sure we do not end up in same net VIA2VIA spacing DRCs or diff-net
VIA2VIA spacing DRCs - check with your LV team for exact spacing rules.
c. make sure not to degrade the source pin's grid structure. An example of
source pin grid structure is shown below. One pin has at least two parallel
lower layer tracks (M1-M4) to support higher current capacity.

3. To fix DIs,
a. check the orientation.
b. It should generally fix the orientation based PG LVS shorts.

Caliber fixing
1. 1_38 fixing strategies:
a. if cell is a low drive strength cell or has high fanouts:
i. upsize if size is available and cap/IR-RV is not degrading
ii. if upsize is not available or not possible due to above factors, split
b. if net's routing quality is bad (either routed on lower metal layers or has
zig-zag routing):
i. net improvement with manual routings
ii. if net is v long, insert a buffer to split the net but make sure to
check 1_26 and timing margins
2. 5_9 fixing strategies:
a. same as 1_38 strategies, only make sure not to use a clock buffer while
sizing/inserting.
 3. 1_26 caliber rule:
a. This rule defines the extra min margins that must be met if you are
deviating from 3 levels of clock from DOP to Flop. This rule generally
violates only when PEO adds extra buffer(s) or removes existing buffer(s)
in a clock path.
b. The fix is to increase the hold margin on the violating endpoints based on
project specific hold margin requirements in each hold-convergence-
corner. The more the deviation from 3 levels of logic, greater is the min-
margin requirement.
4. 6_10: 6_* rule does not run at section level, so make sure you check your partition level
caliber reports to view the 6_* violations.
6_10 rule generally violates when,
i. ssb not driven by scanparisolshiften_cfg_reg, when data pins are driven by ports (fixed without -
shadowing switch)
ii. ssb not driven by scanshiften_cfg_reg, when data pins are not driven by ports (fixed without -
shadowing switch)
iii. ssb has unknown driver (waiver/tfm issue)
iv. si tied off when ssb is connected (fixed with -shadowing switch/waiver)
v. ssb signal not inverted from startpoint (waiver/tfm issue)
vi. incorrect si/ssb case values (waiver/tfm issue)

6_10 generally violates in following 2 cases, where fixes must be done by PEOs.
Case1: If SI pin is connected properly and SSB pin is connected to incorrect driver, you
can use following utility to fix the violations.
Case2: If SI pin is tied off and is violating in 6_10 xml, you can use -shadowing switch in
the "scan::scan_flop_checker" cmd to fix these type of violations. But please check
with your SQO before using this switch.

To fix ssb pins and shadow flops, we have the following utility:
scan::scan_flop_checker.

This utility comes with 3 switches:

-flop (required): receives a single/list/collection of flops to check/fix them.
-check (optional): Ignores the fixer engine and only performs a validity check of the
cells (checks if the cells should be fixed in the first place).
-shadowing (optional): Enables shadowing fixer engine, by default shadowing is
disabled as adding a sequential element to a scan chain can be costly.

This command dumps three reports:

-> ssb_pins_to_fix.rpt: list of flops with ssb identified ssb issues.
-> shadowing.rpt: List of identified flops to be shadowed.
-> flops_witch_clock_issues.rtp: List of flops with non-scan clock (will be excluded
from fixing).

By default, the command will fix any ssb pin violation provided.

Examples of use:
scan::scan_flop_checker -flop <list of flops> : Fixes ssb pins only.
 scan::scan_flop_checker -shadowing -flop <list of flops> : Fixes ssb pins and
shadow flops.
scan::scan_flop_checker -check -flop <list of flops> : Performs a high level check
of the cells (no fixes).
scan::scan_flop_checker -check -shadowing -flop <list of flops> : Performs a high
level check of the cells (no fixes).

More info can be found in the following wiki:

https://wiki.ith.intel.com/display/gtkit/Scan+Methodology#tool-2150461

Please note that the command may not have 100% hit rate, so left out violations must be
cleaned up either manually (as mentioned below) or iteratively running the utility.

The Manual way of fixing 6_10:

Steps:
1. Disconnect the violating SE pin from its existing net.
2. Connect the SE pin with the correct output pin (i.e. to the nearest buffer's output pin that is
connected to the actual desired driver).
3. Upsize the buffer, if necessary.

Example:
disconnect_net -net [get_nets -of [get_pins maunit2/fifout_pre_reg[167]/SE]]
[get_pins maunit2/fifout_pre_reg[167]/SE]
connect_pin -driver maunit2/Buf2009047/X [get_pins
maunit2/fifout_pre_reg[167]/SE] -incremental
size_cell maunit2/Buf2009047 HDBULT06_BUF_CAQM_9

iMET Tool:
iMET is an ECO tool used for manual routing of nets. It eases PEO's manual efforts of net
routings.
To enable iMET plugin, source following script inside your ICC2/FC shell where you have opened
your DB.
source $env(GTKIT_PATH)/rally/tools/iMet/bin/imet.tcl

Useful key shortcuts

shift+L --> shape split
s --> stretch

To draw shapes (via will be automatically inserted if u draw on same net), in case if short is getting
created it will not draw the shape:
To draw a shape of a particular metal layer, you can use following key shortcuts:
alt+0 to alt+9 (m0-m9)
ctrl+0 to ctrl+3 (m10-13)

To write outputs:
set va_nets [get_nets {names of nets whose routing has been changed and needs to be
preserved}]
source /nfs/site/disks/gmd_user_scripts/apaturka/scripts/tclscripts/write_routes_va.tcl
 It will dump va_write_routes.tcl. You can source this tcl directly in your main ECO tcl at
appropriate location.

In case, you are changing some routes of existing net (and not creating new nets), you must
remove the earlier existing routes of that net (called as rip) and then source the
va_write_routes.tcl in the main eco.tcl.
remove_routes -detail_route -global_route -user_route -nets { names of nets
whose routing has been changed and needs to be preserved}
source va_write_routes.tcl

Using fix ECO timing correctly in pt_shell:

restore_session <>

define_user_attribute pt_dont_use -quiet -type boolean -class lib_cell

proc set_pt_dont_use {lib_cell} {
set_user_attribute -class lib_cell [get_lib_cell -quiet $lib_cell] pt_dont_use true
}

Create a tcl by adding all the lib cells present in the

absolute_dont_use.list as follows.
set_pt_dont_use [get_lib_cells { <mention all the lib cells as a list here> }]

Add to the above list any other lib cells that must be excluded as per
caliber/setup/hold requirement.

source absolute_dont_use.stcl that we just created.

run 'fix_eco_timing ' cmd with required switches (e.g. fix_eco_timing -to
$ep_list -type setup -output <output_file>).
write_changes <>

e.g. dont use list to create the absolute_dont_use.stcl:

source /p/mtlsd/gcd/env/library/tsmc_n5p/stdcell/snps_210h/
rev8_v20ww49e_pdk1p1a/scripts/absolute_dont_use.list

Lite man eco cmds:

fill::insert_base_fill -remove

# your ecos here #

legalize_placement -post_route
fill::insert_base_fill
route::eco -loops 10
route::search_and_repair -loops 30
#set ::route::params(adr_max_loops) 2 (ADR viz. Automatic DRC repair is used for sign-off DRC
checks and fixes which are not addressed by the router)
#route::adr
place::swap_cell_variants (to resolve orientation issues)
process::stdcell_power_hookup (this cmd is not required in TSMC process, please check with you
LV owner for the same in intel process)
 common::rename_objects (changes the names if net and cell names are same - if they are same, it
causes issues in FEV)
upf::derive_pg_connections
upf::cleanup
fill::insert_metal_fill
kit::outputs

Advanced PT shell commands:

report_delay_calculation : use to debug crosstalk on any victim net to find the aggressor.

Example:
report_timing -nets -input_pins -thr
gtveboxpar11/veounit1/place_opt_fc_ZINV_inst_1159138/X

report_delay_calculation -crosstalk -from

gtveboxpar11/veounit1/place_opt_fc_ZINV_inst_1159140/X -to
gtveboxpar11/veounit1/place_opt_fc_ZINV_inst_1159138/A

Attribute 'A' for the aggressor means the Aggressor is Active.

How to use this information?

 Space out the aggressor from the victim net.
 Split the long nets by inserting buffers.
 Jump to different metal layers.
 Upsize the victim net's driver or downsize the aggressor net's driver.
 Shielding the nets by ground nets so that the coupling capacitance is formed with the ground
nets and not between the signals.

report_annotated_parasitics : use to get pin-to-pin net annotation issues, if any.

How to use this information?

 If we have pin-pin nets not annotated, it may cause annotation issues in SPV and timing data
may become corrupt.
 We need to check the parasitics log to find the not-annotated net, and root-cause it.
 e.g. log pointer:
<SPV_RUN_AREA>/10_assembly/100_pv_caliber/tmp/parasitics_command.sifunctional
_ffgnp_0p605v_0p66v_0c_rcworst_CCworst_0C_min.log
 Generally, the annotation issues occur because of spef and netlist mismatch. If PEO fixes
something interactively in DB that includes net changes, dumps new netlist but fails to update
the spef files, then it will create annotation issues.

report_bottleneck : use to get worst cells in a timing path. A bottleneck is a common point in the
design that contributes to multiple violations.
 report_bottleneck -cost <path_count | path_cost | fanout_endpoint_cost>
 path_count (the default) - Uses the number of violating paths through the cell.
 path_cost - Uses the total slack of violating paths through the cell.
 fanout_endpoint_cost - Uses the total cost of violating endpoints in the fanout of the
cell.
 e.g. >>
