EEE-4131: EPITAXY Lecture-07

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 CONTENTS
01 What is Epitaxy?

02 Types of Epitaxy

03 Methods of Epitaxial Deposition

04 Epitaxial Defects

05 Evaluation of Epi-Layer

06 Latch-up in CMOS

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 What is Epitaxy
The term epitaxy comes from the Greek words epi (upon) and taxis (an ordered manner).
Epitaxy is the process of depositing pure single-layer crystal film.
Lower temperature process compared to diffusion.
Temperature and substrate type determines the physical structure of deposited films.
Provides a clean, flat layer on top of the less ideal Silicon substrate.
Higher purity films on top of the lower quality substrate can be deposited. (e.g. SiC)
The top Silicon layer of SOI and SOS structure is formed through epitaxy.
The buried layer of a bipolar transistor is produced through epitaxy.
Optical coatings and protective coating are made through epitaxy.
Can combine Silicon substrate with compound semiconductor films. (e.g. HEMTs ,HBTs)

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 Types of Epitaxy
Epitaxy

Homo Epitaxy Hetero Epitaxy

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 Methods
Methods for Epitaxial Deposition

Liquid Phase Epitaxy(LPE)

Vapor Phase Epitaxy(VPE)

Molecular Beam Epitaxy (MBE)

Solid Phase Epitaxy (SPE)

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 Liquid Phase Epitaxy (LPE)

Sliding boat apparatus Sliding boat apparatus with presaturation arrangement

Involves the precipitation of a crystalline film to form a supersaturated melt onto the substrate.
The substrate is dissolved in the melt of another material.
Temperature is increased until a phase transition occurs and then reduced for precipitation.
Layer growth can be controlled by controlling the cooling rate.
Cooling could be a continuous reduction or step reduction.
It is a low-cost method yielding films of controlled composition, thickness, and lower dislocation density.
Disadvantage: Rough surface
Poor thickness uniformity

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 Molecular Beam Epitaxy (MBE)
The environment is highly controlled (Ultra High Vacuum).
In-situ cleaning is done before the process starts.
The substrate (wafer) is mounted on a molybdenum heating block.
The beams of materials to be transported are generated by thermal
evaporation from crucibles known as effusion cells.
Series of effusion cells each with a separate shutter are set up so that
their flux is directed to the substrate.
During growth, the heating block rotates at slow RPM for layer
uniformity.
Reflected high energy electron diffraction (RHEED) technique is used to
monitor the growth of the crystal.
No chemical reaction with the surface.

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 Vapor Phase Epitaxy (VPE)

In VPE epitaxial layer deposition takes place in reactors.

The wafer is etched, cleaned, and degreased before transferring it to the reactor.
Hot H2 gas is flown to the reactor to bring temperature equilibrium.
HCL gas is flown at 1150-1200oC for a few minutes to clean the native oxide of the wafer
Volatile compound (Si and dopant) flows toward the substrate.
The source material is silicon tetrachloride (SiCl4) which is introduced with vapor transport medium H2 gas. (Silane SiH4 is also used)
The chemical reaction for Silicon growth:
SiCl4 +2H2 ⇋ Si+ 4HCl (g)
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 Horizontal Reactor
(RF)

Gas inlet vent

Horizontal Reactor
Reaction chamber in the form of a horizontal quartz tube.
The wafers are placed on a tilted (3-10o) carrier also called susceptor.
RF heating coil heats the susceptor only.[cold wall chamber]
The source gas velocity is forced to increase when it travels down the chamber through tilted susceptor.
The deposition is not uniform.
Low-cost construction.

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 Vertical(Pancake) Reactor

vent
Gas inlet

Vertical (Pancake) Reactor

Wafers are placed on a rotating holder.
RF or Resistive heating is used to maintain the process temperature.
Gas flows at the right angle to the surface.
Uniform deposition.
Complex mechanical design.

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 Barrel Reactor
Gas inlet

Radiant
Heaters

Barrel Reactor

Wafer slices are held(by gravity) in a slightly sloping vertical wall of a large cylindrical carrier.
Radiant heating is used to maintain the process temperature of the reactor. (RF or Resistive)
Gas flow is parallel to the wafer slices.
Better quality of deposition than the horizontal reactor.
Suitable for large batch production(high volume).
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 Epitaxial Defects

Shift in Pattern
▪ A lightly doped epi-layer is introduced in a heavily doped wafer to reduce parasitic resistance.
▪ Transistors are formed in the epi-layer and the heavily doped wafer is a buried layer.
▪ It is necessary to align the upper layers with the buried layers that’s why before growing epilayer alignment mark is etched.
▪ Alignment marks shifts if the growth rate is non uniform.
▪ Due to growth rate and chlorine content precursors pattern shift occurs.

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 Epitaxial Defects

Selective Epitaxial Growth(SEG)

▪ Epi-layer is grown in some regions of the wafer and not deposited in other regions.
▪ SEG applications are device isolation, trench isolation filling, formation of elevated source/drain structure of MOS.
▪ Problems with selective growth include faceting and thickness variations.
▪ Faceting is a nonplanar of the surface due to a lower growth rate along the various crystal planes.

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 Evaluation of Epilayer
Sheet Resistance: Four-point probe method and Van Der Pauw method .

ρ
𝑆ℎ𝑒𝑒𝑡 𝑅𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒, 𝑅𝑠 =
𝑡

[𝑡 ≫ 𝑠 ; bulk sample] ρ 𝑝𝑖 𝑉𝐶𝐷

𝑝𝑖 ∗ 𝑡 𝑉 𝑅𝑠 = = ∗
ρ= ∗ [𝑡 ≪ 𝑠 ; thin sheet] 𝑡 ln(2) 𝐼𝐴𝐵
ln(2) 𝐼

Van Der Pauw method

Four-point probe method
Layer thickness measurement: i) Destructive techniques: Grooving wheel and Angle Lap technique.
ii) Non-destructive technique: Using the lapping interferometric technique.

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 Evaluation of Epilayer
Mobility and carrier concentration: Hall experiment or Van Der Pauw method (without perpendicular magnetic filed).

Hall coefficient,

mobility, Van Der Pauw Method

Hall experiment
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 Evaluation of Epilayer
Secondary ion mass spectrometry or C-V measurement of Schottky barrier diode(formed by mercury contact) technique is
used to measure the impurity profile in the epitaxial layer. This technique is not applicable in case the substrate and epi
layer is of the same type.
Here,
x=Depletion layer width
V=Reverse bias voltage

Electric filed,

Schottky diode structure

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 Latch-up in CMOS
Input

G Output G
VDD
Vss S D D S
oxide oxide
n+ n+ p+ p+
Q1 Rwell

Q2 n-well
Rsubstrate

p-substrate

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 Latch-up in CMOS
If Voutput > VDD
▪ The PMOS drain(p+) and N-Well junction will be forward biased.
▪ Holes will be injected from the Darin region to PMOS.
▪ The current due to hole injection will flow from the PMOS drain to Vss.
▪ The current will turn on the Q1 parasitic transistor.
▪ The base current of Q1 is the collector current of the Q2 parasitic transistor.
▪ This will turn on the Q2 transistor.
If Voutput < VSS
▪ The NMOS drain(n+) and p-substrate junction will be forward biased.
▪ Electrons will be injected from the drain(n+) region to p-substrate.
▪ The injected electron will flow from NMOS drain to VDD
▪ The current due to electron injection will turn on the Q2 parasitic transistor.
▪ The base current of Q2 is the collector current of the Q1 parasitic transistor.
▪ This will turn on the Q1 transistor. Latchup equivalent circuit

From the above conditions, we can say that if any of the parasitic transistors operate, it turn-ons another transistor. Thus the current gain
increases. This current will cause device failure.
To prevent this current flow we have to stop the injected minority electrons to flow from the p-substrate to VDD and minority holes from the N-
well region to the ground(VSS).

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 Latch-Up Prevention
Tap Cell/ Substrate Contact
▪ Add “Well” and “Substrate Contacts” of the appropriate type to reduce the substrate resistance and well resistance.
▪ Place substrate contact as close as possible to the source connection of the substrate.
▪ Substrate contact should be connected to metal to a supply pad.

Guard Rings CMOS with substrate contact

▪ PMOS encircles n+ guard ring connected to VDD to collect the minority carriers.
▪ NMOS encircles p+ guard ring connected to VSS or GND to collect the minority carriers.

CMOS with guard ring

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 Latch-Up Prevention
Epitaxial Layer
▪ P- epitaxial layer in P+ substrate.
▪ Using retrograde well doping.

P- epilayer on P+ substrate Retrograde well

Use of epitaxial substrate with retrograde well doping configuration.

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 Latch-Up Prevention
Isolation
▪ Increase the separation between MOS devices.
▪ Trench technology. (isolates well from the substrate with deep trenches of polysilicon).

Trench isolation

CMOS with trench isolation and P- epiplayer on P+ substrate

Use of SOI structure.

The use of gold impurities in the substrate will minimize the lifetime of the minority carrier.

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 References
VLSI Fabrication Principles by Sorab K Ghandhi.
VLSI Technology by S. M. SZE.
The Science and Engineering of Microelectronic Fabrication by Stephen A. Campbell.
Silicon VLSI Technology by Plummer, Deal, and Griffin
Introduction to Microelectronic Fabrication by Richard C. Jaeger

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 Any
QUESTIONS

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