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Model Question Paper Format COA

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34 views2 pages

Model Question Paper Format COA

Uploaded by

Kushal Kalluru
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Code: CS20APC301 R 20

B.Tech II Year II Semester Regular/Supplementary Examinations Aug


2023
COMPUTER ORGANIZATION AND ARCHITECTURE
(CSE)
Time: 3 hrs. Max
Marks: 60
PART-A
(Compulsory Question)
1. Answer the following 05 x 02 = 10 Marks
a) Define computer organization, computer architecture. 2M
b) What are the conditional code flags? 2M
c) Define seek time and latency in magnetic hard disks. 2M
d) What is an interrupt? what are vectored interrupts? Explain with example. 2M
e) What is SISD? What are its advantages? 2M
PART-B
Answer All five Units 05 x 10 = 50 Marks
UNIT-I
2. a) What is performance measurement? Explain the overall SPEC rating for the 5M
computer in a program.
b) Explain the following: 5M
i)Byte addressabilit y ii) B ig-endian assignment (iii) Little-endian assignment
OR
3. 10 M
What is the need of addressing modes? With suitable example, explain the addressing
modes.
UNIT-II
4. a)Booth’s algorithm for signed numbers (–13) and (+ 11).
Perform 5M

b) Show and perform non restoring division for 3 and 8. 5M


OR
5. Distinguish between Hardwired control and Micro programmed control 10 M
UNIT-III
6. a) Explain the organization of 1K × 1 memory chip. 5M
b) I llustrate cache mapping techniques. 5M
OR
A digital computer has a memory unit of 64K*16 and a cache memory of 1K words. The
cache uses direct mapping with a block size of four words.
7. a) How many bits are there in the tag, index, block and word fields of the address format? 5M
b) How many blocks can the caches accommodate? 5M
UNIT-IV
8. a) What is DMA? Explain the working of DMA with a neat sketch. What are its 5M
advantages?
b) With a neat diagram explain the general 8-bit parallel interface circuit 5M

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Code: CS20APC301 R 20
OR
9. What is an interrupt? What are interrupt service routines and what are vectored 10 M
interrupts? Explain with example
UNIT-V
10. a) What is pipeline? Explain the 4 stages pipeline with its instruction execution steps and 5M
hardware organization.
b) What is Hazard? Differentiate Data Hazards and Instruction Hazards. 5M
OR
11. Explain in detail about interconnection networks. 10 M
*****

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