Solution to Assignment 1 FM : 48

Semiconductor Fundamentals

1. a) Explain the energy band diagrams of a metal, a semiconductor and an insulator. [6]
Every solid has its own characteristic energy band structure. This variation in band structure is responsible
for the wide range of electrical characteristics observed in various materials.

Semiconductor materials at 0 K have basically the same structure as insulators—a filled valence band
separated from an empty conduction band by a band gap containing no allowed energy states. The
difference lies in the size of the band gap Eg, which is much smaller in semiconductors than in insulators.
For example, the semiconductor Si has a band gap of about 1.1 eV compared with 5 eV for diamond. The
relatively small band gaps of semiconductors allow for excitation of electrons from the lower (valence)
band to the upper (conduction) band by reasonable amounts of thermal or optical energy. For example,
at room temperature a semiconductor with a 1 eV band gap will have a significant number of electrons
excited thermally across the energy gap into the conduction band, whereas an insulator with Eg = 6 eV will
have a negligible number of such excitations.

Thus, an important difference between semiconductors and insulators is that the number of electrons
available for conduction can be increased greatly in semiconductors by thermal or optical energy.

In metals, the bands either overlap or are only partially filled. Thus, electrons and empty energy states are
intermixed within the bands so that electrons can move freely under the influence of an electric field. As
expected from the metallic band structures, metals have a high electrical conductivity.
b) Write the Fermi Dirac distribution function and explain the notations used. [2]
Electrons in solids obey Fermi–Dirac statistics. In the development of this type of statistics, one must
consider the indistinguishability of the electrons, their wave nature, and the Pauli exclusion principle.
The rather simple result of these statistical arguments is that the distribution of electrons over a range
of allowed energy levels at thermal equilibrium is

where,
• k is Boltzmann’s constant (k = 8.62 X 10-5 eV/K = 1.38 X 10-23 J/K).
• The function f(E), the Fermi–Dirac distribution function, gives the probability that an available
energy state at E will be occupied by an electron at absolute temperature T.
• The quantity EF is called the Fermi level, and it represents an important quantity in the analysis
of semiconductor behavior. We notice that, for an energy E equal to the Fermi level energy
EF, the occupation probability is ½.

c) Draw the energy band diagram and show the position of the Fermi level for n-type and p-
type semiconductors. [4]

Position of the Fermi level for (a) n-type and (b) p-type semiconductors.
Here,
EC = minimum of the conduction band energy level
EV = maximum of the valence band energy level
EF = Fermi level
ED = Donor energy level for n-type semiconductor
EA = Acceptor energy level for p-type semiconductor.
The energy axis represents the electron energy.

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2. a) Name two elemental and compound semiconductors. [2]

elemental semiconductors – Silicon (Si), Germanium (Ge)
compound semiconductors – GaAs (Gallium Arsenide), GaAsP (Gallium Arsenide Phosphide).
Note : GaAsP is used in the manufacture of red and orange LEDs.

b) What is the difference between intrinsic and extrinsic semiconductor? [2]

A perfect semiconductor crystal with no impurities or lattice defects is called an intrinsic semiconductor.
In such material there are no charge carriers at 0 K, since the valence band is filled with electrons and the
conduction band is empty. At higher temperatures EHPs (electron hole pairs) are generated as valence
band electrons are excited thermally across the band gap to the conduction band. These EHPs are the only
charge carriers in intrinsic material.

In addition to the intrinsic carriers generated thermally, it is possible to create carriers in semiconductors
by purposely introducing impurities into the crystal. This process, called doping, is the most common
technique for varying the conductivity of semiconductors. By doping, a crystal can be altered so that it has
a predominance of either electrons or holes. Thus, there are two types of doped semiconductors, n-type
(mostly electrons) and p-type (mostly holes). When a crystal is doped such that the equilibrium carrier
concentrations n0 and p0 are different from the intrinsic carrier concentration ni, the material is said to be
extrinsic.

Note : This answer is too detailed for a 2 marks question. Write much more briefly. A more comprehensive
solution is provided so that you know what to write for a question carrying higher marks.
c) What is doping ? How do you convert a Germanium semiconductor to p-type and n-type ?
[4]
The process of introducing controlled number of impurities in an intrinsic semiconductor, so as
to alter the original properties of the intrinsic semiconductor, is called doping. The electrical
properties, in particular, are substantially changed. Such impurities are typically added in the
ratio of 1 impurity for every 1 million atoms of the intrinsic semiconductor.
When we add trivalent impurities like Boron (B), Gallium (Ga), Indium (In), etc. to a pure
Germanium semiconductor, we get p-type extrinsic semiconductor.
On the other hand, when we add pentavalent impurities like Phosphorus (P), Arsenic (As),
Antimony (Sb), etc. to a pure Germanium semiconductor, we get n-type extrinsic semiconductor.

d) Explain the conduction mechanism for an n-type semiconductor. [4]

In a semiconductor, the two basic processes of current conduction are diffusion due to a carrier gradient
and drift in an electric field.

Diffusion : When excess carriers are created nonuniformly in a semiconductor, the electron and hole
concentrations vary with position in the sample. Any such spatial variation (gradient) in n and p calls for a
net motion of the carriers from regions of high carrier concentration to regions of low carrier
concentration. This type of motion is called diffusion and represents an important charge transport
process in semiconductors. Carriers in a semiconductor diffuse in a carrier gradient by random thermal
motion and scattering from the lattice and impurities.

The diffusion current crossing a unit area (the current density) is the particle flux density multiplied by the
charge of the carrier:

Drift : If the semiconductor bar of the figure contains both types of carriers, the following equation gives
the current density, Jx i.e., the current passing through a unit cross section area, and is expressed in A/cm2.

The physical mechanism of carrier drift requires that the holes in the bar move as a group in the direction
of the electric field and that the electrons move as a group in the opposite direction. Both the electron
and the hole components of current are in the direction of the field, since conventional current is positive
in the direction of hole flow and opposite to the direction of electron flow. The drift current described by
the mentioned equation is constant throughout the bar.

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3. a) Draw and explain the Fermi Dirac Distribution function qualitatively for three different
temperatures, 0K, 150K and 300K. [2 + 4]

An examination of f(E) indicates that at 0 K the distribution takes the simple rectangular form shown in
the figure. With T = 0 in the denominator of the exponent, f(E) is 1/(1 + 0) = 1 when the exponent is
negative (E < EF), and is 1/(1 + ∞) = 0 when the exponent is positive (E > EF). This rectangular distribution
implies that at 0 K, every available energy state up to EF is filled with electrons, and all states above EF are
empty.

At temperatures higher than 0 K, some probability exists for states above the Fermi level to be filled. For
example, at T = T1 = 150K there is some probability f(E) that states above EF are filled, and there is a
corresponding probability [1 - f(E)] that states below EF are empty. The Fermi function is symmetrical
about EF for all temperatures; that is, the probability f(EF + ΔE) that a state ΔE above EF is filled is the same
as the probability [1 - f(EF - ΔE)] that a state ΔE below EF is empty. The symmetry of the distribution of
empty and filled states about EF makes the Fermi level a natural reference point in calculations of electron
and hole concentrations.

At still higher temperatures, T2 (= 300K) > T1 (150K), there is a higher probability f(E) that states above EF
are filled, and there is a corresponding lower probability [1 - f(E)] that states below EF are empty.

b) What do you mean by effective mass of a hole? [2]

The electrons in a crystal are not completely free, but instead interact with the periodic potential of the
lattice. As a result, their “wave - particle” motion cannot be expected to be the same as for electrons in
free space. Thus, in applying the usual equations of electrodynamics to charge carriers in a solid, we must
use altered values of particle mass. In doing so, we account for most of the influences of the lattice, so
that the electrons and holes can be treated as “almost free” carriers in most computations. The calculation
of effective mass must take into account the shape of the energy bands in three-dimensional k-space,
taking appropriate averages over the various energy bands.

In any calculation involving the mass of the charge carriers (electron or hole), we must use effective mass
values for the particular material involved. The electron effective mass is denoted by m*n and the hole
effective mass by m*p. The n subscript indicates the electron as a negative charge carrier, and the p
subscript indicates the hole as a positive charge carrier.

Note : This answer is too detailed for a 2 marks question. Write much more briefly. A more comprehensive
solution is provided so that you know what to write for a question carrying higher marks.

c) Assume that, in an n-type semiconductor at T = 300K, the electron concentration varies

linearly from 1018 to 7  1017/cm3 over a distance of 0.1 cm. Calculate the diffusion current
density if the electron diffusion co-efficient, Dn = 22.5 cm2/s. [2]

The diffusion current density is given by

dn(x)⁄
Jn = q Dn dx
Substituting the values of the relevant parameters, we get
Jn = 1.6 x 10-19 C x 22.5 cm2/s x {(1018 - 71017) cm-3 / 0.1 cm}
or

Note : 1 (one) mark is to be deducted for no or incorrect unit.

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4. a) Define Fermi energy level at T = 0K. [1]

An examination of f(E) indicates that at 0 K, the distribution takes the simple rectangular form. With T = 0
in the denominator of the exponent, f(E) is 1/(1 + 0) = 1 when the exponent is negative (E < EF), and is 1/(1
+ ∞) = 0 when the exponent is positive (E > EF). This rectangular distribution implies that at 0 K every
available energy state up to EF is filled with electrons, and all states above EF are empty.

b) Show that the probability of an energy state being occupied ΔE above the Fermi level is the
same as the probability of a state being empty ΔE below the Fermi level.
f(EF + ΔE) = 1 – f(EF – ΔE). [4]

The Fermi-Dirac distribution function f (E) of electrons over a range of allowed energy levels at thermal
equilibrium is given by

This gives the probability that an available state at E will be occupied by an electron at absolute
temperature T.

Now, the probability of an energy state being occupied, ΔE above the Fermi level is
1
f (EF + E) = ΔE -------------------------- (1)
1+ⅇ
kT

Again, the probability of an energy state being empty, ΔE below the Fermi level is
−ΔE
1 ⅇ
1 - f (EF -  E) = 1 - −ΔE = kT
−ΔE
1+ⅇ 1+ⅇ
kT kT

ΔE
Multiplying both numerator and denominator by ⅇ , we get
kT

1
f (EF -  E) = ΔE -------------------------- (2)
1+ⅇ
kT

Since equations (1) and (2) are same, the given proposition is true.
c) Calculate the position of the Fermi level, EF w.r.t. conduction band energy, EC for silicon
doped with 1017 donor atoms / cm3. Intrinsic carrier concentration ni = 1010 / cm3, band gap of
silicon Eg = 1.2 eV and thermal voltage VT = 26 mV. [3]

EFn - EFi = kT ln (no / ni)

where,
EFn = position of the Fermi level of electrons (n-type),
EFi = intrinsic Fermi level
no = concentration of electrons in the conduction band
= Nd = 1017 / cm3
ni = intrinsic carrier concentration
= 1010 / cm3
Substituting appropriate values, we get

EFn - EFi = 0.026 ln (1017 / 1010)

= 0.42 eV

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5. a) Define conduction band and valence band of a semiconductor. [2]

In a solid, many atoms are brought together, so that the split energy levels form essentially continuous
bands of energies. As an example, considering the imaginary formation of a silicon crystal from isolated
silicon atoms, each isolated silicon atom has an electronic structure 1s2 2s2 2p6 3s2 3p2 in the ground
state. Each atom has available two 1s states, two 2s states, six 2p states, two 3s states, six 3p states, and
higher states. If we consider N atoms, there will be 2N, 2N, 6N, 2N, and 6N states of type 1s, 2s, 2p, 3s,
and 3p, respectively.

As the interatomic spacing decreases, these energy levels split into bands, beginning with the outer (n =
3) shell. As the “3s” and “3p” bands grow, they merge into a single band composed of a mixture of energy
levels. This band of “3s–3p” levels contains 8N available states. As the distance between atoms
approaches the equilibrium interatomic spacing of silicon, this band splits into two bands separated by an
energy gap Eg. The upper band (called the conduction band) contains 4N states, as does the lower
(valence) band. Thus, apart from the low-lying and tightly bound “core” levels, the silicon crystal has two
bands of available energy levels separated by an energy gap Eg wide, which contains no allowed energy
levels for electrons to occupy.

Note : This answer is too detailed for a 2 marks question. Write much more briefly. A more comprehensive
solution is provided so that you know what to write for a question carrying higher marks.

b) Write Einstein's relation for the drift and diffusion of carriers in semiconductor. [2]

where,
D = Diffusion coefficient of charge carriers, electrons or holes (cm2 / s)
μ = Mobility of charge carriers, electrons or holes (cm2 / V-s)
k = Boltzmann’s constant (8.62 X 10-5 eV/K = 1.38 X 10-23 J/K)
T = Absolute Temperature (K)
q = charge of an electron, 1.6 x 10-19 C.

c) Find the conductivity of silicon with donor impurity of 1015/cm3. Given, that ni for Si at 300K is
1.5×1010/cm3, μn = 1,300 cm2/Vs, μp = 500 cm2/Vs. [2]

The doped semiconductor is of n type.

Now, nn ≈ ND = 1015/cm3
pn = ni2 / nn = (1.5×1010)2 / 1015 = 2.25 x 105 /cm3

The conductivity, σ is
σ = q (n μn + p μp)
or, σ = 1.6 x 10-19 x (1015 x 1300 + 2.25 x 105 x 500) C x /cm3 x cm2/Vs
or, σ ≈ 0.208 (Ω cm)-1, ignoring the second term w.r.t. the much larger first term.

References
1. Electronic Devices & Circuit Theory – Boylestad & Nashelsky
2. Solid State Electronic Devices – Streetman & Banerjee

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Solution to Assignment 2 FM : 46

p-n junction, Semiconductor Diodes

1. a) Write down the current-voltage equation of p-n junction diode explaining all the symbols
used. [2]
Shockley’s equation states the current-voltage equation of p-n junction diode
ID = IS [e (VD / ηVT) - 1], where

ID = Current flowing through a diode

IS = Reverse saturation current

VD = Voltage across the diode or bias voltage

η = Ideality factor of a diode (η = 1 for Ge, and η = 2 for Si at low current levels; η = 1 for both Si and
Ge at higher current levels)
𝑘𝑇
VT = 𝑞
is the Thermal voltage = 26 mV at T = 300 K

k = Boltzmann’s constant = 1.38 X 10-23 J / K

T = Absolute Temperature in K

q = Charge of an electron = 1.6 x 10-19 C.

b) A Si diode, for which the reverse saturation current is 10 µA, is conducting 1 Amp at 27 0C.
Calculate the forward voltage drop across it. Thermal voltage = 26 mV. [2]
We know from Shockley’s equation that
ID = IS [e (VD / ηVT) - 1], where for the following given parameter values
ID = 1 A
IS = 10 x 10-6 A = 10-5 A
𝑘𝑇
Thermal voltage, VT = 𝑞
= 26 mV at T = 300 K.
η = 2 (for Si), we are to find VD = Voltage across the diode.

Substituting appropriate values, we get

1 = 10-5 [e (VD / 2 x 0.026) – 1]
or, 105 = [e (VD / 0.052) – 1],
or, 105 + 1 = e (VD / 0.052)
or, ln (105 + 1) = VD / 0.052,
or, 11.513 x 0.052 = VD
or, VD = 0.6 V.
c) Explain the formation of the depletion region in pn junction? Show the built-in voltage
(contact potential) across it. [3 + 1]
Since there is a density gradient across the junction (p on the left, n on the right), holes will initially
diffuse to the right across the junction, and electrons to the left. We see that the (positive) holes which
neutralized the acceptor ions near the junction in the p-type material have disappeared as a result of
combination with electrons which have diffused across the junction. Similarly, neutralizing electrons
in the n-type material have combined with holes which have crossed the junction from the p-type
material. The unneutralized ions in the neighbourhood of the junction are referred to as uncovered
charges. The general shape of the charge density (bottom left of the figure) depends upon how the
diode is doped. Since the region of the junction is depleted of mobile charges, it is called the depletion
region, or the space charge region. Within this narrow depletion region (about 0.5 μm) there are no
mobile carriers.

The electrostatic potential variation in the depletion region shown (top right) constitutes a potential
energy barrier against the further diffusion of holes across the barrier. The form of the potential
energy barrier against the flow of electrons from the n side across the junction is shown in the figure
(bottom right). It is similar to that shown in the (top right), except that it is inverted, since the charge
on an electron is negative.

d) Explain the breakdown mechanisms in pn junction diode. [6]

Avalanche breakdown Zener breakdown

Occurs at higher reverse bias voltages, |Vbr| > 5V. Occurs at lower reverse bias
voltages, |Vbr| < 5V.
For lightly doped diodes. For higher doping levels of p and
n-type material, resulting in
 lesser depletion width at the
junction.
Ionization takes place by collision. Ionization takes place due to
high electric field / unit width of
the depletion region.
As the voltage across the diode increase in the reverse bias region, It occurs because there is a
the velocity of the minority carriers responsible for the reverse strong electric field in the region
saturation current, IS will also increase. Eventually their velocity and of the junction that can disrupt
associated Kinetic Energy (½ mv2) will be sufficient to release the bonding forces within the
additional carriers through collisions with stable atomic structures atom and generate carriers.
i.e., an ionization process will result, whereby valence electrons
absorb sufficient energy to leave the parent atom. These additional
carriers can then aid the ionization process to the point, where a
high avalanche current is established and the avalanche breakdown
region determined.

Although the Zener breakdown mechanism is a significant contributor only at low levels of VBV, this
sharp change in the characteristic at any level is called the Zener region, and diodes employing this
unique portion of the characteristic of a p-n junction are called Zener diodes.

2. a) Explain the I-V (current-voltage) characteristics of a pn junction diode, under forward

and reverse bias conditions. [6]

For a p-n junction the current ID is related the applied voltage VD, by Shockley’s equation

ID = IS [e (VD / ηVT) - 1]. The form of the volt-ampere characteristic described by Shockley’s equation, is
shown in the figure below. When the voltage VD is several times VT, the unity in the parenthesis can
be neglected. Accordingly, except for a small range in the neighbourhood of the origin, the current
increases exponentially with voltage. When the diode is reverse biased and | VD | is several times VT,
ID ≈ - IS (since the exponential term in Shockley’s equation becomes negligible compared to 1). The
reverse current is therefore constant, independent of the applied reverse bias. Consequently, IS is
referred to as the reverse saturation current.

For the sake of clarity, the current IS in the figure has been greatly exaggerated in magnitude.
Ordinarily, the range of forward currents over which a diode is operated is many orders of magnitude
larger than the reverse saturation current. To display forward and reverse characteristics
conveniently, two different scales have been used, a forward-scale in mA, and a reverse-scale in nA.
The dashed portion of the curve indicates that, at a reverse-biasing voltage VZ, the diode I-V
characteristic exhibits an abrupt and marked departure from the Shockley’s equation. At this critical
voltage, called breakdown voltage, a large reverse current flow, and the diode is said to be in
breakdown region.

Figure : The IV characteristic for a Germanium diode.

b) The saturation current density of a Ge p-n diode at 270 C is 30 nA. What voltage must be
applied to the diode to yield a forward current density of 6 mA ? Thermal voltage is 26 mV.
[2]
We know from Shockley’s equation that
ID = IS [e (VD / ηVT) - 1], where for the following given parameter values
IS = 30 nA, at T = 300 K,
ID = 6 mA
𝑘𝑇
Thermal voltage, VT = 𝑞
= 26 mV at T = 300 K.
η = 1 (for Ge), we are to find VD = Voltage across the diode.
Substituting appropriate values, we get
6 x 10-3 = 30 x 10-9 [e (VD / 1 x 0.026) – 1]
or, 2 x 105 = [e (VD / 0.026) – 1],
or, 2 x 105 + 1 = e (VD / 0.026)
or, ln ((2 x 105)+ 1) = VD / 0.026,
or, 12.206 x 0.026 = VD
or, VD = 0.317 V.
c) Define built-in potential and derive the expression for the built-in potential of an abrupt
p-n junction. [6]

An electric field ℰ builds up to the point where the net current is zero at equilibrium. The electric field appears
in some region W about the junction, and there is an equilibrium potential difference V0 across W. In the
electrostatic potential diagram shown above, there is a gradient in potential in the direction opposite to ℰ, in
accordance with the fundamental relation ℰ(x) = -d 𝒱(x) / dx. We assume the electric field is zero in the neutral
regions outside W. Thus, there is a constant potential 𝒱n in the neutral n material, a constant 𝒱p in the neutral
p material, and a potential difference V0 = 𝒱n - 𝒱p between the two. The region W is called the transition region,
and the potential difference V0 is called the built-in potential or contact potential. The contact potential
appearing across W is a built-in potential barrier, in that it is necessary to the maintenance of equilibrium at the
junction; it does not imply any external potential.
3. a) Draw the energy band diagram of a pn junction diode in thermal equilibrium, under
forward bias and reverse bias conditions. [6]

It is to be noted that the Fermi level at equilibrium must be constant throughout the materials
in intimate contact, since the net motion of electrons is zero. In other words, there is
invariance of the Fermi level at equilibrium - no discontinuity or gradient can arise in the
equilibrium Fermi level EF.

b) Consider a uniformly doped silicon pn junction with doping concentration N A = 1017 cm-3
and ND = 1016 cm-3. What is the value of Vbi (built in potential barrier) at T = 300K. ni = 1.5 ×
1010 cm-3. Thermal voltage is 26 mV.
 The Vbi (built-in potential) is given by the formula
𝑘𝑇
Vbi = VT ln {NA ND) / ni2}, where VT = 𝑞
= 26 mV at T = 300 K.

So, Vbi = 26 x 10-3 ln [(1017 x 1016) / (1.5 x 1010)2 ]

or, Vbi = 26 x 10-3 ln (4.44 x 1012)

or, Vbi = 26 x 10-3 x 29.12

or, Vbi = 757 x 10-3 V = 757 eV.

Draw the energy band diagram of this pn junction showing all the energy levels.
[5]

Note : Please refer to “Solid State Electronic Devices – Global edition”, Streetman Banerjee,
Example 5-1, Page 199 for an elaboration of these type of problems.

4. a) Explain the effect of temperature on the current of p-n junction under reverse bias
condition. [3]
The reverse saturation current IS at a p-n junction consists of minority charge carriers. When
the temperature of the semi-conductor material is raised, increasing numbers of electrons
break away from their atoms. This generates additional minority charge carriers, causing IS to
increase as the junction temperature rises.
When IS is known for a given temperature (T1), it can be calculated for another temperature
(T2) from the following equation :-
IS (T2) = IS (T1) x 2 (T2 – T1) / 10
It follows that IS approximately doubles for every 10oC rise in temperature.

b) Calculate the bandgap of an intrinsic LED which emits light of wavelength 760 nm. [2]

To move an electron from one discrete energy level to another requires a specific amount of energy,
the amount of energy involved is given by
Eg = hc / λ
where,
h = Plank’s constant = 6.626 x 10-34 Js
c = velocity of light = 3 x 108 m/s, and
λ = wavelength of the light = 760 nm = 760 x 10-9 m = 76 x 10-8 m (given).
Therefore,
Eg = (6.626 x 10-34 x 3 x 108) / 76 x 10-8 = 2.6 x 76 x 10-19 J
Eg = 2.6 x 76 x 10-19 J / 1.6 x 10-19 = 1.63 eV.

c) Determine the wavelength of light emitted from LED which is made up of GaAsP
semiconductor whose forbidden energy gap is 1.75 eV. [2]
We know that,

Eg = hc / λ
where,
Eg = Band gap energy = 1.75 eV
h = Plank’s constant = 6.626 x 10-34 Js
c = velocity of light = 3 x 108 m/s, and
λ = wavelength of the light (to be determine
Therefore,
λ = (6.626 x 10-34 x 3 x 108) / (1.75 x 1.6 x 10-19)
or, λ = 7.1 x 10-7 m
λ = 710 nm.

References
1. Electronic Devices & Circuit Theory – Boylestad & Nashelsky
2. Solid State Electronic Devices – Streetman & Banerjee.
3. Lecture Notes – Razavi Electronics 1

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Solution to Assignment 3 FM : 56

Diode circuits

1. a) i) Explain the operation of a bridge rectifier circuit. ii) How can you reduce the ripple
voltage? iii) Why bridge rectifiers are preferred over centre-tapped full wave rectifiers?
[5 + 1 + 2]

i) The dc level obtained from a sinusoidal input can be improved 100% using a process called full-
wave rectification. The most familiar network for performing such a function appears in Fig. 2.53
with its four diodes in a bridge configuration.

During the period t = 0 to T/2 the polarity of the input is as shown in Fig. 2.54. The resulting polarities
across the ideal diodes are also shown in Fig. 2.54 to reveal that D2 and D3 are conducting, whereas D1
and D4 are in the “off” state. The net result is the configuration of Fig. 2.55, with its indicated current and
polarity across R. Since the diodes are ideal, the load voltage is vo = vi, as shown in the same figure.

For the negative region of the input the conducting diodes are D1 and D4, resulting in the configuration
of Fig. 2.56. The important result is that the polarity across the load resistor R is the same as in Fig. 2.54,
establishing a second positive pulse, as shown in Fig. 2.56.
Over one full cycle the input and output voltages will appear as shown in Fig. 2.57.

ii) The ripple voltage can be reduced by connecting a (storage) capacitor across the load.

iii) Preference of bridge rectifiers over centre-tapped full wave rectifiers

1) In case of a bridge rectifier the PIV across either of the non-conducting diodes is equal to the peak
value of the transformer secondary voltage, Vm, whereas the PIV of each diode in a centre tapped
full wave rectifier (FWR) is 2Vm. Hence, diodes of higher rating are to be used in centre-tapped
FWR.
2) Transformers used in centre-tapped FWR are bulky, consume more space and eventually costlier
than the two extra diodes used in bridge rectifiers.
3) Transformer utilization factor (TUF) is considerably higher in case of bridge rectifier. Since the
current flowing in the transformer secondary is purely alternating, the TUF increases from 0.693
to 0.812, which is the main reason for the popularity of a bridge rectifier.
 4) The bridge rectifiers are used in applications allowing floating output terminals, i.e., no output
terminal is grounded.

Note (not part of the answer) : The following parameters are same for both
▪ Efficiency = 81.2%
▪ Ripple factor = 0.48
▪ Form factor = 1.11
▪ Vdc (no load) = 2Vm / π
▪ Average current = Idc / 2

b) Draw the output voltage waveform of the clipper circuit shown in following Figure 1.
VB1=1 V, VB2= 2 V, cut-in voltage (V0) = 0.5 V. [7]

Figure 1

For time t --> 0 to T/2

▪ The diode, D2 is reverse biased by both Vin (20 V(p-p)), VB2 (2 V) and D2 cut-in voltage,
V0 (0.5 V) for the full positive half cycle, t -> 0 to T/2.
▪ The diode, D1 is forward biased by Vin and reverse biased by VB1 (1 V) and D1 cut-
in voltage, V0 (0.5 V).

Replacing the diode, D1 by its equivalent circuit and applying Kirchoff’s Voltage
Law (KVL) (clockwise direction), in loop 1, we get

- Vin + VR + VB1 + V0 = 0.

Neglecting VR, till Vin ≤ VB1 + Vo, i.e. Vin ≤ 1 V + 0.5 V (= 1.5 V), the diode, D1 is reverse
biased and no current flows in the loop 1. The output voltage, V out = Vin.

For Vin > VB1 + Vo, i.e. Vin > 1 V + 0.5 V (= 1.5 V), the diode, D1 path is short circuit
and Vout = 0.
For time t --> T/2 to T

▪ The diode, D1 is reverse biased by both Vin (20 V(p-p)), VB1 (1 V) and D1 cut-in voltage,
V0 (0.5 V) for the full negative half cycle, t -> T/2 to T.
▪ The diode, D2 is forward biased by Vin and reverse biased by VB2 (2 V) and D2 cut-
in voltage, V0 (0.5 V).

Replacing the diode, D2 by its equivalent circuit and applying KVL (anti-clockwise
direction), in loop 2, we get

- Vin + V0 + VB2 + VR = 0.

Neglecting VR, till Vin ≤ VB2 + Vo, i.e. Vin ≤ 2 V + 0.5 V (= 2.5 V), the diode, D2 is reverse
biased and no current flows in the loop 2. The output voltage, V out = Vin.

For Vin > VB2 + Vo, i.e. Vin > 2 V + 0.5 V (= 2.5 V), the diode, D2 path is short circuit
and Vout = 0.
 The resulting input and output waveforms are shown in the figure below.

2. a) The circuit given below (Figure 2) has an input voltage Vin = 200V, R = 10KΩ and the load
having resistance 5KΩ. If the Zener voltage VZ = 40V and Zener impedance ZZ = 2. Find the
current through R (I), Zener current (IZ) and load current (IL). [5]

Figure 2
Applying KVL, in the loop in the left part of the circuit, we have
Vin = (I x R) + (IZ x RZ) + VZ
or, 200 = (I x 10,000) + (IZ x 2) + 40
or, 10,000 I + 2 IZ = 160 -------------- (1)
 Now, considering potential drop across the Zener and RL to be the same, we have
(IZ x RZ) + VZ = IL x RL = (I – IZ) x RL
or, (IZ x 2) + 40 = (I – IZ) x 5000
or, 2 IZ + 40 = 5000 I – 5000 IZ
or, 5000 I - 5002 IZ = 40 -------------- (2)
Multiplying eq (2) by 2, we get
10000 I – 10004 IZ = 80 -------------- (3)
eq (1) – eq (3) gives
10006 IZ = 80,
or, IZ = 80 / 10006 = 7.995 mA.

From eq (1),
I = {160 – (2 x 7.995 x 10-3)} / 10000 = 15.998 mA.
IL = I – IZ = 15.998 – 7.995 = 8.003 mA.

b) For the same circuit (Figure 2), the input voltage peak, Vin (peak) = 110 V having load
resistance, RL = 10 KΩ. The maximum current through the Zener diode is 0.5 A. The Zener
voltage VZ = 40 V. Find the minimum value of the series resistance, R. Determine current
through R (I), Zener current (IZ), and load current (IL) for R = 1 KΩ. [5]

Load current, IL will always be VZ / RL = 40 / 10K = 4 mA.

I = (Vin – VZ) / R = IZ + IL
When IZ = IZmax = 0.5 A = 500 mA,
I = 500 + 4 = 504 mA
Therefore, Rmin = (Vin – VZ) / I = (110 – 40) V / 504 mA = 138.9 Ω

When R = 1 KΩ
I = (Vin – VZ) / R = (110 – 40) V / 1 KΩ = 70 mA
IL = 4 mA, and
IZ = I - IL = 70 -4 = 66 mA.
3. a) Define and derive the ripple factor of a rectifier circuit. Determine the ripple factor for a
full wave rectifier. [2 + 3]

Ripple factor of a rectifier circuit determines the amount of ripple in the output voltage of
the rectifier. Lower the ripple factor, truer is the dc voltage.

Ripple factor is given by

γ = [(I2rms / I2dc) - 1]½

Mathematically,
rms value of ac part of the voltage
Ripple factor, γ = dc value of the voltage

rms value of ac part of the current

or, γ = dc value of the current

Again,

Ripple factor, γ = [(Form factor)2 - 1]½

Where, Form factor, FF = Vrms / Vavg

Ripple factor for a full wave rectifier,

Vrms = Vm / 2 ½, and

Vavg = 2 Vm / π.

So, FF = π / (2 x 2 ½) = 1.11

Therefore, Ripple factor, γ = [(Form factor)2 - 1]½

or, γ = [(1.11)2 - 1] ½ = 0.482

in percentage, γ = 48.2 %
b) Draw the output voltage waveform of the clipper circuit shown in following Figure 3.
VB1=3 V and cut-in voltage (V0) = 0.5 V. [5]

Figure 3

Replacing the diode with its equivalent circuit, we have the following :-

from time t --> 0 to T/2, for Vin = 0 to 3.5V, and from 3.5V to 0, the diode is reverse biased
and can be replaced by an o.c. the output voltage V out follows the input voltage, Vin. For
Vin = 3.5V to 10V, the diode is forward biased and can be replaced by a s.c. the output
voltage Vout is clipped at 3.5V, as shown.

from time t --> T/2 to T, the diode is reverse biased and can be replaced by an o.c. the
output voltage Vout follows the input voltage, Vin, ignoring any voltage drop across the
resistance, R.
4. a) Draw and explain the operation of a centre-tapped full-wave rectifier circuit. Write down
the disadvantages, if any, of bridge rectifiers over centre-tapped full-wave rectifiers.
[4 + 1]
The centre-tapped full wave rectifier requires two diodes and a centre-tapped transformer
to establish the input signal across each section of the secondary of the transformer.

During the positive portion of vi applied to the primary of the transformer, the network will
appear as shown below with a positive pulse across each section of the secondary coil. D1
assumes the short-circuit equivalent, and D2 the open-circuit equivalent, as determined by
the secondary voltages and the resulting current direction. The output voltage appears as
shown to the right of the circuit.

During the negative portion of the input, the network appears as shown below, reversing the
roles of the diodes but maintaining the same polarity for the voltage across the load resistor,
R. The net effect is the same output as that appearing in the upper figure with the same dc
levels.
Bridge rectifiers need 4 diodes in the circuit, whereas the centre tapped full wave rectifier
needs only 2. Hence more economically efficient.

b) Write the name of the circuit shown in Figure 4. Explain its operation and draw the
output voltage across the load for a sinusoidal input. Assume the diode is ideal. V P = 5V.
[1 + 4 + 2]

Figure 4
Note the corrected convention of representing a polarized electrolytic capacitor.

For t --> T/2 to T

The diode is forward biased, and can be replaced by a s.c. The equivalent circuit is as
shown in the middle of the figure below.
The current passes through the s.c. and no current passes through the resistance R L.
Therefore, Vo = 0.

For t --> 0 to T/2

The diode is reverse biased, and can be replaced by an o.c. The equivalent circuit is as
shown in the left of the figure below.
Applying KVL, in the loop (clockwise direction) we get,
-Vi - VC + Vo = 0
or, Vo = Vi + VC = 2 Vi.
 The output waveform is as shown superimposed on the input waveform. Note that for
ease of understanding, t --> T/2 to T is explained first, then t --> 0 to T/2. But for a periodic
waveform it does not matter.

The circuit is that of a positive unbiased clamper.

5. a) Draw a positive clipper circuit using a diode. Sketch the output waveform for a square wave
input. [3]
b) Draw and explain the operation of a half-wave rectifier circuit. Considering the ideal diode model
obtain the expression for ripple factor. [3 + 3]

During the interval t = 0 to T/2 in Fig. 2.44 the polarity of the applied voltage vi is such as to establish “pressure” in
the direction indicated and turn on the diode with the polarity appearing above the diode. Substituting the short-
circuit equivalence for the ideal diode will result in the equivalent circuit of Fig. 2.45, where it is fairly obvious that
the output signal is an exact replica of the applied signal. The two terminals defining the output voltage are
connected directly to the applied signal via the short-circuit equivalence of the diode.

For the period T/2 to T, the polarity of the input vi is as shown in Fig. 2.46, and the resulting polarity across the ideal
diode produces an “off” state with an open-circuit equivalent. The result is the absence of a path for charge to flow,
and vo = iR = (0)R = 0 V for the period T/2 to T.

The input vi and the output vo are sketched together in Fig. 2.47, for comparison purposes.
 Ripple factor for a half wave rectifier,

Vrms = Vm /2, and

Vavg = Vm / π.

So, FF = π / 2.

Therefore, Ripple factor, γ = [(Form factor)2 - 1]½

or, γ = [(π / 2)2 - 1] ½ = 1.2113

in percentage, γ =121.13 %

References
1. Electronic devices and Circuit Theory – Boylestad & Nashelsky, 11th edition
2. Electronic devices and Circuits – Salivahanan, Suresh Kumar, Mc Graw Hill @ 2018

--------------------- X ---------------------
Solution to Assignment 4 FM : 63

Transistors

1. a) Draw and explain the input and output characteristics of a bipolar junction transistor (BJT) operated in
common emitter (CE) mode. [7]

Input characteristics
The input set for the common-emitter amplifier as shown in the figure, relates an input current (IB) to an
input voltage (VBE) for various levels of output voltage (VCE).

Output characteristics
The output set relates an output current (IC) to an output voltage (VCE) for various levels of input current (IB) as
shown in the figure. The output or collector set of characteristics has three basic regions of interest, as indicated :
the active, cutoff, and saturation regions.
Note that the magnitude of IB is in μA, compared to mA of IC. Consider also that the curves of IB are not as horizontal
as those obtained for IE in the common-base configuration, indicating that the collector-to emitter voltage, VCE will
influence the magnitude of the collector current, due to “Early effect”. The active region for the common-emitter
configuration is that portion of the upper-right quadrant that has the greatest linearity, that is, that region in which
the curves for IB are nearly straight and equally spaced. In the figure, this region exists to the right of the vertical
dashed line at VCE sat and above the curve for IB equal to zero. The region to the left of VCE sat is called the saturation
region.

In the active region of a common-emitter amplifier, the base-emitter junction is forward-biased, whereas the
collector-base junction is reverse-biased.

The cutoff region for the common-emitter configuration is not as well defined as for the common-base
configuration. Note on the collector characteristics that IC is not equal to zero when IB is zero. For the common-
base configuration, when the input current IE was equal to zero, the collector current was equal only to the reverse
saturation current ICO, so that the curve IE = 0 and the voltage axis were, for all practical purposes, one.

The reason for this difference in collector characteristics can be seen from the equation
IC = α IE + ICBO
IC = α (IC + IB) + ICBO

If we consider the case, where IB = 0A, and substitute a typical value of α such as 0.996, the resulting collector
current is the following:

If ICBO were 1 μA, the resulting collector current with IB = 0A would be 250*(1 μA) = 0.25 mA, as reflected in the
output characteristics.

For linear (least distortion) amplification purposes, cutoff for the common-emitter configuration will be defined by
IC = ICEO. In other words, the region below IB = 0 μA is to be avoided if an undistorted output signal is required.
b) Write down the differences between BJT and FET. [4]
Difference in characteristic, neutral
1. BJT is a current-controlled device, whereas the FET is a voltage-controlled device.

Difference in characteristics, advantage BJT

1. BJT has a much higher sensitivity to changes in applied signals than a JFET (the variation in output
current is typically a great deal more for BJTs than for FETs for the same change in the applied
voltage).
2. The construction characteristics of some FETs can make them more sensitive to handling than BJTs.

Difference in characteristics, advantage JFET

1. JFET has a very high input impedance (one MΩ to several hundred MΩ), whereas BJT has low input
impedance (~KΩ).
2. JFET has better thermal stability compared to a BJT.
3. JFETs are usually smaller (in dimensions) than a BJT, making them particularly useful in fabrication
of integrated circuit (IC) chips.

Note : For a 4 marks question, writing any 4 of the above points would fetch full marks.

c) Explain pinch-off phenomenon in junction field effect transistor (JFET). [4]

For a n-channel JFET, as the voltage VDS is increased from 0 V to a few volts, the current will increase as determined
by Ohm’s Law, and the plot of ID vs VDS will appear as shown to the left. For the region of low values of VDS, the
resistance is essentially constant (straight slope of the curve). As VDS increases and approaches a level referred to
as VP, the depletion regions will widen, causing a noticeable reduction in channel width. The reduced path of
conduction causes the resistance to increase, and the curve in the graph shown occurs. The more horizontal the
curve, the higher the resistance, suggesting that the resistance is approaching “infinite” ohms in the horizontal
region. If VDS is increased to a level where it appears that the two depletion regions would “touch” as shown, a
condition referred to as pinch-off will result. The level of VDS that establishes this condition is referred to as pinch-
off voltage and is denoted by VP, as shown in the figure.
2. a) Draw and explain the input and output characteristics of a BJT operated in common base (CB) mode. [8]
Input characteristics
The input set for the common-base amplifier as shown in the figure, relates an input current (IE) to an input
voltage (VBE) for various levels of output voltage (VCB).

The input characteristics reveal that for fixed values of collector voltage (VCB), as the base-to-emitter voltage
increases, the emitter current increases in a manner that closely resembles the diode characteristics. However,
with increasing levels of VCB, the emitter current IE increases due to “Early effect”.

Output characteristics
The output set relates an output current (IC) to an output voltage (VCB) for various levels of input current (IE) as
shown in the figure. The output or collector set of characteristics has three basic regions of interest, as indicated :
the active, cutoff, and saturation regions.
The active region is the region normally employed for linear (undistorted) amplifiers. In particular, in the active
region the base-emitter junction is forward-biased, whereas the collector-base junction is reverse-biased.

At the lower end of the active region the emitter current (IE) is zero, and the collector current is simply that due to
the reverse saturation current, ICO, as indicated in the figure below. The current ICO is so small (microamperes) in
magnitude compared to the vertical scale of IC (mA) that it appears on virtually the same horizontal line as IC = 0.
The circuit conditions that exist when IE = 0 for the common-base configuration are shown in the figure.

As the emitter current increases above zero, the collector current increases to a magnitude essentially equal to
that of the emitter current as determined by the basic transistor-current relations. Note also the almost negligible
effect of VCB on the collector current for the active region. In the active region, IC = αIE + ICO. The second part of the
expression (~ μA) is negligible compared to the first part (~ mA). So, we can take IC ≈ αIE. However, as the curves
clearly indicate that a first approximation to the relationship between IC and IE in the active region is given by IC ≈
IE, since α ≈ 1 (Note α is always < 1).

As inferred by its name, the cutoff region is defined as that region where the collector current is 0 A. In addition,
in the cutoff region the base-emitter and collector-base junctions of a transistor are both reverse-biased.

The saturation region is defined as that region of the characteristics to the left of VCB = 0 V. The horizontal scale in
this region was expanded to clearly show the dramatic change in characteristics in this region. Note the exponential
increase in collector current as the voltage VCB increases toward 0 V. In the saturation region the base-emitter and
collector-base junctions are forward-biased. In the saturation region, IC < αIE.

b) Write down the different modes of operation of BJT for it to act as a current amplifier, a voltage amplifier
and a voltage buffer. [3]
i) Current amplifier– Common emitter
ii) Voltage amplifier– Common base
iii) Voltage buffer – Common collector.

c) Derive the relationship between α and β . Given α = 0.98, what will be the corresponding β. [2 + 2]
α (common-base amplification factor) and β (common-emitter amplification factor) are related by the
α 0.98 0.98
expression β = 1− α. So, for α = 0.98, β = 1− 0.98 or, β = 0.02 or, β = 49.
3. a) Explain the base width modulation in BJT. [3]

Taking the example of a common-emitter configuration, we observe that there is an upward slope of the output
characteristic curve. This is due to early effect i.e., base width modulation with change in reverse bias voltage, VCE.

For a particular value of base current IB (taking one from the family of curves), when the output voltage, VCE is
increased, the collector-base reverse bias increases. Consequently, the depletion width at this junction will
increase, and the effective base width will decrease. There will be lesser recombination of electron-hole pairs (EHP),
and the base current will tend to decrease. Moreover, the concentration gradient of charge carriers between
emitter and base increases, resulting in increase in emitter and collector current. Keeping the base current fixed at
a particular value, the result is an increase in collector current, IC. Thus, the output characteristic curve slopes
upwards.

Note : The same explanation can be given for a BJT in common base (CB) configuration. Either explanation is correct.

b) Draw the output characteristics of n-channel JFET showing all regions of operation. Indicate the pinch-off
voltage on the characteristics. [4]

The pinch-off voltage is VP, as shown in the figure. For VGS ≥ |VP|, the current ID is zero.

4. NULL
5. b) Draw and explain the output characteristics of n-channel enhancement type MOSFET showing
all regions of operation. [4]

The output (or drain) characteristics reveal that for the MOSFET device with VGS = 8 V, saturation occurs at a level
of VDS = 6 V. In fact, the saturation level for VDS is related to the level of applied VGS by VDS sat = VGS - VT. Obviously,
therefore, for a fixed value of VT, the higher the level of VGS, the greater is the saturation level for VDS, as shown in
the figure by the locus of saturation levels.

For the characteristics shown in the figure, the level of VT is 2 V, as revealed by the fact that the drain current has
dropped to 0 mA. In general, therefore, for values of VGS less than the threshold level, the drain current of an
enhancement type MOSFET is 0 mA.

The figure also reveals that as the level of VGS increases from VT to 8 V, the resulting saturation level for ID also
increases from a level of 0 mA to 10 mA. In addition, it is quite noticeable that the spacing between the levels of
VGS increases as the magnitude of VGS increases, resulting in ever-increasing increments in drain current.

For levels of VGS > VT, the drain current is related to the applied gate-to-source voltage by the following nonlinear
relationship:- ID = k(VGS - VT)2. Again, it is the squared term that results in the nonlinear (curved) relationship
between ID and VGS. The k term is a constant that is a function of the construction of the device.

Now, to identify the ohmic (triode) region, saturation region and cut-off region in the drain characteristics, draw
the locus of the line VDS (sat) = VGS – VT.

• The triode (ohmic) region is to the left of this locus, where VDS (sat) < VGS – VT.
• The saturation region is to the right of this locus, where VDS (sat) ≥ VGS – VT.
• The cut-off region is the region below the curve for VGS = VT, where VGS < VT.
Note : In the answer script, the different regions of operation should be drawn in the figure for the output
characteristic curves itself.

6. Find I B, IC, IE and

VCE for the voltage divider network shown in the Figure 1 below, and determine its region of
operation. R1 = R2 = 5KΩ, RE = 2KΩ, RC = 1KΩ, VCC = 10V, β = 100, VBE = 0.7V. [7 + 1 = 8]

Figure 1

The Thevenin voltage,

VTh = {R2 / (R2 + R1)} VCC

or, VTh = {5 / (5 + 5)} 10 = 5 V, and

the Thevenin resistance,

RTh = R1 || R2 = (R1 x R2) / (R1 + R2)

or, RTh = (5 x 5) / (5 + 5) = 2.5 KΩ.

Redrawing the circuit, we have

For loop 1

Applying KVL in loop 1, we get

- VTh + (IB x RTh) + VBE + (IE x RE) = 0

or, VTh – (IB x RTh) – VBE – (β + 1) IB x RE = 0

or, 5 – IB x (2.5 x 103) – 0.7 – 101 IB x (2 x 103) = 0

 or, IB = (5 – 0.7) / {103 (2.5 + 101 x 2)}

or, IB = 4.3 / (103 x 204.5)

or, IB = 21.03 μA

Therefore, IC = β IB = 100 x 21.03 μA

or, IC = 2.103 mA

Now, IE = (β + 1) IB = 101 x 21.03 μA

or, IE = 2.124 mA

For loop 2

Applying KVL in loop 2, we get

-VCC + (IC x RC) + VCE + (IE x RE) = 0

or, 10 – {(2.103 X 10-3) x (1 x 103)} – VCE – {(2.124 x 10-3) x (2 x 103)} = 0

or, VCE = 10 – 2.103 – (2.124 x2)

or, VCE = 10 – 2.103 – 4.248

or, VCE = 3.65 V.

7. What is thermal run-away? Determine the stability factor (S) with respect to reverse saturation current for
the Figure 1 above. [2 + 3]

Thermal run-away

Taking the example of a BJT in common-emitter (CE) configuration, we have

IC = β*IB + (β + 1)*ICO

where, in the second term, ICO is due to the flow of minority charge carriers, which in turn depends on the
temperature (T). With increase in temperature, ICO increases, so also IC. As a matter of fact, ICO doubles for every
100 rise in temperature.

Now, the flow of collector current, IC produces heat within the transistor. As a result, temperature increases,
ICO increases and the collector current, IC also increases. So, a cyclic process starts. Increase in temperature (T)
results in increase in the minority carrier current, ICO and consequently IC. This results in generation of heat
which raises the temperature further. This process repeats itself, and within a short period of time, the collector
current, IC will be high enough to burn the transistor. This self-destruction of an unstabilized transistor is called
thermal runaway.
Stability factor (S)

The rate of change of the collector current, IC w.r.t. the leakage current ICO, at constant input voltage VBE and
amplification factor, β is called Stability factor, S.

The Thevenin equivalent circuit for the potential divider bias circuit of Figure 1, is shown to the left.

Explanatory Note (not part of evaluation)

8. a) Write the importance of biasing of a transistor. [2]

Biasing means the application of dc voltages to establish a fixed level of current and voltage in a BJT or FET
transistor amplifier, i.e., to select the Q point (dc operating point) suitably to achieve maximum undistorted
output signal swing.

Once selected properly, the Q point should not shift because of change in IC due to variation in

 β, and
 temperature.

b) Calculate stability factor with respect to reverse saturation current for the collector to base feedback circuit.
[2]
c) Physically explain why a collector to base feedback circuit offers better thermal stability with respect to fixed
bias circuit. [2]
In fixed bias circuit, the Stability factor, S is given by the relation, S = β + 1. So, any change in β, has a direct
relationship with S. In case of collector to base feedback circuit, S depends on values of RB and RC, apart from β, as
deduced earlier.

The collector to base feedback configuration ensures that the transistor is always biased in the active region
regardless of the value of Beta (β). The DC base bias voltage is derived from the collector voltage VC, thus providing
good stability.

9. For Figure 2 below, find V CE and IC; β = 50. [3]

Figure 2

Redrawing the circuit (for convenience) as follows, we have

For loop 1

Applying KVL in loop 1, we get

- VCC + (IB x RB) + VBE + (IE x RE) = 0

or, VCC – (IB x RB) – VBE – (β + 1) (IB x RE) = 0

or, 12 – IB x (240 x 103) – 0.7 – 51 (IB x 470) = 0

or, IB = (12 – 0.7) / {103 (240 + 51 x 0.47)}

or, IB = 11.3 / (103 x 263.97)

or, IB = 42.8 μA

Therefore, IC = β IB = 50 x 42.8 μA

or, IC = 2.14 mA

For loop 2

Now, IE = (β + 1) IB = 51 x 42.8 μA

or, IE = 2.18 mA

Applying KVL in loop 2, we get

-VCC + (IC x RC) + VCE + (IE x RE) = 0

or, -12 + {(2.14 X 10-3) x (2.2 x 103)} + VCE + {(2.18 x 10-3) x 470} = 0

or, VCE = 12 – (2.14 x 2.2) – (2.18 x 0.47)

or, VCE = 12 – 4.708 – 1.025

or, VCE = 6.267 V.

10. Additional question, not part of evaluation

Why are the depletion regions for an n-channel JFET not uniform from Source to Drain during conduction ? [5]

The depletion region is wider near the top of both p - type materials. The reason for the change in width of the
region is best described through the help of the figure. Assuming a uniform resistance in the n - channel, we can
break down the resistance of the channel into the divisions appearing in in the figure. The current ID will establish
the voltage levels through the channel as indicated on the same figure. The result is that the upper region of the p
- type material will be reverse-biased by about 1.5 V, with the lower region only reverse-biased by 0.5 V. From the
discussion of the diode operation, it was found that the greater the applied reverse bias, the wider is the depletion
Region - hence the distribution of the depletion region as shown in the figure. The fact that the p – n junction is
reverse-biased for the length of the channel results in a gate current of zero amperes, as shown in the same figure.
The fact that IG = 0 A is an important characteristic of the JFET.

Reference:
1. Electronic Devices and Circuit Theory – Boylestad, Nashelsky
2. Youtube : Neso Academy – Analog Electronics.

------------------- X -------------------
Solution to Assignment 5 FM : 65

Transistors Circuits & Amplifiers

Question 1
a) Explain different feedback topologies with the help of block diagrams. [8]
Note : Much of this solution is for information purposes, especially the initial introductory part. Your answer
should be an abbreviated version of the main discussion on each feedback topology.

Negative feedback in an amplifier is the method of feeding a portion of the amplified output to the input but
in opposite phase. The phase opposition occurs as the amplifier provides 180o phase shift whereas the
feedback network doesn’t.

While the output energy is being applied to the input, for the voltage energy to be taken as feedback, the
output is taken in shunt connection and for the current energy to be taken as feedback, the output is taken in
series connection.

There are two main types of negative feedback circuits. They are −

• Negative Voltage Feedback

• Negative Current Feedback
Negative Voltage Feedback

In this method, the voltage feedback to the input of an amplifier is proportional to the output voltage. This is
further classified into two types −

• Voltage-series feedback (Voltage amplifier)

• Voltage-shunt feedback (Trans-resistance amplifier)
Negative Current Feedback

In this method, the voltage feedback to the input of amplifier is proportional to the output current. This is
further classified into two types.

• Current-series feedback (Trans-conductance amplifier)

• Current-shunt feedback (Current amplifier)
1. Voltage-Series Feedback

In the voltage series feedback circuit, a fraction of the output voltage is applied in series with the input voltage
through the feedback circuit. This is also known as shunt-driven series-fed feedback, i.e., a parallel-series
circuit. Sensing is voltage and return is also voltage.

The following figure shows the block diagram of voltage series feedback, in which it is evident that the
feedback circuit is placed in shunt with the output but in series with the input.

As the feedback circuit is connected in shunt with the output, the output impedance is decreased and due to
the series connection with the input, the input impedance is increased.

2. Voltage-Shunt Feedback

In the voltage shunt feedback circuit, a fraction of the output voltage is applied in parallel with the input
voltage through the feedback network. This is also known as shunt-driven shunt-fed feedback i.e., a parallel-
parallel proto type. Sensing is voltage and return is current.

The figure below shows the block diagram of voltage shunt feedback, in which it is evident that the feedback
circuit is placed in shunt with the output and also with the input.

As the feedback circuit is connected in shunt with the output and the input as well, both the output impedance
and the input impedance are decreased.
3. Current-Series Feedback

In the current series feedback circuit, a fraction of the output voltage is applied in series with the input voltage
through the feedback circuit. This is also known as series-driven series-fed feedback i.e., a series-series circuit.
Sensing is current and return is voltage.

The following figure shows the block diagram of current series feedback, in which it is evident that the
feedback circuit is placed in series with the output and also with the input.

As the feedback circuit is connected in series with the output and the input as well, both the output impedance
and the input impedance are increased.

4. Current-Shunt Feedback

In the current shunt feedback circuit, a fraction of the output voltage is applied in series with the input voltage
through the feedback circuit. This is also known as series-driven shunt-fed feedback i.e., a series-parallel
circuit. Sensing is current and return is also current.

The figure below shows the block diagram of current shunt feedback, in which it is evident that the feedback
circuit is placed in series with the output, but in parallel with the input.

As the feedback circuit is connected in series with the output, the output impedance is increased and due to
the parallel connection with the input, the input impedance is decreased.
 b) What are the advantages of negative feedback in an amplifier? [4]
• Higher input impedance.
• Better stabilized voltage gain.
• Improved frequency response.
• Lower output impedance.
• Reduced noise.
• More linear operation.

c) Explain Barkhausen criteria for oscillation. [4]

For a state of oscillation to be sustained in any sinusoidal oscillator circuit, certain conditions known as
Barkhausen criteria, must be fulfilled viz.

1. The loop gain must be equal to (or greater than) one.

2. The loop phase shift must be equal to zero or integral multiples of 2π.

d) Explain the operation of RC phase-shift oscillator. [4]

The phase shift oscillator consists of an inverting amplifier and an RC phase shifting network. The minimum
number of RC stages in the feedback network is three, as each section provides 600 of phase shift. The inverting
amplifier phase shifts its input by -1800, and the RC phase-lead network phase shifts the amplifier output by +1800,
giving a total phase shift of zero. The attenuated feedback signal (at the amplifier input) is amplified to reproduce
the output. In this condition the circuit is generating its own input signal; consequently, it is oscillating. The output
and feedback voltage waveforms illustrate the circuit operation.
 The RC oscillator is ideally suited to the range of audio frequencies, from a few cycles to approximately 100 KHz.
At the higher frequencies, the network impedance becomes so low that it may seriously load the amplifier,
thereby reducing its voltage gain below the required minimum value, and the oscillations will cease. At low
frequencies, the loading effect is not usually a problem and the required large resistance and capacitance values
are readily available.

The RC phase-lead network consists of three equal value resistors, and three equal value capacitors. Resistor R1
functions as the last resistor in the RC network and as the amplifier input resistor. A phase-lag network would give
a total loop phase shift of -3600, and so it would work just as well as the phase-lead network.

The frequency of the oscillator output depends upon the component values in the RC network. The circuit can be
analyzed to show that the phase shift in the feedback network is 1800 when

XC = √6 R.

This gives an oscillation frequency of

As well as phase shifting the amplifier output, the RC network attenuates the output. It can be shown that, when
the required 1800 phase shift is produced, the feedback factor β is always 1�29. This means that the amplifier
must have a closed loop voltage gain, A of at least 29 to give a loop gain βA of one; otherwise, the circuit will not
oscillate.

If the amplifier voltage gain is much greater than 29, the output waveform will be distorted. When the gain is
slightly greater than 29, a reasonably pure sine wave output is generated. The gain is usually designed to be just
over 29 to ensure that the circuit oscillates.

-------------------------------------------------------------------------------------------------------------------------------------------------------

Question 2
a) Write the characteristics of an ideal OP-AMP. [5]
Note : The last column is not part of the answer, but in one table it covers the case when the OP-AMP is not
an ideal one. This may be another question in the actual examination.

Sr. Practical OP-AMP

Parameter Ideal OP-AMP
No. (typical values for IC 741)
1 Input resistance, Ri Infinity Finite (2 MΩ)
2 Output resistance, Ro Zero Finite (75 Ω)
3 Open loop voltage gain, AvOL Infinity Finite (~ 2 x 105)
 Finite (gain drops off at low
4 Bandwidth Infinity
and high frequencies)
Slew rate
5 (Maxm rate of change of output voltage per Very high 0.5 V / µs
unit time)
Input offset voltage, VIO
6 (due to mismatch of the two transistors in Zero Very small value (1 mV)
the differential amplifier)
Input offset current, IIO
7 Zero Very small value (20 nA)
(due to mismatch of input base currents)

b) Define CMRR and explain its importance. [3]

Common-Mode Rejection Ratio (CMRR) is the ratio of the differential gain of the amplifier (Ad) divided by
the common-mode gain of the amplifier (Ac).
CMRR = Ad / Ac.
In logarithmic terms, CMRR can be expressed as
CMRR = 20 log10 (Ad / Ac).

Now, since signals applied to an OP-AMP, in general, have both in-phase and out-of-phase components,
the resulting output can be expressed as
V0 = Ad Vd + Ac Vc
or, V0 = Ad Vd {(1 + (Ac Vc) / (Ad Vd)}
or, V0 = Ad Vd {1 + (Ac / Ad) (Vc / Vd)}
or, V0 = Ad Vd {1 + (1 / CMRR) (Vc / Vd)}

Now if the value of CMRR is very high, the output voltage, V0 is almost equal to Ad Vd (i.e. product of
differential gain of the amplifier and the difference of the input voltages). This is a very significant analysis,
since for a very high CMRR, the common-mode part is almost zero.
 c) Draw and explain the transfer characteristics of an ideal OP-AMP. [5]

The characteristics of an ideal OP-AMP that results in this transfer characteristic curve, is as given in the
table accompanying answer to Question 2a).

-------------------------------------------------------------------------------------------------------------------------------------------------------

Question 3

a) Derive the voltage gain for an inverting amplifier using OP-AMP. [2]

Equating the current entering the node at the junction of R1 and Rf (which is a virtual ground) and the
current leaving it, we get,

(V1 – 0) / R1 = (0 – Vo) / Rf

or, V1 / R1 = -Vo / Rf

or, V0 = - (Rf / R1) V1.

Therefore, the voltage gain, Vo / V1 = - (Rf / R1).

b) Draw non-inverting amplifier using OP-AMP. Write the expression of the output voltage. [2]

The voltage across R1 is V1. This is equal to the output voltage, through a voltage divider of R1 and Rf, so
that

V1 = (R1 / (R1 + Rf)) V0

or, V0 / V1 = (R1 + Rf) / R1 = 1 + Rf / R1.

c) Explain the working principle of OP-AMP integrator and differentiator with proper circuit diagram and
suitable input and output waveforms. [5 + 5 = 10]

Integrator

The voltage between input and output can be derived in terms of the current I from input to output. The
voltage at the junction of R and C can be considered as ground (virtual ground), but no current goes into
ground at that point.

The capacitive impedance can be expressed as

XC = 1 / jωC = 1 / sC, where s = jω in Laplace notation.

Now, I = (V1 – 0) / R = (0 – V0) / XC

or, V1 / R = - V0 / (1/sC)
or, V1 / R = - sCV0

or, V0 / V1 = - 1 / sRC

This can be written in the time domain, as

The above equation shows that the output is the integral of the input, with an inversion and a scale
1
multiplier of . The ability to integrate a given signal provides an analog computer with the ability to solve
𝑅𝑅𝑅𝑅
differential equations, and therefore provides the ability to electrically solve analogs of physical system
operation.

Differentiator

The output of the circuit in terms of the input can be expressed as,

v0(t) = - RC d{v1(t)} / dt, where the scale factor is – RC.

Note :- Derive the output and input voltage relation, by equating the current entering the node at the
junction of C and R and the current leaving it, as shown in case of an integrator.
d) Draw the circuit and explain the operation of an inverting two input adder using OP-AMP. [3]

The circuit shown is a two-input summing amplifier circuit (adder), which provides a means of algebraically
summing (adding) two voltages, each multiplied by a constant-gain factor.

Potential at the inverting (-) terminal is zero (virtual ground). Since no current enters the OP-AMP, current
from the two voltage sources entering the node is equal to the current leaving the node towards the
output.

In the figure above Rf = 10 kΩ, R1 = 1 kΩ, and R2 = 2 kΩ.

(V1 - 0)/R1 + (V2 - 0)/R2 = (0 – VO)/Rf

or, V1/R1 + V2/R2 = – VO/Rf

or, VO = - { (Rf / R1) V1 + (Rf / R2) V2}

Now, if Rf = R1 = R2

VO = - (V1 + V2).

e) Draw the circuit for adding three voltages 3V, 5V and 7V using an OP-AMP to obtain an output voltage
of 30V. Value of the feedback resistor can be considered to be 10 KΩ. [5]

In the above circuit,

VO = - { (Rf / R1) V1 + (Rf / R2) V2 + (Rf / R3) V3 }

 Given Rf = 10 KΩ, if we choose R1 = R2 = R3 = 5 KΩ,
we will obtain an output voltage of 30 V, given V1, V2, and V3 to be 3, 5 and 7 V respectively.

f) With the help of circuit explain the operation of differential amplifier using OP-AMP. [4]

The differential amplifier circuit is the basic building block of an OP-AMP.

The circuit has two separate inputs and two separate outputs, and the emitters are connected together.
The main feature of the differential amplifier is the very large gain when opposite signals are applied to the
inputs compared to the very small (negligible) gain resulting from common inputs.

g) Find the output voltage of the circuit shown below. [5]

4
Potential at the non-inverting (+) terminal = ( ) * 3 V = 1.2 V
4+6

Potential at the inverting (-) terminal = Potential at the non-inverting (+) terminal = 1.2 V

Now, since no current enters the inverting (-) terminal of the OP-AMP, current flowing into the junction of
the 1KΩ and 3KΩ resistance is the same as the current flowing out of the junction.
 Thus,
0−1.2 1.2−𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉′
( ) =( )
1000 3000

where,

Vout’ is the output of the first stage (= input at the non-inverting (+) terminal of the 2nd stage)

or, 3 * (- 1.2) = 1.2 – Vout’

or, Vout’ = 1.2 + 3.6 = 4.8 V

Now, the output VOUT = 4.8 V, since the 2nd OP-AMP stage is a voltage follower.

h) Mention applications of an OP-AMP without any feedback (open loop). [1]

Comparator, Zero cross-over detector (which actually is an application as a comparator).

References

1. Electronic Devices Circuit Theory

Robert L. Boylestad & Louis Nashelsky, Pearson, 11th edition.

2. Electronic Devices and Circuits

David A Bell, Oxford 5th Edition.

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