Operating Systems:

Internals and Design Principles, 6/ Roadmap

E
William Stallings – Basic Elements
– Processor Registers
Chapter 1 – Instruction Execution
Computer System Overview – Interrupts
– The Memory Hierarchy
Click to edit Master subtitle style
– Cache Memory
– I/O Communication Techniques

9/14/11 Dave Bremer

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Operating System A Computer’s

Basic Elements
• Exploits the hardware resources of one or • Processor
more processors • Main Memory
• Provides a set of services to system users • I/O Modules
• Manages secondary memory and I/O • System Bus
devices

Processor Main Memory

• Controls operation, performs data • Volatile
processing – Data is typically lost when power is removed
• Two internal registers • Referred to as real memory or primary
– Memory address resister (MAR) memory
– Memory buffer register (MBR) • Consists of a set of locations defined by
• I/O address register sequentially numbers addresses
• – Containing either data or instructions
I/O buffer register
 I/O Modules System Bus
• Moves data between the computer and • Communication among processors, main
the external environment such as: memory, and I/O modules
– Storage (e.g. hard drive)
– Communications equipment
– Terminals
• Specified by an I/O Address Register
– (I/OAR)

Top-Level View Roadmap

– Basic Elements
– Processor Registers
– Instruction Execution
– Interrupts
– The Memory Hierarchy
– Cache Memory
– I/O Communication Techniques

Processor Registers User-Visible Registers

• Faster and smaller than main memory • May be referenced by machine language
• – Available to all programs – application
User-visible registers
– Enable programmer to minimize main memory programs and system programs
references by optimizing register use • Types of registers typically available are:
• – data,
Control and status registers
– – address,
Used by processor to control operating of the
processor – condition code registers.
– Used by privileged OS routines to control the
execution of programs
 Data and Control and
Address Registers Status Registers
• Data • Program counter (PC)
– Often general purpose – Contains the address of an instruction to be
– But some restrictions may apply fetched
• • Instruction register (IR)
Address
– – Contains the instruction most recently fetched
Index Register
– Segment pointer • Program status word (PSW)
– Stack pointer – Contains status information

Condition codes Roadmap

• – Basic Elements
Usually part of the control register
– – Processor Registers
Also called flags
• – Instruction Execution
Bits set by processor hardware as a result
– Interrupts
of operations
– – The Memory Hierarchy
Read only, intended for feedback regarding
the results of instruction execution. – Cache Memory
– I/O Communication Techniques

Instruction Execution Basic Instruction Cycle

• A program consists of a set of instructions
stored in memory
• Two steps
– Processor reads (fetches) instructions from
memory
– Processor executes each instruction
 Instruction Fetch Instruction Register
and Execute
• The processor fetches the instruction from • Fetched instruction loaded into instruction
memory register
• Program counter (PC) holds address of • Categories
the instruction to be fetched next – Processor-memory,
– PC is incremented after each fetch – processor-I/O,
– Data processing,
– Control

Characteristics of a Example of
Hypothetical Machine Program Execution

Roadmap Interrupts
– Basic Elements • Interrupt the normal sequencing of the
– Processor Registers processor
– Instruction Execution • Provided to improve processor utilization
– Interrupts – Most I/O devices are slower than the
– The Memory Hierarchy processor
– – Processor must pause to wait for device
Cache Memory
– I/O Communication Techniques
Common Classes Flow of Control
of Interrupts without Interrupts

Interrupts and the Transfer of Control

Instruction Cycle via Interrupts

Instruction Cycle Short I/O Wait

with Interrupts
 Long I/O wait Simple
Interrupt Processing

Changes in Memory and Multiple Interrupts

Registers for an Interrupt
• Suppose an interrupt occurs while another
interrupt is being processed.
– E.g. printing data being received via
communications line.
• Two approaches:
– Disable interrupts during interrupt processing
– Use a priority scheme.

Sequential Nested
Interrupt Processing Interrupt Processing
 Example of Multiprogramming
Nested Interrupts
• Processor has more than one program to
execute
• The sequence the programs are executed
depend on their relative priority and
whether they are waiting for I/O
• After an interrupt handler completes,
control may not return to the program that
was executing at the time of the interrupt

Roadmap Memory Hierarchy

– Basic Elements • Major constraints in memory
– Processor Registers – Amount
– Instruction Execution – Speed
– Interrupts – Expense
– The Memory Hierarchy • Faster access time, greater cost per bit
– Cache Memory • Greater capacity, smaller cost per bit
– I/O Communication Techniques • Greater capacity, slower access speed

The Memory Hierarchy Secondary Memory

• Going down the • Auxiliary memory
hierarchy • External
– Decreasing cost per bit • Nonvolatile
– Increasing capacity • Used to store program and data files
– Increasing access time
– Decreasing frequency of
access to the memory
by the processor
 Roadmap Cache Memory
– Basic Elements • Invisible to the OS
– Processor Registers – Interacts with other memory management
– Instruction Execution hardware
– Interrupts • Processor must access memory at least
– The Memory Hierarchy once per instruction cycle
– Cache Memory – Processor speed faster than memory access
– I/O Communication Techniques speed
• Exploit the principle of locality with a small
fast memory

Principal of Locality Cache and Main Memory

• More details later but in short …
• Data which is required soon is often close
to the current data
– If data is referenced, then it’s neighbour might
be needed soon.

Cache Principles Cache/Main-Memory

Structure
• Contains copy of a portion of main
memory
• Processor first checks cache
– If not found, block of memory read into cache
• Because of locality of reference, likely
future memory references are in that block
 Cache Read Operation Cache Design Issues
• Main categories are:
– Cache size
– Block size
– Mapping function
– Replacement algorithm
– Write policy

Size issues Mapping function

• Cache size • Determines which cache location the block
– Small caches have significant impact on will occupy
performance • Two constraints:
• Block size – When one block read in, another may need
– The unit of data exchanged between cache replaced
and main memory – Complexity of mapping function increases
– Larger block size means more hits circuitry costs for searching.
– But too large reduces chance of reuse.

Replacement Algorithm Write policy

• Chooses which block to replace when a • Dictates when the memory write operation
new block is to be loaded into the cache. takes place
• Ideally replacing a block that isn’t likely to • Can occur every time the block is updated
be needed again • Can occur when the block is replaced
– Impossible to guarantee – Minimize write operations
• Effective strategy is to replace a block that – Leave main memory in an obsolete state
has been used less than others
– Least Recently Used (LRU)
 Roadmap I/O Techniques
– Basic Elements • When the processor encounters an
– Processor Registers instruction relating to I/O,
– Instruction Execution – it executes that instruction by issuing a
– Interrupts command to the appropriate I/O module.
– The Memory Hierarchy • Three techniques are possible for I/O
– Cache Memory operations:
– – Programmed I/O
I/O Communication Techniques
– Interrupt-driven I/O
– Direct memory access (DMA)

Programmed I/O Programmed I/O

Instruction Set
• The I/O module performs the requested • Control
action – Used to activate and instruct device
– then sets the appropriate bits in the I/O status • Status
register – Tests status conditions
– but takes no further action to alert the • Transfer
processor.
– Read/write between process register and device
• As there are no interrupts, the processor
must determine when the instruction is
complete

Programmed Interrupt-Driven I/O

I/O Example
• Data read in a word at a • Processor issues an I/O command to a
time module
– Processor remains in status- – and then goes on to do some other useful
checking look while reading work.
• The I/O module will then interrupt the
processor to request service when it is
ready to exchange data with the
processor.
 Interrupt- Direct Memory Access
Driven I/O
• Eliminates needless • Performed by a separate module on the
waiting system
– But everything passes • When needing to read/write processor
through processor. issues a command to DMA module with:
– Whether a read or write is requested
– The address of the I/O device involved
– The starting location in memory to read/write
– The number of words to be read/written

Direct Memory Access

• I/O operation delegated to
DMA module
• Processor only involved
when beginning and
ending transfer.
• Much more efficient.