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Design and FPGA Implementation of Asynchronous Counters using Reversible

Logic Gates

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 Design and FPGA Implementation of Asynchronous Counters using
Reversible Logic Gates
Harish Naik KP1, G.Jyothi2, Dr.K.N.Murulidhara3, Dr.M.Z.Kurian4

PG Student, Dept of E&C, SSIT, Tumkur, India1

Asst Prof, Dept of E&C, SSIT, Tumkur, India2
HOD, Dept of E&C, PESCE, Mandya, India3
HOD, Dept of E&C, SSIT, Tumkur, India4
Email: [email protected]

Abstract—The basic reversible logic gates are used for reversible

operation and can be used for reversible sequential circuit II. LITERATURE SURVEY
designing. When we say reversible computing, we mean
Landauer [1] determined that the amount of energy
performing computation in such a way that any previous state of
the computation can always be reconstructed, given a description dissipated to erase each bit of information is at least kTln2
of the current state. In recent years, reversible logic has many (where k is the Boltzmann constant i.e. 3 *10^12 joule at
applications in quantum computing, DNA computing and room temperature) during any computation the intermediate
nanotechnology. This paper proposes the design& bits used to compute the final result are erased this erasure of
implementation of four bit asynchronous using reversible T bits is one of the main reason for the power dissipation.
flip-flop. The coding is done in Verilog HDL and simulated and
synthesized in Xilinx 13.1 and modelsim 6.3c.we have used
Virtex 5 FPGA for implementation. The area and power analysis
C. H. Bennett [2] in 1973 discovered that the power
is done using Cadence Tool. We hope this paper will initiate a dissipation in any device can be made zero or negligible if the
new area of research in the field of reversible sequential circuit. computation is done using reversible model. He proved his
theory with the help of the turing machine which is a
Index Terms—Reversible Logic, Reversible Logic Gate, symbolic model for computation introduced by Turing.
T Flip-Flop, Reversible Counters. Bennett also showed that the computations that are
performed on irreversible or classical machine can be
I. INTRODUCTION performed with same efficiency on the reversible machine.
Reduction of power dissipation remains one of the major Based on the above concept the research on the reversibility
goals in the VLSI circuit design for many years. R.Landauer was started in 1980's.
demonstrated in early 1960s, that irreversible hardware
computation results in energy dissipation due to the In the year 1994 Shor [3] did a remarkable research work in
information loss, regardless of its realization technique [2]. It creating an algorithm using reversibility for factorizing large
is proved that the loss of each one bit of information number with better efficiency when compared to the classical
dissipates at least KTln2 joules of energy (heat), where K is computing theory. After this the work on reversible
the Boltzmann’s constant and T is the absolute temperature
computing was started by more people in different fields such
at which operation is performed [2]. Reversible logic circuits
as nanotechnology, quantum computers and CMOS VLSI.
have theoretically zero internal power dissipation since they
do not lose information. Bennett showed that in order to
avoid KTln2 joules of energy dissipation in a circuit, it must Edward Fredkin and Tommaso Toffoli [4, 5] presented the
be built using reversible logic gates [3]. The applications of concept of reversibility and introduced new reversible gates
reversible logic are quantum computation [12], optical known as Fredkin and Toffoli reversible gates. These gates
computing [13], ultra low power CMOS design [14] and have zero power dissipation and are used as universal gates
nanotechnology [15]. in the reversible circuits..

This paper is organized as follows. Section II presents the Peres [6] introduced a new gate known as peres gate. Peres
literature survey. Section III presents the basic definitions gate is also a 3*3 gate but it is not a universal gate like the
pertaining to reversible logic. Section IV discusses the Fredkin and Toffoli gate. Even though this gate is not
reversible logic gates. Section V discusses the universal gate it is widely used in many applications because
implementation part. Section VI discusses the testing and it has less quantum cost when compared to the universal gate.
results part. Section VII gives the comparative analysis. VIII The quantum cost of the Peres gate is 4.
applications and Section IX conclude/future work of the
paper. H Thalpliyal and N Ranganathan [7] invented a reversible
gate known as TR gate. The main objective of introducing
this reversible gate was to reduce the garbage output in a

International Conference on Information & Communication Engineering (ICICE-2014)

ISBN: 978-3-643-24819-08, Bangalore, 29th June, 2014
reversible circuit. Using the combination of Fredkin and III. BASIC DEFINITIONS PERTAINING TO
Feynman gate a new gate known as Sayem gate was REVERSIBLE LOGIC
developed by Sujata S. Chiwande Prashanth R. Yelekar [9]
sayem gate is a 4*4 reversible gate and is used in designing A. Reversible function
sequential reversible circuits. The multiple output Boolean function F(x1, x2,..., xn) of n
Boolean variable is called reversible if:
H Thapliyal and N Ranganathan [8] were the first people to
introduce the reversible logic to sequential circuits. They 1. The number of outputs is equal to the number of inputs.
were successful in implementing sequential circuit such as 2. Any output pattern has a unique pre-image.
D-latch, JK latch, T latch and SR latch using Fredkin and
Feynman gate. After this more research has been done on In other words, the reversible functions are those that
sequential circuits using reversible gates. perform permutations of the set of input vectors.
B. Reversible Logic Gate
A.V.Ananthalakshmi, G.F.Sudha [11] proposed a new 4x4
A reversible gate is a logical cell that has the N number of
reversible gate and it is being used to realize the D-latch and
inputs and N number of outputs with a one-to-one mapping
D-flip-flop in the reversible domain. The transistor between the input and output vector. For the logical cell to be
representation of the proposed reversible D-flip-flop is reversible the following two conditions are not permitted.
implemented using adiabatic logic. The proposed D-flip-flop
can generate both the outputs Q and Q’. Md. Selim Al 1. Direct fan-outs from the reversible gates.
Mamun, B. K. Karmaker [12] presented a research work on 2. Feedback from a gate output directly to its input.
the design and synthesis of sequential circuits and flip-flops
that are available in digital arena; and describes a new
The block diagram of irreversible XOR gate and reversible
synthesis design of reversible counter that is optimized in XOR gate is as shown in fig 1.
terms of quantum cost, delay and garbage outputs compared
to the existing designs. They proposed a new model of
reversible T flip-flop in designing reversible counter.

Sujata S. Chiwande , Shilpa S. Katre, Sushmita S. Dalvi; (a)

Jyoti C Kolte[13] presented the introduction of basics
reversible logic gates used for reversible operation & one of
the applications as Synchronous counter. In this paper, they
proposed comparison of synchronous & asynchronous
counter using Sayem reversible gate. (b)
Fig 1(a) Irreversible XOR gate (b) Reversible XOR gate
Tehniat Banu, Manjunath Kounte [14] in recent years, there C. The number of Reversible gates (N)
is a remarkable paradigm shift in computation effiency due to
This refers to the number of reversible gates used in circuit.
information lossless computation performed by the reversible
gates. The reversible logic means performing computation in D. The number of constant inputs (CI)
such a way that using the output the input can be constructed This refers to the number of inputs that are to be maintained
and the erasure of intermediate data and energy dissipation is constant at either 0 or 1 in order to synthesize the given
eliminated. The power dissipation, a major problem due to logical function.
scalability in the VLSI devices has been addressed by using
E. The number of garbage outputs (GO)
reversible logic.
This refers to the number of unused outputs present in a
reversible circuit. One cannot avoid the garbage outputs as
V. Rajmohan, Dr. V. Ranganathan [16] they proposed a
these are very essential to achieve reversibility.
reversible T-Flip-flop. Design of reversible asynchronous
and synchronous counters is also proposed in their paper. F. Quantum cost (QC)
The key contribution of their paper is the reversible This refers to the cost of the circuit in terms of the cost of a
realization of 4-bit Asynchronous and synchronous counters primitive gate. It is calculated by knowing the number of
by using proposed reversible gates and the existing one. The primitive reversible logic gates (1*1 or 2*2) required to
proposed counter designs have the applications in building realize the circuit.
reversible ALU, reversible processor etc.
G. Flexibility
And this paper proposes a concept on efficient and This refers to the universality of a reversible logic gate in
optimized reversible sequential circuit design of realizing more functions.
asynchronous and synchronous counters.

International Conference on Information & Communication Engineering (ICICE-2014)

ISBN: 978-3-643-24819-08, Bangalore, 29th June, 2014
H. Gate Level
This refers to the number of levels in the circuit which are
required to realize the given logic functions.
I. Hardware Complexity
This refers to the total number of logic operation in a circuit.
Means the total number of AND, OR and EXOR operation in
a circuit.
J. Design constraints for Reversible Logic circuits Fig 4 Block Diagram of Proposed T Flip-Flop
In the design of any reversible logic circuits the following
points must be considered to achieve an optimized circuit.
i. Fan-out is not permitted.
ii. Minimum quantum cost.
iii. Garbage outputs must be minimum.
iv. Constant inputs must be minimum.
v. Minimum number of logic depth or gate levels.
vi. Minimum delay.

Fig 5 Reversible Positive Edge Triggered T Flip-Flop

IV. REVERSIBLE LOGIC GATES

A. B. Design of Reversible Asynchronous Counters

A reversible logic gate has equal number of input and output
terminals and there is one to one mapping between them.
Again we can say, gate is reversible if we can determine input A counter, by function, is a sequential circuit consisting a set
vector from output vector and vice-versa. Reversible gate of flip flops connected in a suitable manner to count the
should practically loose very little amount of energy. Fan-out sequence of the input pulse presented to it in digital form. In
is not allowed in reversible circuits however fan-out can be a asynchronous counters, the output transition of one flip flop
achieved using additional gates. In this paper we have serves as a source for triggering other flip flops [22].
discussed basic reversible gates like Feynman gate, Fredkin
gate, Toffoli gate, Peres gate and Sayem gate. Which we have a. Proposed 4-bit Reversible Asynchronous up Counter
used in implementing reversible sequential circuits.
The reversible design of the 4-bit asynchronous up counter is
shown in fig 6. At the output of each reversible T flip flop, the
A P=A Feynman gate is used for the complemented Q output with
Feynman the input B=1, these complemented Q outputs of each T flip
gate Q=A xor B flop trigger the subsequent T flip flop and the reversible
B
design performs the up counter design [22].
Fig 2 Feynman gate

Fig 3 SVS gate

V. REVERSIBLE SEQUENTIAL CIRCUITS IMPLEMENTATION

A. T Flip-flop using SVS gate

A flip flop is a bi-stable multivibrator. A flip flop has only

two states. In this section we propose the realization of T flip
flop using reversible SVS gate. The reversible design is
shown in fig 5. And corresponding block diagram is shown Fig 6 Proposed 4-bit Reversible Asynchronous up Counter
in fig 4. The reversible realization of T flip flop has one
constant input and it produces the garbage outputs [22].

International Conference on Information & Communication Engineering (ICICE-2014)

ISBN: 978-3-643-24819-08, Bangalore, 29th June, 2014
 b. Proposed 4-bit Reversible Asynchronous down Counter VI. TESTING AND RESULTS

The reversible design of the 4-bit asynchronous up counter is In the following sections, simulation results and FPGA
shown in fig 7. At the output of each reversible T flip flop, the implementation results using Chipscope pro analyzer of T
Feynman gate is used for the complemented Q output with flip-flop and Synchronous and Asynchronous counters are
the input B=0, these complemented Q outputs of each T flip shown.
flop trigger the subsequent T flip flop and the reversible
design performs the up counter design [22].
A. Proposed Reversible T Flip-flop using SVS gate

Fig 9 Simulation result of Proposed Reversible T flip-flop using SVS gate

Fig 7 Proposed 4-bit Reversible Asynchronous down Counter B. Proposed Design of Reversible Asynchronous Counters

c. Proposed 4-bit Reversible Asynchronous up/down Counter a. Proposed 4-bit Reversible Asynchronous up Counter

The implementation of reversible asynchronous Up/Down

Counter is shown in Fig 8. The Up/Down operation of this
reversible circuits is controlled by the control input UP/DOWN.
For UP operation, the control input should be 1 and for down
operation, the control input should be 0 [22].

Fig10 Simulation result of Proposed Reversible Asynchronous up Counter

Fig 8 Proposed 4-bit Reversible Asynchronous Up/down counter

International Conference on Information & Communication Engineering (ICICE-2014)

ISBN: 978-3-643-24819-08, Bangalore, 29th June, 2014
 c. 4-bit Reversible Asynchronous up/down Counter

Fig 11 Output results of Reversible Synchronous up Counter on FPGA using

Chipscope pro analyzer.

b. Proposed 4-bit Reversible Asynchronous down Counter

Fig 14 Simulation result of Proposed Reversible Asynchronous up/down
counters

Fig 12 Simulation result of Proposed Reversible Asynchronous down

Counter
Fig 15 Output results of Proposed Reversible Asynchronous up/down
counter on FPGA using Chipscope pro analyzer.

VII. COMPARATIVE ANALYSIS

Table I Comparative result analysis of different counter

Proposed design No of Garbage Constant

(counters) Gate outputs inputs

Async up 7 8 7

Fig 13 Output results of Proposed Reversible Asynchronous down Async down 7 8 7

Counter on FPGA using Chipscope pro analyzer.

Async up/down 7 8 7

International Conference on Information & Communication Engineering (ICICE-2014)

ISBN: 978-3-643-24819-08, Bangalore, 29th June, 2014
 designs. The counters designs have applications in building
reversible processor, reversible Johnson & ring counter,
Table II Cadence tool power analysis building reversible ALU, reversible processor.
Instance Cells Leakage Dynamic Total The design can further be extended to develop efficient
reversible counters and reversible sequential circuits.
(counter) Power Power Power
(nW) (nW) (nW) ACKNOWLEDGMENT
Async 24 17.61 2125.0 2142.6
We would like to express our sincere thanks to the
down anonymous reviewers for their critical suggestions which
Async 27 17.72 2825.9 2843.6 helped in improving the manuscript and also we express our
gratitude to our respective faculty and our parents for
up supporting this work.
Async 27 20.29 3969.6 3989.9
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up/down
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International Conference on Information & Communication Engineering (ICICE-2014)

ISBN: 978-3-643-24819-08, Bangalore, 29th June, 2014
 [15] Majid Haghparast, 2Mohammad Samadi Gharajeh, “Design of a
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[21] KP, Harish Naik, G. Jyothi, K. N. Murulidhara, and M. Z. Kurian. "A

Survey on Synchronous and Asynchronous Counters using Reversible
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3. Feb 2014..

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ISBN: 978-3-643-24819-08, Bangalore, 29th June, 2014

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