Lecture 09

Branch and Control Instructions

(ARM Cortex-M Assembly Language)

MCT-238: Embedded Systems-I

© 2018Smart
© 2018 Smart Wires
Wires Inc. Inc.
 1 INTRODUCTION TO BRANCH INSTRUCTIONS

2 CONDITIONAL BRANCH EXECUTION

IMPLEMENTING BRANCHING
3 STRUCTURES/FUNCTIONS

COMBINED COMPARE AND CONDITIONAL

4 BRANCH

5 IF-THEN CONDITIONAL INSTRUCTION BLOCK

© 2018 Smart Wires Inc. Slide 2

 INTRODUCTION TO BRANCH
INSTRUCTIONS
ARM Cortex-M4 Assembly Language

© 2018 Smart Wires Inc. Slide 3

Overview
INTRODUCTION TO BRANCH INSTRUCTIONS
• A user program for real-time application involve decision making, conditional execution,
calling subtasks or functions
• To handle these complexities, the processor architecture supports branch and control
instructions to allow the software developer to control the flow of program execution
• The Cortex-M processor supports different types of branch and control instructions with
varying complexity
1. Branch instructions (conditional and unconditional) – simple branch instructions
2. Function calls (conditional and unconditional) – requires a return address before calling the function
3. Combined compare and conditional branch – implements two operations in one instruction to
improve the branch operation efficiency
4. Conditional execution of instructions (IF-THEN instruction) – allow to map if-else and switch-case
types of higher-level conditional constructs directly to these assembly instructions
5. Table branch –

© 2018 Smart Wires Inc. Slide 4

 BRANCH INSTRUCTIONS
ARM Cortex-M4 Assembly Language

© 2018 Smart Wires Inc. Slide 5

B, BX, BL, & BLX
BRANCH INSTRUCTIONS

The most basic branch instructions, supported by Cortex-M processor, are:

• The instruction B is also called branch immediate, and BX is also termed branch
register
• For BL and BLX instructions, the address of the next instruction, following the branch
instruction, is saved to register LR (link register or R14) at the time of execution of
the branch instruction, which is used subsequently at the time of returning.

© 2018 Smart Wires Inc. Slide 6

B, BX, BL, & BLX
BRANCH INSTRUCTIONS
• The general syntax for branch instructions is given:

• {cond} is one of the condition codes.

• When the optional condition code is omitted, these branch instructions become unconditional
branches.
• On the other hand, use of any of the conditional codes makes these branch instructions become
conditional branches.
• label specifies the address of the instruction to which the branch must be performed.
• The compilation tools (assembler or compiler) are responsible to evaluate the required value of the
offset from this label to the current value of the program counter (R15 or PC) (i.e., the address of the
current B instruction being executed).
• Rm is a register containing the address to which the branch must be performed
• Bit 0 of the address contained in register Rm should be set to 1, which indicates that the code
execution is in Thumb mode. However, the address to which the branch is performed to is obtained
by resetting the bit 0 to 0.

© 2018 Smart Wires Inc. Slide 7

Conditional Code Suffixes
BRANCH INSTRUCTIONS

© 2018 Smart Wires Inc. Slide 8

Branch Ranges
BRANCH INSTRUCTIONS

© 2018 Smart Wires Inc. Slide 9

 CONDITIONAL BRANCH EXECUTION
ARM Cortex-M4 Assembly Language

© 2018 Smart Wires Inc. Slide 10

Introduction
CONDITIONAL BRANCH EXECUTION

• Conditional branch instructions are used to determine whether a branch should be

carried out and are implemented with the help of Cortex-M processor application
program status register (APSR)
• There are four bits, namely, overflow (V), carry (C), negative (N), and the zero (Z)
flags, which indicate the status of the current operation performed by the
microprocessor.
• Irrespective of their category, branch instructions work depending on the current
values of the flags but do not affect the flags.

© 2018 Smart Wires Inc. Slide 11

Introduction
CONDITIONAL BRANCH EXECUTION
• Conditional branch instructions can be broadly categorized in three groups:
1. Single-flag Branch instructions
• e.g., in making the decision whether 0x7FFF FFFF and 0x8000 0000 are equal, the microprocessor
needs to take only one flag (the Z flag in this case) into account
2. Signed Branch instructions – used when operands are treated as signed numbers
• e.g., let’s take the case of testing whether 0x7FFF FFFF is greater than 0x8000 0000 (both
signed), then 0x7FFF FFFF is greater than 0x8000 0000
3. Unsigned Branch instructions – used when the operands are interpreted as
unsigned numbers
• e.g., let’s take the case of testing whether 0x7FFF FFFF is greater than 0x8000 0000 (both
unsigned), then 0x8000 0000 is greater than 0x7FFF FFFF
• For signed/unsigned branch, we may need to consider multiple flags

© 2018 Smart Wires Inc. Slide 12

Single-Flag Branch Instructions
CONDITIONAL BRANCH EXECUTION

• BEQ, BNE, BCS, BCC, BMI,

BPL, BVS, and BVC are
examples of single-flag
branch instructions
• These single-flag instructions
can be used in different
scenarios for making
decisions

© 2018 Smart Wires Inc. Slide 13

Single-Flag Branch Instructions
CONDITIONAL BRANCH EXECUTION

The Z-Flag Usage

• The Thumb2 instruction set uses condition codes EQ (equal) and NE (not equal) with
branch instructions to check equality (==) and inequality (!=) of data objects.
• The EQ code results in true condition when Z flag is 1 while NE code gives true
condition for Z = 0

© 2018 Smart Wires Inc. Slide 14

Single-Flag Branch Instructions
CONDITIONAL BRANCH EXECUTION

The C-Flag Usage

• Using the BCC or BCS single-
flag branch instructions, we
can count the number of 1s
in each number.

© 2018 Smart Wires Inc. Slide 15

Unsigned Conditional Branch Instructions
CONDITIONAL BRANCH EXECUTION

• The carry and zero flags are used In order to implement unsigned conditional branch
• For some comparisons, either the zero or carry flag is used, while for others their
combination is used

• One example illustrating the use of unsigned conditional branch is when we need to
differentiate characters from the standard and extended ASCII character sets

© 2018 Smart Wires Inc. Slide 16

Signed Conditional Branch Instructions
CONDITIONAL BRANCH EXECUTION

• To implement the signed conditional branch, the negative, overflow, and zero flags
are used

• An example illustrating the use of signed conditional branch instructions to count the
negative numbers in an array of numbers

© 2018 Smart Wires Inc. Slide 17

 IMPLEMENTING BRANCHING
STRUCTURES
ARM Cortex-M4 Assembly Language

© 2018 Smart Wires Inc. Slide 18

Introduction
IMPLEMENTING BRANCHING STRUCTURES

• The execution flow of a program can be altered using branching structures.

• Let's discuss the following three basic branching structures.
1. If-else branching
2. Loop based branching
3. Switch-case based branching
• In the following we discuss these three basic branching structures along with their
different variants and examples.

© 2018 Smart Wires Inc. Slide 19

If-else Branching
IMPLEMENTING BRANCHING STRUCTURES

Implementing if
• The if branching structure tests a condition and based on the result of condition
testing, a set of instructions is executed.
• If the condition is true, the instructions inside the if block are executed

© 2018 Smart Wires Inc. Slide 20

If-else Branching
IMPLEMENTING BRANCHING STRUCTURES

Implementing if-else
• In case of if-else structure, there is a condition to test, while there are two different
instruction blocks.
• When the condition is true, the set of instructions corresponding to if block is
executed, otherwise the instructions inside the else block are executed.
• Omitting the else block reduces the if-else structure to if block.

© 2018 Smart Wires Inc. Slide 21

Loop Based Branching
IMPLEMENTING BRANCHING STRUCTURES

Implementing for Loop

• Looping structures allow a program to execute a set of instructions for a number of
times
• A for loop is used whenever we know in advance the number of times a set of
instructions should be executed

© 2018 Smart Wires Inc. Slide 22

Loop Based Branching
IMPLEMENTING BRANCHING STRUCTURES

Implementing while Loop

• When the number of loop iterations is not known in advance, we use while loop
• while loop is iterated until a certain condition is fulfilled

© 2018 Smart Wires Inc. Slide 23

Switch-case Based Branching
IMPLEMENTING BRANCHING STRUCTURES
• The condition testing can be performed for
multiple possible values, resulting in multiway
branching.
• For instance, a variable can be tested for three
different possible values and correspondingly
one of the three different code segments is
executed.
• This situation can be implemented using switch-
case conditional structure
• When the switch-case construct has multiple
cases, it requires multiple test or compare
operations followed by conditional branch
instructions but this type of implementation will
execute slowly if the number of cases is large

© 2018 Smart Wires Inc. Slide 24

 IMPLEMENTING FUNCTIONS
ARM Cortex-M4 Assembly Language

© 2018 Smart Wires Inc. Slide 25

Simple Function Call
IMPLEMENTING FUNCTIONS
• When BL and BLX instructions are used, the
address of the next instruction following the
branch instruction is saved to LR register (the
link register or R14)
• This address is used at the time of returning
from the called function.
• The return from the function can be
implemented using instruction BX LR, which
causes program control to return to the
calling process.
• Note that BL or BLX instructions are not used
when returning from a function or
subroutine

© 2018 Smart Wires Inc. Slide 26

Nested Function Calls
IMPLEMENTING FUNCTIONS

© 2018 Smart Wires Inc. Slide 27

Implementing Branch Operations Indirectly
IMPLEMENTING FUNCTIONS
• Other assembly programming instructions can be used to implement the branch
operation indirectly
• Example below illustrate indirect branch operation using MOV, LDR instructions

• The POP PC instruction is used to implement the return operation from a function
call, which conventionally would have been implemented using a BX LR instruction
• Some other assembly programming instructions, e.g., ADD and SUB, can also update
the PC register. However, it is recommended that these instructions should not be
used to create a branch operation

© 2018 Smart Wires Inc. Slide 28

Recursive Function Call
IMPLEMENTING FUNCTIONS

© 2018 Smart Wires Inc. Slide 29

Passing Parameters to Functions
IMPLEMENTING FUNCTIONS

• In high level languages, there are two well-known mechanisms for parameter passing
to functions:
1. Call by Value: the actual data values are passed to the called function
2. Call by Reference: the address of the data is passed to the function. Particularly useful when
dealing with data arrays.
• Unlike high-level languages, assembly language functions do not have associated
parameter lists due to which it is up to the programmer to devise strategies for
passing parameters to functions

© 2018 Smart Wires Inc. Slide 30

Passing Parameters to Functions
IMPLEMENTING FUNCTIONS

Call by Value
• For R4 = M + N - R3, where M
and N are 32-bit data.
• Addition function
implemented and the
operands are passed through
the call by value method

© 2018 Smart Wires Inc. Slide 31

Passing Parameters to Functions
IMPLEMENTING FUNCTIONS

Call by Reference
• For R4 = M + N - R3, where M
and N are 32-bit data.
• Addition function implemented
and the operands are passed
through the call by reference
method

© 2018 Smart Wires Inc. Slide 32

 COMBINED COMPARE AND
CONDITIONAL BRANCH
ARM Cortex-M4 Assembly Language

© 2018 Smart Wires Inc. Slide 33

CBZ & CBNZ Instructions
COMBINED COMPARE AND CONDITIONAL BRANCH

• CBZ and CBNZ performs comparison with zero and branch conditionally

• CBZ instruction is equivalent to two consecutive instructions, CMP (compare with

zero) followed by conditional branch BEQ
• Similarly, CBNZ is equivalent to CMP with zero followed by BNE
• APSR condition flags values are not affected by the CBZ and CBNZ instructions
• The compare and branch instructions only support forward branches

© 2018 Smart Wires Inc. Slide 34

CBZ & CBNZ Instructions
COMBINED COMPARE AND CONDITIONAL BRANCH

CBZ Example

© 2018 Smart Wires Inc. Slide 35

CBZ & CBNZ Instructions
COMBINED COMPARE AND CONDITIONAL BRANCH

CBNZ Example

© 2018 Smart Wires Inc. Slide 36

 IF-THEN CONDITIONAL
INSTRUCTION BLOCK
ARM Cortex-M4 Assembly Language

© 2018 Smart Wires Inc. Slide 37

What is If-Then Block?
IF-THEN CONDITIONAL INSTRUCTION BLOCK

• Apart from the conditional branch instructions ARM Cortex-M architecture extends
the use of condition codes to other instructions as well
• e.g., ADD and SUB instructions can be executed conditionally by using the optional condition
code
• Conditional execution of an instruction is implemented by Thumb2 ISA using If-Then
(IT) block.
• The IT instructions allow up to four succeeding instructions to be conditionally executed and
they collectively form an IT block.
• The IT block instruction is very useful for handling small conditional codes.
• It avoids branch penalties because there is no change to program flow.
• Conditional instructions, except for conditional branches, must be inside an IT instruction block.

© 2018 Smart Wires Inc. Slide 38

Syntax
IF-THEN CONDITIONAL INSTRUCTION BLOCK
• The syntax of IT instruction is

• x, y, and z are the optional conditional execution switches for second, third, and
fourth instructions in the IT block
• cond is the base condition for the IT instruction block. The first instruction following
IT instruction is executed if the cond is true
• Each of the optional condition switches x, y, and z can be either T (THEN) or E (ELSE)
• When condition switch T is used, then cond is applied to the corresponding instruction
• The use of condition switch E applies the inverse cond to the corresponding instruction

© 2018 Smart Wires Inc. Slide 39

Syntax
IF-THEN CONDITIONAL INSTRUCTION BLOCK

• In IT instruction blocks, the first instruction must be the IT instruction itself, detailing
the choice of condition switches along with the condition it checks.
• The first conditional instruction after the IT instruction must be TRUE.
• The condition codes for second through fourth instructions following the IT
instruction can be either TRUE or FALSE.
• The use of condition code with an instruction is specified with a two-letter suffix,
such as EQ or CC, appended to the instruction mnemonic.
• The conditional instructions following the IT instruction in the IT block must specify
either the condition code cond or its logical inverse as part of their instruction syntax

© 2018 Smart Wires Inc. Slide 40

Conditional Code Suffixes
IF-THEN CONDITIONAL INSTRUCTION BLOCK

• The cond operand in IT instruction

uses the same condition codes as
conditional branch
• It is possible to use AL (the always
condition) for cond in an IT
instruction.
• If this is done, all of the instructions
in the IT block must be
unconditional, and each of x, y, and
z must be T or omitted but not E.

© 2018 Smart Wires Inc. Slide 41

How Condition Code works?
IF-THEN CONDITIONAL INSTRUCTION BLOCK

• The condition code suffix appended to an instruction inside an IT block requires the
processor to test the condition code based on the status of the flags.
• If the condition test of a conditional instruction in IT block fails, the instruction
• Does not execute
• Does not write any value to its destination register
• Does not affect any of the flags
• Does not generate any exception
• This feature often eliminates the need to branch, avoiding pipeline stalls and results
in an improved execution performance and can also increase code density

© 2018 Smart Wires Inc. Slide 42

How Condition Code works?
IF-THEN CONDITIONAL INSTRUCTION BLOCK

• By default the data processing instructions do not affect the condition code flags but
can be made to by suffixing S.
• On the other hand, the comparison instructions, e.g., CMP, TST, do affect the flags
implicitly.
• The execution of an instruction in IT block is conditionally dependent on the status of
the condition flags, which are updated by a priorly executed instruction.
• The prior instruction that has updated the flags can either be the immediately
preceding instruction that updated the flags, or there may be an arbitrary number of
intermediate instructions that did not update the flags

© 2018 Smart Wires Inc. Slide 43

Examples
IF-THEN CONDITIONAL INSTRUCTION BLOCK

IF Only Block
• 3 Instructions

IF-ELSE Block
• 4 instructions

© 2018 Smart Wires Inc. Slide 44

Examples
IF-THEN CONDITIONAL INSTRUCTION BLOCK

Implementing if-else using IT block

© 2018 Smart Wires Inc. Slide 45

Examples
IF-THEN CONDITIONAL INSTRUCTION BLOCK

Implementing nested if-else using IT block

© 2018 Smart Wires Inc. Slide 46

Instruction Execution
IF-THEN CONDITIONAL INSTRUCTION BLOCK
Data Processing Instructions inside IT Block
• It is important to note that data processing instructions, encoded using 16-bit encoding, do
not update APSR when they are used inside an IT instruction block.
• If the suffix S is added to the conditionally executed instructions inside the IT block, then 32-
bit encoding of the instruction would be used by the assembler.
Interrupt Handling while inside IT Block
• In case an exception or interrupt has happened, while the processor was executing an IT
instruction block, the execution status for that IT block is stored to the stacked xPSR register
(specifically in the IT/Interrupt-Continuable Instruction [ICI] bit field).
• Once the execution of the interrupt service routine has been completed, the IT block
execution is resumed and the remaining instructions of the block can continue the execution.
• In case of multi-cycle instructions (for example, multiple load and store) inside an IT block, if
an exception occurs during its execution, the whole instruction is abandoned and restarted
after the interrupt process is completed.

© 2018 Smart Wires Inc. Slide 47

Rules for IT Block Construction
IF-THEN CONDITIONAL INSTRUCTION BLOCK
• A branch or any instruction that modifies the PC must either be outside an IT block or
must be the last instruction inside the IT block.
• Do not branch to any instruction inside an IT block, except when returning from an
exception handler
• All conditional instructions except conditional branches must be inside an IT block.
Conditional branch instructions can be the last instructions of an IT block.
• The conditional branch instructions have a larger branch range when they are used
inside an IT block.
• Each instruction inside the IT block must specify a condition code suffix that is either
the same or logical inverse of the condition code used by the IT instruction.
• The first conditional instruction inside the IT block should always use the condition
code the same as the one used by the IT instruction itself.

© 2018 Smart Wires Inc. Slide 48

IT Instruction Advantages Illustration
IF-THEN CONDITIONAL INSTRUCTION BLOCK

• Conditional execution based on IT block can provide both the code density as well as
execution speed improvement
• To validate these advantages, Greatest Common Divisor (GCD) Algorithm, proposed
by Euclid, is implemented for both with and without IT Instructions

© 2018 Smart Wires Inc. Slide 49

IT Instruction Advantages Illustration
IF-THEN CONDITIONAL INSTRUCTION BLOCK

• It is important to note that branch instructions for Cortex-M3/M4 based processors

can take from 2 to 4 cycles for their execution, depending on the alignment and
width of the target instruction.
• For the micro-controller used in this class, it takes 3 cycles for branch execution.
• On the other hand, many of the data processing instructions require one cycle for
their execution.
• The extra cycles required for the branch operation are attributed to the fact that
branch instructions require refilling of the pipeline.
• In case of conditional branch, if the condition is false then branch does not occur and
in this case the instruction only takes one cycle for its execution

© 2018 Smart Wires Inc. Slide 50

IT Instruction Advantages Illustration
IF-THEN CONDITIONAL INSTRUCTION BLOCK

• The execution performance for the GCD algorithm is superior

for the IT block-based implementation compared to the
conditional branch-based implementation
• Euclid GCD Algorithm without IT Instructions
• Seven 16-bits instructions (14 bytes of ROM used)
• Euclid GCD Algorithm with IT Instructions
• Five 16-bits instructions (10 bytes of ROM used)

© 2018 Smart Wires Inc. Slide 51

 THANK YOU
Any Questions???

© 2018 Smart Wires Inc. Slide 52