Hi3516D V300 Professional Smart IP Camera SoC

Brief Data Sheet

Issue 02

Date 2018-08-22
Copyright © HiSilicon Technologies Co., Ltd. 2018. All rights reserved.
No part of this document may be reproduced or transmitted in any form or by any means without prior
written consent of HiSilicon Technologies Co., Ltd.

Trademarks and Permissions

, , and other HiSilicon icons are trademarks of HiSilicon Technologies Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their respective
holders.

Notice
The purchased products, services and features are stipulated by the contract made between HiSilicon and
the customer. All or part of the products, services and features described in this document may not be
within the purchase scope or the usage scope. Unless otherwise specified in the contract, all statements,
information, and recommendations in this document are provided "AS IS" without warranties, guarantees
or representations of any kind, either express or implied.
The information in this document is subject to change without notice. Every effort has been made in the
preparation of this document to ensure accuracy of the contents, but all statements, information, and
recommendations in this document do not constitute a warranty of any kind, express or implied.

HiSilicon Technologies Co., Ltd.

Address: New R&D Center, Wuhe Road,
Bantian, Longgang District,
Shenzhen 518129 P. R. China
Website: http://www.hisilicon.com

Email: [email protected]
 Hi3516D V300
Hi3516D V300 Professional Smart IP Camera SoC

Key Specifications 
Local tone mapping
Sensor built-in WDR and 2F WDR (line-based/frame-
Processor Core based/DCG)
 Dual-core ARM Cortex-A7@ 900 MHz, 32 KB I-cache,  Video-/Gyro-based 6-DoF IS
32 KB D-cache, 256 KB L2 cache  ISP tuning tools for the PC
 Neon acceleration and integrated FPU Audio Encoding and Decoding
VEDU  Multi-protocol audio encoding and decoding (G.711,
 H.264 BP/MP/HP G.726, and ADPCM) by using software
 H.265 MP  Audio 3A functions (AEC, ANR, and ALC)
 I-/P-frames and SmartP reference. Security
 MJPEG/JPEG baseline  Secure boot
VEDU Performance  Hardware-based memory isolation
 Up to 2688-pixel wide and 2688 x 1944 resolution for  Hardware-based encryption and decryption algorithms
H.264/H.265 encoding and decoding. Only the decoding (including AES, DES, 3DES, and RSA)
of self-encoded streams is supported..  Hardware-based HASH algorithms
 Real-time multi-stream H.264/H.265 encoding and (SHA1/SHA256/HMAC_SHA/HMAC_SHA256)
decoding:  Hardware random number generator
− 2688 x 1536@30 fps encoding +720 x 480@30 fps  8-kbit OTP storage space
encoding + 360 x 240@30 fps encoding Video Interface
− 2688 x 1944@20 fps encoding +720 x 480@20 fps  VI
encoding + 360 x 240@20 fps encoding − 2-channel VI
− 1920 x 1080@30 fps encoding + 720 x 480@30 fps Up to 2688-pixel wide and 2688 x 1944 resolution for
encoding + 1920 x 1080@30 fps decoding input of the first channel
 JPGE encoding and decoding performance: 16M (4608 x Up to 2048-pixel wide and 2048 x 1536 resolution for
3456) @10 fps input of the second channel
 Five bit rate control modes (CBR, VBR, FixQp, AVBR, − 8-/10-/12-/14-bit RGB Bayer DC timing VI
and QpMap) − BT.601, BT.656, and BT.1120 VI interfaces
 Up to 50 Mbit/s output bit rate − MIPI, LVDS/sub-LVDS, and HiSPi
 Up to 8-ROI encoding − Compatibility with mainstream HD CMOS sensors
Smart Video Analysis provided by vendors such as Sony, ON, OmniVision,
 Neural network acceleration engine with processing and Panasonic
performance up to 1.0 TOPS − Compatibility with the electrical specifications of
 Smart computing acceleration engine (including tracking parallel and differential interfaces of various sensors
and face image correction) − Programmable sensor clock output
 VO
Video and Graphics Processing
− One BT.656/BT.1120 VO interface
 3DNR, image enhancement, and DCI
− 6-/8-bit RGB serial LCD VO and 16-/18-/24-bit RGB
 Anti-flicker processing for video and graphics output
parallel LCD VO
 1/15–16x video and graphics scaling
− 4-lane MIPI-DSI VO
 Video graphics overlay
− HDMI 1.4 output with a maximum resolution of
 90°, 180°, and 270° image rotation
1080p60
 Image mirroring and flipping
 Up to 8-region OSD overlay before encoding Audio Interface
 Audio codec, supporting 16-bit input and output
ISP
 Mono-channel differential MIC input for background NR
 3A functions (AE, AF, and AWB), supporting third-party
 Single-end dual-channel input
3A algorithms
 I2S interface for connecting to external audio codec
 FPN removal and DPC
 LSC, LDC, and purple fringing correction Peripheral Interface
 Direction-adaptive demosaic  POR
 Gamma correction, DCI, and color management and  High-precision RTC
enhancement  2-channel LSADC
 Region-adaptive dehaze  I2C interfaces, SPIs, and UART interfaces
 Multi-level NR (including BayerNR and 3DNR), detail  Three PWM interfaces
enhancement, and sharpening enhancement  Two SDIO 3.0 interfaces, supporting the 3.3 V/1.8 V level

HiSilicon Proprietary and Confidential

Issue 02 (2018-08-22) 1
Copyright © HiSilicon Technologies Co., Ltd.
 Hi3516D V300
Hi3516D V300 Professional Smart IP Camera SoC
− SD 3.0 card supported over one SDIO 3.0 interface Startup
 One USB 2.0 host/device interface Booting from the SPI NOR flash, SPI NAND flash, or eMMC
 RMII mode, TSO network acceleration, 10/100 Mbit/s
SDK
full-duplex or half-duplex mode, and PHY clock output
 Linux-4.9-based SDK
External Memory Interface  High-performance H.264 PC decoding library
 SDRAM interface  High-performance H.265 PC, Android, and iOS decoding
− 32-bit DDR3(L)/DDR4 SDRAM, supporting a libraries
maximum capacity of 16 Gbits
Physical Specifications
− Up to 1800 Mbit/s rate
 Power consumption
 SPI NOR flash interface
Typical power consumption at 4M (2688 x 1536)P30 fps:
− 1-/2-/4-line mode
TBD
− Maximum capacity of 256 MB
 Operating voltage
 SPI NAND flash interface
− 0.9 V core voltage
− Up to 24 bit/1 KB ECC performance
− 3.3 V I/O voltage (±10%)
− Maximum capacity of 1 GB
− 1.5 (1.35) V/1.2 V DDR3(L)/4 SDRAM interface
 eMMC 4.5 interface
voltage
4-bit data width
 Package

Functional Block Diagram

Image Subsystem
32bit MIPI/LVDS/
CPU Subsystem HiSPi/
DDR3(L) DDRC VPSS+VGS
DDR4 BT.1120
Cortex-A7 MP2 GDC BT.1120/
@900MHz
RGB565/888/
(32K I/32K D/
SD ISP MIPI DSI/
SDIO3.0 256K L2)
(3A/WDR) HDMI

SPI Flash/ SPI Flash/ AMBA3.0 BUS

eMMC eMMC
RTC
AI
Subsystem I2Cx8
Video Subsystem
FEPHY ETH
NNIE SPIx3
H.264/H.265/
MJPEG Codec
IVE GPIOs
USB USB 2.0
Host/Device IR
AES/DES
/3DES/HASH UARTx5
Audio
I2S
CODEC PWMx3

RSA/TRNG LSADCx2
Hi3516D V300

Hi3516D V300 is a new-generation SoC designed for the industry-dedicated smart HD IP camera. It introduces a new-generation
ISP, the latest H.265 video compression encoder, and a high-performance NNIE engine, enabling Hi3516D V300 to lead the industry
in terms of low bit rate, high image quality, intelligent processing and analysis, and low power consumption. Integrated with the
POR, RTC, audio codec, and standby wakeup circuit, Hi3516D V300 can greatly reduce the EBOM costs for customers. Hi3516D
V300 also provides similar interface designs to the HiSilicon DVR and NVR SoCs, facilitating rapid mass production.

HiSilicon Proprietary and Confidential

Issue 02 (2018-08-22) 2
Copyright © HiSilicon Technologies Co., Ltd.
 Hi3516D V300
Hi3516D V300 Professional Smart IP Camera SoC
Body size of 14 mm x 14 mm (0.55 in. x 0.55 in.), 0.65
mm (0.03 in.) ball pitch, TFBGA RoHS package with 367
pins

HiSilicon Proprietary and Confidential

Issue 02 (2018-08-22) 3
Copyright © HiSilicon Technologies Co., Ltd.
 Hi3516D V300
Hi3516D V300 Professional Smart IP Camera SoC
Hi3516D V300 HD IP Camera Solution
SPI flash DDR3

SFC DDRC
MIC Audio
codec
Speaker
RTC Coin battery

4M VICAP (ISP)
2 SDIO Wi-Fi module
CMOS sensor SPI/I C
Hi3516D V300
USB2 PC/USB flash drive
Photosensitive
component ADC
MAC FE PHY Ethernet cable
IR light PWM

UART 0 UART 1 GPIO SDXC

Debug PTZ
Alarm SD card
(RS485)

HiSilicon Proprietary and Confidential

Issue 02 (2018-08-22) 4
Copyright © HiSilicon Technologies Co., Ltd.
 Hi3516D V300
Hi3516D V300 Professional Smart IP Camera SoC

Acronyms and Abbreviations

3DNR three-dimensional noise reduction
6DoF six degrees of freedom
AE automatic exposure
AEC acoustic echo cancellation
AF automatic focus
ALC automatic level control
ANR audio noise reduction
AVBR adaptive variable bit rate
AWB automatic white balance
CBR constant bit rate
codec coder/decoder
DC digital camera
DCG Dual Conversion Gain
DCI dynamic contrast improvement
DDRC double data rate controller
DPC defect pixel correction
DVR digital video recorder
EBOM engineering bill of materials
ECC error-correcting code
FPN fixed pattern noise
I 2C inter-integrated circuit
IR infrared
LCD liquid crystal display
LDC lens distortion correction
LSADC low-speed analog-to-digital converter
LSC lens shading correction
NNIE neural network inference engine
NR noise reduction
NVR network video recorder
OSD on-screen display
OTP one-time programming
POR power-on reset
PWM pulse-width modulation
RMII reduced media-independent interface
ROI region of interest
RTC real-time clock
SDIO secure digital input/output
SoC system-on-chip
SPI serial peripheral interface
TFBGA thin & fine ball grid array
TOPS tera operations per second
UART universal asynchronous receiver transmitter
VBR variable bit rate
VENC video encoding
VI video input
VO video output
WDR wide dynamic range

HiSilicon Proprietary and Confidential

Issue 02 (2018-08-22) 5
Copyright © HiSilicon Technologies Co., Ltd.