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DDLab Hridey Arora Exp4

besto

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12 views4 pages

DDLab Hridey Arora Exp4

besto

Uploaded by

talfromnepal101
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Name and ID - Hridey Arora 2023A7PS0256U Date - Monday 30th September

Assignment
All assignments are to be submitted strictly before the start of the next lab
session through online only. Late assignments will not be entertained and
will be awarded ‘0’ marks.
1. Write Verilog code and testbench for converting 8-bit binary number to
gray code using data flow modeling.
Ans: https://www.edaplayground.com/x/dsyB
Verilog Code:
Name and ID - Hridey Arora 2023A7PS0256U Date - Monday 30th September

2. Verilog code and testbench for converting 8-bit binary number to gray
code using data flow modeling.
Ans: https://www.edaplayground.com/x/qfXu
Verilog Code:
Name and ID - Hridey Arora 2023A7PS0256U Date - Monday 30th September

3. Write the Verilog code and testbench for full subtractor using behavioral
modeling.
Ans: https://www.edaplayground.com/x/eQjZ
Verilog Code:
Name and ID - Hridey Arora 2023A7PS0256U Date - Monday 30th September

Self-Practice and self-evaluation


1. What are the advantages of data flow modelling over gate level
modelling?
2. What is the use of the “? :” operator in Verilog?
3. How can you construct an 8-bit parallel adder using 4-bit adder ICs?
4. Draw the diagram of full adder using minimum number of NAND gates
only.
5. Verilog code and testbench for half adder using data flow.
6. Verilog code and testbench for full adder using data flow modeling.
7. Verilog code and testbench for full adder using structural modeling.
8. Verilog code and testbench for half subtractor using data flow.
9. Verilog code and testbench for full subtractor using structural modeling.
10. Verilog code and testbench for 4-bit binary adder using structural
modeling.
11. Verilog code and testbench for 4-bit binary subtractor using structural
modeling.
12. Verilog code and testbench for 4-bit binary adder-cum-subtractor using
structural modeling and use control bit to change mode.
13. BCD to seven segment decoder.
14. Verilog code and testbench for converting 8-bit gray coded number into
binary using

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