Polling and Interrupts

Polling and interrupts are two different mechanisms used in computer systems to help facilitate the communication and synchronization between devices. Polling involves

Polling and interrupts are two different mechanisms used in computer

systems to help facilitate the communication and synchronization
between-devices. Polling involves continually checking the status of a
device, while interrupts allow devices to signal when an event needs
immediate attention‫‏‬

The primary distinction between an interrupt and polling lies in the communication between the CPU
and the system. With an interrupt, the system signals the CPU when it requires attention. In contrast,
during polling, the CPU continuously checks the system's status to determine if it needs to intervene.

Interrupts:

An interrupt is a signal that alerts the CPU to handle a specific task immediately. The device indicates to
the CPU that it needs its attention. When an interrupt occurs, the CPU typically suspends its current
task, handles the interrupt, and then resumes the previously paused task.

Polling:

Polling is a method where the CPU continuously checks if a system needs its attention. It's a consistent
process to ensure that the system is operating efficiently.

The Differences between Interrupt and Polling

S.No Interrupt Polling

1. In an interrupt, the device signals the CPU In polling, the CPU continuously checks
when it needs attention. if the device needs attention.

2. It is a hardware mechanism, not a protocol. It is a protocol, not a hardware

mechanism.

3. The system is managed by an interrupt In this case, the system is serviced by

handler in this case. the CPU.

4. It can occur at any given time. The CPU polls the system at specific
intervals.

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 RETI

Fig-1 : Mechanism of Interrupt

Fig-2 : Mechanism of Polling

Fig-3 : Architecture of multiple interrupts
Interrupt is the method of creating a temporary halt during program execution and allows peripheral
devices to access the microprocessor. The microprocessor responds to that interrupt with an ISR

which is a short program to instruct the microprocessor on how to handlethe interrupt.

The following image shows the types of interrupts we have in a 8086 microprocessor −

Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to
the microprocessor.

The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and
INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA called
interrupt acknowledge.

NMI
It is a single non-maskable interrupt pin - , ( having higher priority than the maskable interrupt
request pin ( - 3 1 and it is of type 2 interrupt.

When this interrupt is activated, these actions take place −

Completes the current instruction that is in progress.

Pushes the Flag register values on to the stack.

Pushes the CS value and IP value of the return address on to

the stack.

IP is loaded from the contents of the word location 00008H.

CS is loaded from the contents of the next word location 0000AH.

Interrupt flag and trap flag are reset to 0.

 Interrupt Sequence

COMPLETE CURRENT
INSTRUCTION

YES
INTERNAL
INTERRUPT?
NO
YES
NMI

NO
YES 1
ACKNOWLEDGE READ TYPE
INTR IF
INTERRUPT NUMBER
NO 0

1 COMPLET CURRENT
TF INSTRUCTION
0

EXECUTE NEXT LET TEMP = TF

INSTRUCTION

CLEAR IF & TF

PUSH CS & IP

CALL INTERRUPT
SERVICE ROUTINE

EXECUTE USER
INTERRUPT ROUTINE

POP IP & CS

Fig-4 POP FLAGS

Flow chart of the interrupt
processing sequence of the 8088 RESUME INTERRUPT
PROCEDURE
and 8086 microprocessor
Interrupt Priority

Interrupts provide a mechanism for quickly changing program environment.

Transfer of program control is initiated by the occurrence of either an event to the
microprocessor or an event in its external hardware. The 8088 and 8086
microcomputers are capable of implementing any combination of up to 256
interrupts. As Fig. below shows, they are divided into five groups.

Types of interrupts and their priority

The user defines the function of the external hardware, software, and non
maskable interrupt. For instance, hardware interrupts are often assigned to devices
such as the keyboard, printer, and timers. On the other hand, the functions of the
internal interrupts and reset are not user defined. They perform dedicated system
functions. An example of a high-priority service routine that should not be
interrupted is that for a power failure. Once initiated, this routine should be quickly
run to completion to assure that the microcomputer goes through an orderly power-
down. A keyboard should also be assigned to a high-priority interrupt. This will
assure that the keyboard buffer does not get full and lock out additional entries. On
the other hand, devices such as the floppy disk or hard disk controller are typically
assigned to a lower priority level.

Interrupt Vector Table

An address pointer table is used to link the interrupt type numbers to the
locations of their service routines in the program-storage memory. Figure below
shows a map of the pointer table in the memory of the 8086 microcomputer.

Interrupt vector table of the 8086.

 Looking at this table, we see that it contains 256 address pointers (vectors).
Which are identified as vector 0 through vector 255. That is, one pointer corresponds
to each of the interrupt types 0 through 255. These address pointers identify the
starting location of their service routines in program memory.

Example:
At what address are CS50 and IP50 stored in memory?

Solution:
Address= 4 × 50 = 200
and expressing it as a hexadecimal number results in
Address= C816

Therefore, IP50 is stored at 000C816 and CS50 at 000CA16.

Interrupt Instructions

A number of instructions are provided in the instruction set of the 8086

microprocessors for use with interrupt processing. Figure below lists these
instructions.
 Interrupt instructions.

STI enables the external interrupt request (INTR) input for operation by
setting IF, while CLI disable the external interrupt input by resetting IF.

INT n instruction is used to initiate a vectored call of a subroutine.

IRET instruction must be included at the end of each interrupt service routine.

INTO is the interrupt-on-overflow instruction. This instruction must be

included after arithmetic instructions that can result in an overflow condition,
such as divide. It tests the overflow flag, and if the flag is found to be set, a
type 4 internal interrupt is initiated.
External Hardware Interrupt Interface Signals

When an interrupt request has been recognized on the NMI pin, the 8086
initiate type 2 interrupt (CS2:IP2).

 It cannot be masked by IF.

 The NMI input is positive edge triggered. Therefore, a request for
service is automatically latched internal to the MPU.

When an interrupt request has been recognized on the INTR pin, then o If
IF= 0 then the interrupt request is ignored.
 If IF= 1 then 8086

1. saves the flag register on the stack,

2. saves the old program context on the stack,

3. and clears TF and IF.

4. respond with two pulses at INTA during interrupt acknowledge bus cycle .

The first pulse signals the external circuitry that the interrupt request has
been acknowledged and to prepare to sent the number to the 8086.

The second pulse tells the external circuitry to put the type number on the
data bus.

RESET :
 The reset input of the 8086 MPU provides a hardware means for initializing
the microcomputer.
 After reset the MPU start execution at address:

85
 CS : IP = FFFFH : 0000H

This mean the physical address is FFFF0

What instructions should be written in this address?

Internal interrupt function

It is involve four types: divide error, overflow error, single step, and breakpoint.
Single Step
The single-step function relates to an operation option of the 8086. If the trap
flag (TF) is set, the single-step mode of operation is enabled. When TF is set, the
MPU initiates a type 1 interrupt to the service routine defined by IP 1 and CS1 at
addresses 0000416 and 0000616, respectively, at the completion of every instruction

of the user program.

INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are
enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag
instruction.

The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then
the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first ‘0’
means INTA informs the external device to get ready and during the second ‘0’ the microprocessor
receives the 8 bit, say X, from the programmable interrupt controller.

These actions are taken by the microprocessor −

First completes the current instruction.

Activates INTA output and receives the interrupt type, say X.

Flag register value, CS value of the return address and IP value of the return address are pushed
on to the stack.

IP value is loaded from the contents of word location X × 4

CS is loaded from the contents of the next word location.

Interrupt flag and trap flag is reset to 0

Software Interrupts
Some instructions are inserted at the desired position into the program to create interrupts. These
interrupt instructions can be used to test the working of various interrupt handlers. It includes −

INT- Interrupt instruction with type number

It is 2-byte instruction. First byte provides the op-code and the second byte provides the interrupt type
number. There are 256 interrupt types under this group.

Its execution includes the following steps −

Flag register value is pushed on to the stack.

CS value of the return address and IP value of the return address are pushed on to the stack.

IP is loaded from the contents of the word location ‘type number’ × 4

CS is loaded from the contents of the next word location.

Interrupt Flag and Trap Flag are reset to 0

The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for type2
is 00008H and ……so on. The first five pointers are dedicated interrupt pointers. i.e. −

TYPE 0 interrupt represents division by zero situation.

TYPE 1 interrupt represents single-step execution during the debugging of a program.

TYPE 2 interrupt represents non-maskable NMI interrupt.

TYPE 3 interrupt represents break-point interrupt.

TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and
interrupts from 32 to Type 255 are available for hardware and software interrupts.
 INT 3-Break Point Interrupt Instruction
It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the program so
that when the processor reaches there, then it stops the normal execution of program and follows the
break-point procedure.

Its execution includes the following steps −

Flag register value is pushed on to the stack.

CS value of the return address and IP value of the return address are pushed on to the stack.

IP is loaded from the contents of the word location 3×4 = 0000CH

CS is loaded from the contents of the next word location.

Interrupt Flag and Trap Flag are reset to 0

INTO - Interrupt on overflow instruction

It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As the
name suggests it is a conditional interrupt instruction, i.e. it is active only when the overflow flag is set
to 1 and branches to the interrupt handler whose interrupt type number is 4. If the overflow flag is
reset then, the execution continues to the next instruction.

Its execution includes the following steps −

Flag register values are pushed on to the stack.

CS value of the return address and IP value of the return address are pushed on to the stack.

IP is loaded from the contents of word location 4×4 = 00010H

CS is loaded from the contents of the next word location.

Interrupt flag and Trap flag are reset to 0

BOUND and INTO are both conditional.

BOUND:
Example: BOUND AX, Data ; Compares AX with Data
AX is compared with DATA and DATA+1; if less than an interrupt occurs.
AX is compared with DATA+2 and DATA+3; if greater than an interrupt occurs.

* After the execution of each instruction, the microprocessor determines whether an interrupt is
active by checking, in order:

-Other instruction executions

-Single-step
-NMI
-Coprocessor segment overrun
-INTR
-INT

If one or more of these conditions are present, then the microprocessor executes the
steps described above in "Interrupt response sequence".
Hardware Interrupts
• The INTR pin must be externally decoded to select a vector.
• Any vector is possible, but the interrupt vectors between 20H and
FFH are usually used (Intel reserves vectors between 00H and
1FH).
• INTA is an output of the microprocessor to signal the external
decoder to place the interrupt number on data bus connections D7-
D0.
Timing diagram of the handshake (2x INTA cycles) [1]
Examples of Hardware Interrupts :
1) Simpliest method of generating an interrupt vector:

2) Tri-state Buffer for Generating the Interrupt Vector

vcc
gnd
3) Handling more than one IRQ:

 If any of IRQx goes low, the NAND goes low requesting an interrupt.

 Note that if more than one IRQ goes low, a unique interrupt vector is generated and
an interrupt priority needs to be defined.
o The Interrupt Vector table must be expanded to accommodate this.
Handling more than one interrupt :-
• If several INTR are generated from different peripherals
simultaneously  is necessary to decide their priority and send the
INTA signal only to the highest priority peripheral.
• Two different methods can be used to establish the priority of
interrupt requests from different peripherals
1. Polling and daisy chaining
2. Interrupt priority management hardware

Priority Allocation by Polling and Daisy-Chaining

• Polling = asking each peripheral, in a predetermined order, whether
it needs attention from the microprocessor. The first peripheral
which responds “yes” is served by the appropriate routine.
• Daisy-chaining is a method of implementing the polling scheme by
hardware
Priority Allocation by Daisy-Chaining :
• The INTA signal passes from one peripheral to the next only if the
peripheral is not requesting an interrupt.
• The first peripheral in the daisy-chain has the highest priority and the last
peripheral has the lowest priority (fixed scheme)
• Daisy chaining may be combined with software polling to determine which
routine is needed by the peripheral
Interrupt priority management hardware :
A Programmable interrupt controller(8259A) is usually used in practical
systems to determine the priority of interrupts

Example: a single
8259A connected in the
8086 [1]
• /CS must be decoded.
Other connections are
direct to micro
• Programmable IR
priority (defult: IR0
highest … IR7 lowest)

Adress decoder
Using 74LS138 address decoder:

Interfacing of 8259 with 8086 in minimum mode

Figure above shows that how an 8259 can be interfaced with the 8086 microprocessor system in minimum
mode.
In case of 8088 microprocessor same interfacing diagram can be used except M/I0 signal.

In 8088, M/IO signal is represented by IO/M signal, therefore this signal is connected to G (active high)
signal of decoder to interface 8259A in I/O mapped I/O mode.

The 74LS138 address decoder will assert the CS input of the 8259 when an I/O base address is FFF0H or FFF2H on the address bus.
The A0 input of the 8259A is used to select one of the two internal addresses in the device.
A0 of the 8259A is connected to system line Al. So the system addresses for the two internal addresses are FFF0H and FFF2H.
The data lines of an 8259 are connected to the lower half of the system data bus; because the 8086 expects to receive interrupt types on
these lower eight data lines.
RD and WR signals are connected to the system RD and WR lines.
The interrupt request signal INT from the 8259 is connected to the INTR input of the 8086 and INTA from the 8086 is connected to
INTA on the 8259A.
As we are using single 8259 in the system SP/EN pin is tied high and CAS0-CAS2 lines are left open.
The eight IR inputs are available for interrupt signals.
Cascading :
The 8259 can be easily interconnected to get multiple interrupts.

Fig below shows how 8259 can be connected in the cascade mode.

In cascade mode one 8259 is configured in Master mode and other should be configured in the Slave mode.

Each slave 8259 is identified by the number which is assigned as a part of its initialization.

Since the 8086 has only one INTR input, only one of the 8259 INT pins is connected to the 8086 INTR pin.

The 8259 connected directly into the 8086 INTR pm is referred as the master.

Each 8259A has its own addresses so that command words can be written to it and status bytes read from it.

The INT pins from other 8259 are connected to the IR inputs of the master 8259.

These cascaded 8259s are referred as slave.

The INTA signal is connected to both master and slave 8259.

The cascade pins CAS0 to CAS2 are connected from the master to the corresponding pins of the slave.

For the master these pins function as outputs, and for the slave these pins function as inputs.

The SP/EN signal is tied high for the master. However it is grounded for the slave.
Address for 8259s :

Master and slave operation :

When the slave receives an interrupt signal on one of its IR inputs, it checks mask condition and priority of the interrupt request.

If the interrupt is unmasked and its priority is higher than any other interrupt level being serviced in the slave, then the slave will send

an NT signal to the IR input of a master.

If that IR input of the master is unmasked and if that input is a higher priority than any other IR inputs currently being serviced, then

the master will send an INT signal to the 8086 INTR input.

If the INTR interrupt is enabled, the 8086 will go through its INTR interrupt procedure and sends out two INTA pulses to both the

master and the slave.

The slave ignores the first interrupt acknowledge pulse but the master outputs a 3-bit slave identification number on the CAS0-CAS2

lines.

Sending the 3-bit ID number enables the slave. When the slave receives the second INTA pulse from the 8086, the slave will send the

desired type number to the 8086 on the eight data lines.

If an interrupt signal is applied directly to one of the IR inputs of the master, the master will send the desired interrupt type to the 8086

when it receives the second INTA pulse from the 8086.

Interrupt priority management hardware
Interrupt vector number decoding: timing diagram of the handshake (2x
INTA cycles)
Interrupt priority management hardware
The 8259A may be cascaded (one master 8259A and eight slave
8259A) to provide up to 64 interrupt lines).