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Application Note AN4137

Design Guidelines for Off-line Flyback Converters
Using FPS

Abstract
helps the engineers to design SMPS easily. In order to make
This paper presents practical design guidelines for off- the design process more efficient, a software design tool,
line flyback converter employing FPS (Fairchild Power FPS design assistant that contains all the equations
Switch). Switched mode power supply (SMPS) design is described in this paper is also provided.
inherently time consuming job requiring many trade-offs and
iteration with a large number of design variables.
The step-by-step design procedure described in this paper

DR2 LP2
Bridge
rectifier -
diode VDC Rsn Vsn
C sn Np
+ + NS2
CO2 CP2 V O2
C DC -
Dsn
DR1 LP1
FPS

CL2 Drain 1 NS1

Ra CO1 C P1 V O1
Da
Vcc 3

FB GND
Line Filter Ca Na
4 2
Rd Rbias
CL1
817A R1

R L1 CB

NTC Fuse RF CF
KA431

AC line
R2

Figure 1. Basic Off-line Flyback Converter Using FPS

1. Introduction verter, which includes transformer design, output filter

design, component selection and closing the feedback loop.
Figure 1 shows the schematic of the basic off-line flyback The design procedure described herein is general enough to
converter using FPS, which also serves as the reference cir- be applied to various applications. The design procedure pre-
cuit for the design process described in this paper. Because sented in this paper is also implemented in a software design
the MOSFET and PWM controller together with various tool (FPS design assistant) to enable the engineer to finish
additional circuits are integrated into a single package, the SMPS design in a short time. In the appendix, a step-by-step
design of SMPS is much easier than the discrete MOSFET design example using the software tool is provided.
and PWM controller solution. This paper provides step-by-
step design procedure for FPS based off-line flyback con-

Rev. 1.0.0
©2003 Fairchild Semiconductor Corporation
AN4137 APPLICATION NOTE

2. Step-by-step Design Procedure

With the resulting maximum voltage ripple, the minimum
In this section, design procedure is presented using the and maximum DC link voltages are given as
schematic of the figure 1 as the reference. In general, most
FPS has the same pin configuration from pin 1 to pin 4, as V DC
min
= 2V line
min
– ∆ V DC
max
(4)
shown in figure 1.
max max
V DC = 2V line (5)
(1) STEP-1 : Determine the system specifications

- Line voltage range (Vlinemin and Vlinemax).

- Line frequency (fL).
(3) STEP-3 : Determine the maximum duty ratio (Dmax).
- Maximum output power (Po).
For CCM operation, it is recommended to set Dmax to be
- Estimated efficiency (Eff) : It is required to estimate the smaller than 0.5 in order to avoid sub-harmonic oscillation.
power conversion efficiency to calculate the maximum input Then, the output voltage reflected to the primary (VRO) and
power. If no reference data is available, set Eff = 0.7~0.75 for the maximum nominal MOSFET voltage (Vdsnom) are
low voltage output applications and Eff = 0.8~0.85 for high obtained as.
voltage output applications. D max min
V RO = ----------------------- ⋅ V DC (6)
With the estimated efficiency, the maximum input power is 1 – D max
given by V ds
nom
= 2V line
max
+ V RO (7)
P
P in = ------o- (1)
E ff
As can be seen in equation (6) and (7), the voltage stress on
For multiple output SMPS, the load occupying factor for
MOSFET can be reduced, by decreasing Dmax. However,
each output is defined as
this increases the voltage stresses on the rectifier diodes in
Po ( n ) the secondary side. Therefore, it is desirable to set Dmax as
K L ( n ) = ------------
- (2)
Po large as possible if there is enough margin in the MOSFET
where Po(n) is the maximum output power for n-th output. voltage rating. The typical value for Dmax is 0.45.
For single output SMPS, KL(1)=1.
(4) STEP-4 : Determine the transformer primary side
Considering the maximum input power, choose the proper inductance (Lm).
FPS. The FPS lineup with proper power rating is also
Flyback converter has two kinds of operation mode ; contin-
included in the software design tool.
uous conduction mode (CCM) and discontinuous conduction
mode (DCM). The operation mode changes as the load con-
dition and input voltage vary. Therefore, the inductance of
(2) STEP-2 : Determine DC link capacitor (CDC) and the the transformer primary side is determined in full load and
DC link voltage range. minimum input voltage condition as
The maximum DC link voltage ripple is obtained as
2
max P in ⋅ ( 1 – D ch ) ( V DC
min
⋅ D max )
∆ V DC = ------------------------------------------------------------ (3) L m = ---------------------------------------------
- (8)
min 2P in f s K RF
2V line ⋅ 2f L ⋅ C DC

where Dch is the DC link capacitor charging duty ratio where fs is the switching frequency and KRF is the ripple fac-
defined as shown in figure 2, which is typically about 0.2. tor defined as shown in figure 3. For DCM operation, KRF =
For universal input range (85-265Vrms), it is proper to set 1 and for CCM operation KRF < 1. For universal input range,
∆VDCmax as 10~15% of 2V line min . it is reasonable to set KRF = 0.3-0.5.
The maximum peak current and RMS current of MOSFET
DC link voltage ripple are obtained as
DC link voltage

I ds
peak ∆I
= I EDC + ----- (9)
2
∆I 2 D max
3 ( I EDC ) +  -----
T1 rms 2
I ds = -------------
- ( 10)
Dch = T1 / T2  2 3
T2
= 0.2 - 0.25

Figure 2. DC Link Voltage Waveform

©2002 Fairchild Semiconductor Corporation

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APPLICATION NOTE AN4137

P in
where I EDC = -------------------------------------
- (11)
min
V DC ⋅ D max
min
DC V D max
and ∆ I = -----------------------------------
Lm fs
(12) Aw

Check if MOSFET maximum peak current (Idspeak) is below

the pulse-by-pulse current limit level of the FPS (Ilim).

∆I I EDC
Ae
∆I I ds peak
K RF =
2 I EDC
Figure 4. Window Area and Cross Sectional Area
CCM operation : KRF < 1

(6) STEP-6 : Determine the number of turns for each

output.
∆I I EDC I ds peak First, determine the turns ratio between the primary side and
∆I the feedback controlled secondary side as a reference.
K RF =
2 I EDC
NP V R0
DCM operation : KRF =1 n = --------- = -------------------------
- (15)
N s1 V o1 + V F1
Figure 3. MOSFET Drain Current and Ripple Factor(KRF) where Np and Ns1 are the number of turns for primary side
and reference output, respectively. Vo1 is the output voltage
and VF1 is the diode forward voltage drop of the reference
(5) STEP-5 : Determine the proper core and the minimum output.
primary turns.
Then, determine the proper integer numbers for Ns1 so that
Actually, the initial selection of the core is bound to be crude resulting Np is larger than Npmin obtained from equation
since there are too many variables. One way to select the (14). Sometimes the resulting Np may be too larger than
proper core is refer to the manufacture's core selection guide. Npmin, which forces to change the core size for a big one. If it
If there is no proper reference, use the following equation as is not possible to change the core due to cost or size con-
a starting point. straint, go back to step 4 and reduce Lm by increasing the rip-
ple factor (KRF). Then, the resulting minimum number of
Ap = Aw Ae turns of the primary side will be decreased.
peak rms 4 1.143 The numer of turns for the the other output (n-th output) is
L m × I ds I ds × 10 4 4
= ------------------------------------------------------------------- × 10 ( mm ) (13) determined as
450 × 0.2 × ∆B
Vo ( n ) + VF ( n )
where Aw is the window area and Ae is the cross sectional N s ( n ) = --------------------------------- ⋅ N s1 ( turns ) ( 16 )
V o1 + V F1
area of the core in mm2 as shown in figure 4. ∆B is the max-
imum flux density swing in tesla in normal operation, which The numer of turns for Vcc winding is determined as
is typically 0.3-0.35 T for most power ferrite cores.
With a chosen core, the minimum number of turns for the V cc * + V Fa
- ⋅ N s1
N a = --------------------------- ( turns ) ( 17 )
transformer primary side to avoid saturation is given by V o1 + V F1
where Vcc* is the nominal voltage for Vcc and VFa is the
min L m I lim 6 diode forward voltage drop. Since Vcc increases as the out-
NP = ------------------ × 10 (turns) (14) put load increases, it is proper to set Vcc* as Vcc start voltage
B sat A e
to avoid the over voltage protection during the normal opera-
where Ilim is the FPS current limit level, Bsat is the saturation tion.
flux density in tesla. If there is no reference data, use Bsat
=0.35-0.4 T.

©2002 Fairchild Semiconductor Corporation

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AN4137 APPLICATION NOTE

With the determined turns of the primary side, the gap length
of the core is obtained as peak
I
o ( n ) max D dsI V R K
RO C ( n ) L ( n )
∆ V o ( n ) = ------------------------
- + ----------------------------------------------------------
- (24)
2 Co ( n ) fs ( Vo ( n ) + VF ( n ) )
 NP 1
G = 40 πA e  --------------------
- – ------ ( mm ) ( 18 ) where Co(n) is the capacitance and Rc(n) is the effective series
 1000L m A L
resistance (ESR) of the n-th output capacitor.
where AL is the AL-value with no gap in nH/turns2.
Sometimes it is impossible to meet the ripple specification
with a single output capacitor due to the high ESR of the
(7) STEP-7 : Determine the wire diameter for each electrolytic capacitor. Then, additional LC filter (post filter)
winding based on the rms current of the each output. can be used. When using the post filter, be careful not to
The rms current of the n-th scondary winding is obtained as place the corner frequency too low. Too low corner fre-
quency may make the system unstable or limit the control
bandwidth. It is proper to set the corner frequency of the post
rms rms 1 – D max V RO ⋅ K L ( n )
I sec ( n ) = I ds ----------------------- ⋅ -------------------------------------- ( 19 ) filter to be around 1/10~1/5 of the switching frequency.
D max ( Vo ( n ) + VF ( n ) )

where KL(n) is the load occupying factor for n-th output

(10) STEP-10 : Design the RCD snubber.
defined in equation (2).
The power loss of the snubber network in normal operation
The current density is typically 5A/mm2 when the wire is
is obtained as
long (>1m). When the wire is short with small number of
turns, current density of 6-10 A/mm2 is also acceptable.
2
Avoid using wire with diameter larger than 1 mm to avoid V sn 1 peak 2
- = --- L l K ( I ds
Loss sn = ----------- ) fs (25)
severe eddy current losses and to make winding easier. R sn 2
For high current output, it is better to use parallel winding
where Llk is the primary side leakage inductance, Vsn is the
with multiple strands of thinner wire to minimize skin effect.
snubber capacitor voltage in normal operation and Rsn is the
Check if the winding window area of the core is enough to snubber resistor. Based on the power loss, the snubber resis-
accommodate the wires. The required window area is given tor with proper rated wattage should be chosen. The snubber
by capacitor voltage should be larger than the reflected output
voltage (VRO). It is typical to set Vsn to be 50~100V higher
Aw = Ac ⁄ AF (20) than VRO. The ripple of the snubber capacitor voltage in nor-
mal operation is obtained as
where Ac is the actual conductor area and KF is the fill
factor. Typically the fill factor is 0.2-0.3.
sn V
∆ V sn = -----------------------
- (26)
C sn R sn f s
(8) STEP-8 : Choose the rectifier diode in the secondary
side based on the voltage and current ratings.
In general, 5-10% ripple is reasonable.
The maximum voltage and the rms current of the rectifier
The maximum snubber capacitor voltage during transient or
diode of the n-th output are obtained as
over load situation is obtained as
max
V DC ⋅ ( Vo ( n ) + VF ( n ) )
V D ( n ) = V o ( n ) + ---------------------------------------------------------------
- ( 21 ) max 1
V RO V sn = --- R sn L l k f s ⋅ I lim (27)
2
rms rms 1 – D max V RO K L ( n )
ID ( n ) = I ds ----------------------- ⋅ -------------------------------------- ( 22 ) Then, the maximum voltage stress of MOSFET is given by
D max ( Vo ( n ) + VF ( n ) )

max max max

V ds = 2V line + V sn (28)

(9) STEP-9 : Determine the output capacitor considering

Design Vdsmax to be below 90 % of the rated voltage of
the voltage and current ripple. MOSFET. Be careful when measuring the primary side leak-
age inductance. By simply measuring the primary side
The ripple current of the n-th output capacitor is obtained as
inductance with other outputs shorted, somewhat larger
value of leakage inductance is obtained since the secondary
rms rms 2 2 side leakage inductance for each output is reflected to the
I cap ( n ) = ( ID ( n) ) – Io ( n ) (23)
primary side.
where Io(n) is the load current of n-th output. The ripple
current should be equal to or smaller than the ripple current
specification of the capacitor.
The voltage ripple on n-th output is given by

©2002 Fairchild Semiconductor Corporation

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APPLICATION NOTE AN4137

2
Voltage rating 1 RL ( 1 – D ) (1 + D)
of MOSFET Voltage Margin
w z = -------------------- , w rz = ----------------------------------------
- and w p = -------------------
R c1 C o1 DL m ( N s1 ⁄ N p )
2 R L C o1
Effect of stary inductance (10-20V)

When the converter has more than one output, the DC and
Snubber capacitor low frequency control-to-output transfer function are propor-
voltage (Vsn) Reflected output voltage tional to the parallel combination of all load resistance,
(VRO )
adjusted by the square of the turns ratio. Therefore, the effec-
tive load resistance is used in equation (29) instead of the
DC link voltage actual load resistance of Vo1.
(VDC )
The voltage-to-current conversion ratio of FPS, K is defined
0V
as

I pk I lim
K = ---------
- = -------
- (30)
V FB 3
∆Vsn Snubber capacitor
voltage (Vsn) where Ipk is the peak drain current and VFB is the feedback
voltage for a given operating condition.
0V

Figure 5. MOSFET voltage and snubber capacitor voltage Notice that there is right half plane (RHP) zero (wrz) in the
control-to-output transfer function of equation (29). Because
the RHP zero reduces the phase by 90 degrees, the crossover
frequency should be placed below the RHP zero.
(11) STEP-11 : Design the feed back loop.
Since FPS employs current mode control as shown in figure Figure 7 shows variation of CCM flyback converter control-
6, the feedback loop can be simply implemented with a to-output transfer function according to the input voltage. As
one-pole and one-zero compensation circuit. can be seen, the system poles and zeros together with the DC
gain change according to input voltage. The gain is highest
in high input voltage condition and the RHP zero is lowest in
FPS vo1' vo1 low input voltage condition.
Lp1 Figure 8 shows variation of CCM flyback converter control-
vFB RD
ibias to-output transfer function according to the load. As can be
seen, the low frequency gain does not change according to
iD Rbias
the load condition and the RHP zero is lowest in full load
CB
1:1 condition.
B R1
CF RF For DCM operation, the control-to-output transfer function
KA431 of the flyback converter using FPS is given by

R2
v̂ o1 V o1 ( 1 + s ⁄ w z )
- = ---------- ⋅ ----------------------------
G vc = -------- (31)
v̂ FB V FB ( 1 + s ⁄ w p )
Ipk
1
where w z = -------------------- , w p = 2 ⁄ R L C o1
MOSFET R c1 C o1
current
Figure 6. Control Block Diagram
Figure 9 shows the variation of the control-to-output transfer
For CCM operation, the control-to-output transfer function function of flyback converter in DCM according to the load.
of the flyback converter using FPS is given by Contrary to the flyback converter in CCM, there is no RHP
zero and the DC gain does not change as the input voltage
v̂ o1
G vc = --------
- varies. As can be seen, the overall gain except for the DC
v̂ FB gain is highest in full load condition
K ⋅ R L V DC ( N p ⁄ N s1 ) ( 1 + s ⁄ w z ) ( 1 – s ⁄ w rz )
= ----------------------------------------------------- ⋅ ---------------------------------------------------------- ( 29 )
2V RO + v DC 1 + s ⁄ wp

where VDC is the DC input voltage, RL is the effective total

load resistance of the controlled output defined as Vo12/Po,

©2002 Fairchild Semiconductor Corporation

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AN4137 APPLICATION NOTE

When the input voltage and the load current vary over wide
range, it is not easy to determine the worst case for the feed-
40 dB back loop design. The gain together with zeros and poles
fp move according to the operating condition. Moreover, con-
20 dB
verter operating in CCM enters into DCM as the load current
decreases and/or input voltage increases.
fp One simple and practical way to this problem is designing
High input voltage
0 dB
the feedback loop for low input voltage and full load condi-
fz
Low input voltage tion with enough phase and gain margin. For universal input
-20 dB
frz
range, the RHP zero is lowest in low input voltage and full
fz frz load condition when the converter operates in CCM. While,
-40 dB the gain increases only about 6dB as the operating condition
is changed from low line to high line condition. Therefore,
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
by designing the feedback loop with more than 45 degrees
Figure 7. CCM flyback converter control-to output trans- phase margin in low line and full load condition, the stability
fer function variation according to the input voltage all over the operation ranges can be guaranteed.

The procedure to design the feedback loop is as follows

40 dB (a) Determine the crossover frequency (fc). For CCM mode
fp Light load
flyback, set fc below 1/3 of right half plane (RHP) zero to
20 dB minimize the effect of RHP zero. For DCM mode fc can be
placed at higher frequency, since there is no RHP zero.
fp
0 dB (b) When additional LC filter is employed, the crossover fre-
Heavy load quency should be placed below 1/3 of the corner frequency
-20 dB of the LC filter, since it introduces -180 degrees phase drop.
frz Never place the crossover frequency beyond the corner fre-
fz frz
quency of the LC filter. If the crossover frequency is too
-40 dB
close the corner frequency, the controller should be designed
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz to have enough phase margin more than about 90 degress
Figure 8. CCM flyback converter control-to output trans- when ignoring the effect of post filter.
fer function variation according to the load
(c) Determine the DC gain of the compensator (wi/wzc) to
cancel the control-to-output gain at fc.
(d) Place compensator zero (fzc) around fc/3.
40 dB
(e) Place compensator pole (fpc) above 3fc.
fp
20 dB fp

Heavy load Loog gain T

40 dB
0 dB

20 dB fzc fpc
-20 dB fz
Light load Compensator
fp wi/wzc
fz 0 dB
-40 dB fc
Control to output
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
-20 dB frz
Figure 9. DCM flyback converter control-to output trans-
fer function variation according to the load fz
-40 dB
The feedback compensation network transfer function of
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
figure 6 is obtained as
Figure 10. Compensator design

ˆ w i 1 + s ⁄ w zc
v FB
-------- = - ----- ⋅ ---------------------------
ˆ-
(32)
v o1 s 1 + 1 ⁄ w pc

RB 1 1
where w i = -------------------------
- , w zc = --------------------------------- , w pc = ---------------
R1 RD CF s ( R F + R 1 )C F RB CB

©2002 Fairchild Semiconductor Corporation

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APPLICATION NOTE AN4137

When determining the feedback circuit component, there are

some restrictions as follows.
(a) The capacitor connected to feedback pin (CB) is related
with the shutdown delay time in overload situation as

T delay = ( V SD – 3 ) ⋅ C B ⁄ I delay (33)

where VSD is the shutdown feedback voltage and Idelay is the

shutdown delay current. These vales are given in the data
sheet. In general, 10 ~ 100 ms delay time is proper for most
applications. In some cases, the bandwidth may be limited
due to the required delay time of the over load protection.
(b) The resistor Rbias and RD used together with opto-cou-
pler and KA431 should be designed to provide proper oper-
ating current for KA431 and to guarantee the full swing of
the feedback voltage of FPS. In general, the minimum cath-
ode voltage and current for KA431 are 2.5V and 1mA,
respectively. Therefore, Rbias and RD should be designed to
satisfy the following conditions.

V o1 – V OP – 2.5
----------------------------------------
- > I FB (34)
RD
V OP
-------------
- > 1mA (35)
R bias
where VOP is opto-diode forward voltage drop, which is typ-
ically 1V and IFB is the feedback current of FPS, which is
typically 1mA. For example, Rbias< 1kΩ and RD < 1.5kΩ
for Vo1=5V.

©2002 Fairchild Semiconductor Corporation

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AN4137 APPLICATION NOTE

- Summary of symbols -

Aw : Window area of the core in mm2

Ae : Cross sectional area of the core in mm2
Bsat : Saturation flux density in tesla.
∆B : Maximum flux density swing in tesla in normal operation
Co : Capacitance of the output capacitor.
Dmax : Maximum duty cycle ratio
Eff : Estimated efficiency
fL : Line frequency
fs : Switching frequency
Idspeak : Maximum peak current of MOSFET
Idsrms : RMS current of MOSFET
Ilim : FPS current limit level.
Isec(n)rms : RMS current of the secondary winding for n-th output
ID(n)rms : Maximum rms current of the rectifier diode for n-th output
Icap(n)rms : RMS Ripple current of the output capacitor for n-th output
Io : Output load current
KL(n) : Load occupying factor for n-th output
KRF : Current ripple factor
Lm : Transformer primary side inductance
Losssn : Power loss of the snubber network in normal operation
Llk : Primary side leakage inductance of the transformer
Npmin : The minimum number of turns for the transformer primary side to avoid saturation
Np : Number of turns for primary side
Ns1 : Number of turns for the reference output
Po : Maximum output power
Pin : Maximum input power
Rc : Effective series resistance (ESR) of the output capacitor.
Rsn : Snubber resistor
RL : Effective total output load resistor
Vlinemin : Minimum line voltage
Vlinemax : Maximum line voltage
VDCmin : Minimum DC link voltage
VDCmax : Maximum DC line voltage
Vdsnom : Maximum nominal MOSFET voltage
Vo1 : Output voltage of the reference output.
VF1 : Diode forward voltage drop of the reference output.
Vcc* : Nominal voltage for Vcc
VFa : Diode forward voltage drop of Vcc winding
∆VDCmax : Maximum DC link voltage ripple
VD(n) : Maximum voltage of the rectifier diode for n-th output
∆Vo(n) : Output voltage ripple for n-th output
VRO : Output voltage reflected to the primary
Vsn : Snubber capacitor voltage in normal operation
∆Vsn : Snubber capacitor voltage ripple
Vsnmax : Maximum snubber capacitor voltage during transient or over load situation
Vdsmax : Maximum voltage stress of MOSFET

©2003 Fairchild Semiconductor Corporation

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APPLICATION NOTE AN4137

Appendix. Design Example Using FPS Design Assistant (1)

Target system : LCD monitor adaptor
- The height of SMPS is restricted (<20mm). The size of the heat sink is also limited.
- Input : universal input (85V-265Vrms)
- Output : 5V/2A, 12V/3A

FPS Design Assistant ver.1.0 By Choi

Blue cell is the input parameters
Red cell is the output parameters

1. Defin e specifications of the SMPS

Minimum Line voltage (V_line.min) 85 V.rms
Maximum Line voltage (V_line.max) 265 V.rms
Line frequency (fL) 60 Hz

Vo Io Po KL
1st output for feedback 5 V 2.4 A 12 W 25 %
2nd output 12 V 3 A 36 W 75 %
3rd output 0 V 0 A 0 W 0 %
4th output 0 V 0 A 0 W 0 %
5th output 0 V 0 A 0 W 0 %
6th output 0 V 0 A 0 W 0 %
Maximum output power (Po) = 48.0 W
Estimated efficiency (Eff) 80 %
Maximum input power (Pin) = 60.0 W

2. Calculate the minimum input voltage

DC link capacitor 100 uF
DC link voltage ripple = 33 V
Minimum DC link voltage = 87 V
Maximum DC link voltage = 375 V

3. Determin e Maximum duty ratio (Dmax)

Maximum duty ratio 0.45
Maximum nominal MOSFET voltage = 446 V
Output voltage reflected to primary = 71 V K RF = 1 ( DCM )
K RF < 1 (CCM )
4. Determin e transfor mer primary inductance (Lm)
Switching frequency of FPS (kHz) 67 kHz ∆I I ED
Ripple factor 0.28
Primary side inductance (Lm) = 680 uH
Maximum peak drain c urrent = 1.96 A ∆I
K RF =
RMS drain current 1.04 A ## 2 I EDC
Maximum DC link voltage in CCM 197 V

5. Determin e proper core and minimum primary turns

Current limit of FPS 2.20 A
Maximum flux density swing 0.35 T
Saturation flux density (Bsat) 0.42 T
4
Estimated AP value of core = 3929 mm
Cross sectional area of core (Ae) 58 mm2
Minimum primary turns = 61.4 T

For a first step, EFD2525 is chosen

(Ae=58mm2, Aw=77mm2, Ap=4466mm4)

©2003 Fairchild Semiconductor Corporation

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AN4137 APPLICATION NOTE

6. Determine the numner of turns for each outputs

Vo VF # of turns
Vcc (Use Vcc start voltage) 12 V 1.2 V 12 => 12 T
1st output for feedback 5 V 0.5 V 5 => 5 T
2nd output 12 V 1.2 V 12 => 12 T
3rd output 0 V 0 V 0 => 0 T
4th output 0 V 0 V 0 => 0 T
5th output 0 V 0 V 0 => 0 T
6th output 0 V 0 V 0 => 0 T
VF : Forward voltage drop of rectifier diode Primary turns = 65 T
->enough turns
2
AL value (no gap) 2130 nH/T
Gap length (center pole gap)= 0.41384 mm

7. Determine proper wire for each output

Diameter Parallel Irms (A/mm 2)

Primary winding 0.5 mm 1 T 1.04 A 5.31
Vcc winding 0.3 mm 1 T 0.10 A 1.42
1st output winding 0.4 mm 4 T 3.73 A 7.41
2nd output winding 0.4 mm 4 T 4.66 A 9.27
3rd output winding 0 mm 0 T #### A #DIV/0!
4th output winding 0 mm 0 T #### A #DIV/0!
5th output winding 0 mm 0 T #### A #DIV/0!
6th output winding 0 mm 0 T #### A #DIV/0!
Copper area = 22.0782 mm2
Fill factor 0.2
Required window area > Aw
Required window area 110.391 mm2
2
(EFD2525 : Aw=77mm )

Replace EFD2525 with EFD3030 and

GO Back to Step 5

2 2
# EFD3030 : Ae=69mm , Aw=87mm ,

4
Ap=6003mm

5. Determine proper core and minimum primary turns

Current limit of FPS 2.20 A
Maximum flux density swing 0.35 T
Saturation flux density (Bsat) 0.42 T
Estimated AP value of core = 3929 mm4
2
Cross sectional area of core (Ae) 69 mm
Minimum primary turns = 51.6 T

6. Determine the numner of turns for each outputs

Vo VF # of turns
Vcc (Use Vcc start voltage) 12 V 1.2 V 9.6 => 10 T
1st output for feedback 5 V 0.5 V 4 => 4 T
2nd output 12 V 1.2 V 9.6 => 10 T
3rd output 0 V 0 V 0 => 0 T
4th output 0 V 0 V 0 => 0 T
5th output 0 V 0 V 0 => 0 T
6th output 0 V 0 V 0 => 0 T
VF : Forward voltage drop of rectifier diode Primary turns = 52 T
->enough turns
2
AL value (no gap) 2130 nH/T
Gap length (center pole gap)= 0.30044 mm

©2003 Fairchild Semiconductor Corporation

10
APPLICATION NOTE AN4137

7. Determine proper wire for each output

2
Diameter Parallel Irms (A/mm )
Primary winding 0.5 mm 1 T 1.04 A 5.31
Vcc winding 0.3 mm 1 T 0.10 A 1.42
1st output winding 0.4 mm 4 T 3.73 A 7.41
2nd output winding 0.4 mm 4 T 4.66 A 9.27
3rd output winding 0 mm 0 T #### A #DIV/0!
4th output winding 0 mm 0 T #### A #DIV/0!
5th output winding 0 mm 0 T #### A #DIV/0!
6th output winding 0 mm 0 T #### A #DIV/0!
2
Copper area = 17.8918 mm
Fill factor 0.2
2
Required window area 89.459 mm

8. Determine the rectifier diodes in the se condary side

Reverse voltage Rms Current

Vcc diode 82 V 0.10 A
1st output diode 34 V 3.73 A
2nd output diode 82 V 4.66 A
3rd output diode 0 V #### A
4th output diode 0 V #### A
5th output diode 0 V #### A
6th output diode 0 V #### A

9. Determine the output capacitor

Capacitance ESR Current Voltage

ripple Ripple
1st output capacitor 1000 uF 30 mΩ 2.8 V 0.21 V
2nd output capacitor 1000 uF 40 mΩ 4.0 V 0.33 V
3rd output capacitor 0 uF 50 mΩ #### V #### V
4th output capacitor 0 uF 50 mΩ #### V #### V
5th output capacitor 0 uF 50 mΩ #### V #### V
6th output capacitor 0 uF 50 mΩ #### V #### V

10. Design RCD snubber

Primary side leakage inductance 4 uH
Nominal Voltage of snubber capacitor 120 V
Nominal snubber capacitor voltage rippl 5 %
Snubber resistor = 27.8821 ㏀
Snubber capacitor = 10.7061 nF
Power loss in snubber resistor = 0.51646 W (In Normal Operation)
Maximum snubber capacitor voltage= 134.474 V
Maximum MOSFET voltage = 509.24 V

©2003 Fairchild Semiconductor Corporation

11
AN4137 APPLICATION NOTE

11. Design Feedback control loop

Control-to-output DC gain = 2
Control-to-output zero = 5,308 Hz
Control-to-output RHP zero = 54,862 Hz
Control-to-output pole = 306 Hz FPS vo ' vo

vFB RD
ibias
Voltage divider resistor (R1) 5.6 ㏀ R bia s
iD
Voltage divider resistor (R2) 5.6 ㏀ CB
1:1
B
Opto coupler diode resistor (RD ) 1 ㏀ CF RF R1

431 Bias resistor (Rbias) 1.2 ㏀ 431

Feeback pin capacitor (CB) = 10 nF R2

Feedback Capacitor (CF) = 33 nF
Feedback resistor (RF) = 4.7 ㏀

Feedback integrator gain (fi) = 2,585 Hz

Feedback zero (fz) = 468.478 Hz
Feedback pole (fp) = 5307.86 Hz

60
Contorl-to-output
16 5.44145 44 50 16 # -88.2 #
Compensator
40 25 5.42444 40 46 25 # -87.2 #
T
40 5.37983 36 42 40 # -85.5 #
20
63 5.2733 32 38 63 # -83 #
Gain (dB)

100 5.01343 28 33 100 # -79 #

160 4.40599 25 29 160 # -72.9 #
0
10 100 250 3.23936 21
1000 25
10000 250 # 100000
-64.6 #
400 1.14564 19 20 400 # -53.8 #
-20
630 -1.6838 17 15 630 # -43.4 #
1000 -5.075 16 10 1000 # -35.7 #
-40 1600 -8.6966 15 6.1 1600 # -33.1 #
2500 -11.984 14 2.1 2500 # -35.8 #
0 4000 -14.93 13 -2 4000 # -43.7 #
10 100 6300 -16.962
1000 11 -6
10000 6300 # 100000
-54.1 #
-30 10000 -18.122 8.3 -10 #### # -64.7 #
16000 -18.532 4.8 -14 #### # -73.3 #
25000 -18.328 1.2 -17 #### # -79.1 #
Phase (degree)

-60
40000 -17.411 -3 -20 #### # -83.1 #
-90
63000 -15.655 -7 -22 #### # -85.6 #
100000 -12.969 -11 -24 #### # -87.2 #
-120

-150

-180

©2003 Fairchild Semiconductor Corporation

12
APPLICATION NOTE AN4137

Design Summary
• For the FPS, FSDM0565R is chosen. This device has a fixed switching frequency of 67kHz. Startup and soft-start circuits
are implemented inside of the device. It consumes under 1W at 265VAC with 0.5W load with an advanced burst-mode
operation
• Since the target system is LCD monitor adaptor, low profile ferrite core (EFD3030) is chosen.
• For output diodes, diodes having rated current more than twice of the actual RMS current are selected due to the limitation
of the heat sink size.
• The control bandwidth is 3kHz. Since the crossover frequency is too close the corner frequency of the post filter (additional
LC filter), the controller is designed to have enough phase margin of 85 degrees when ignoring the effect of the post filter.
• To limit the current, 10 ohms resistor (Ra) is used in series with the Vcc diode.
• To prevent startup with low input voltage, 56k ohms resistor (Rstr) is used on the startup pin.
Figure 1 shows the final schematic of the flyback converter designed by FPS Design Assistant.

DR1
GBLA06
(4A/600V) R sn 10nF 1000uF
27k Csn 1kV Np 25V
NS2 CO2
CDC 2W VO2 12V
Rstr
100uF/400V 56k UF4007
Dsn
(1000V/1A) L p1
DR2 1.2uH

1.5nF/275Vac 470uF
Vstr UF4003 1000uF 10V VO1
Drain (200V/1A) NS1
10V
FPS Ra 10 Cp1 5V
CL2 CL2 Da Co1
(DM0565R) Vcc

FB GND
Line Filter Ca Na
22uF 1.2k Rd Rbias
CL1 0.47uF/275Vac
1k 5.6k
817A
R1
R L1 1.5M CB 33nF
4.7k
NTC 10nF
Fuse RF CF
5D-13
KA431
5.6k
AC line
R2

Figure 1. The final schematic of flyback converter

©2002 Fairchild Semiconductor Corporation

13
AN4137 APPLICATION NOTE

by Hang-Seok Choi / Ph. D

FPS Application Group / Fairchild Semiconductor

Phone : +82-32-680-1383 Facsimile : +82-32-680-1317
E-mail : [email protected]

KA1M0280RB, KA1M0380RB, KA1L0380RB, KA1H0680B, KA1M0680B, KA1H0680RFB, KA1M0680RB, KA1M0880B,

KA1M0880BF, KA1M0880D, KA1H0165RN, KA1H0165R, KA1M0265R, KA1M0365R, KA1H0565R, KA1M0565R,
KA1M0765R, KA1M0965R, KA5M0280R, KA5H0280R, KA5H0380R, KA5M0380R, KA5L0380R, KA5P0680C, KA5H0165R,
KA5M0165R, KA5L0165R, KA5H0165RN, KA5M0165RN, KA5L0165RN, KA5H02659RN, KA5M02659RN, KA5H0265RC,
KA5M0265R, KA5L0265R, KA5M0365RN, KA5L0365RN, KA5H0365R, KA5M0365R, KA5L0365R, KA5M0765RQC,
KA5M0965Q, FS6M07652RTC, FS6M12653RTC, FS7M0680, FS7M0880, FSDH0165, FSDH0165D, FSDH565, FSD200,
FSD200M, FSD210, FSD210M, FSDM311, FSDL312, FSDL0165RN, FSDL0165RL, FSDH0265RN, FSDM0265RL,
FSDM0265RN, FSDM0365RN, FSDL0365RL, FSDL0365RN, FSDM0565R, FSDM07652R

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPROATION. As used herein:

1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

www.fairchildsemi.com

10/9/03 0.0m 002

Stock#ANxxxxxxxxx
 2003 Fairchild Semiconductor Corporation
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