King Greyan C.

Vidal
CpE_3D
CPE 314 INTRO TO HDL
LABORATORY 4
Behavioral Modeling in Verilog

Objective/s:

1. To understand the difference between blocking and nonblocking assignments in Verilog.

2. To implement simple behavioral models using both blocking and nonblocking
assignments.
3. To analyze the behavior of these models under different input conditions.

Procedure:

1. Designing a Simple Model using Blocking Assignment

a. Design a simple sequential circuit (e.g. a D flip-flop) using blocking
assignments.
b. Write the Verilog code for the circuit, including the input, output, and internal
state variables.
c. Simulate the circuit and observe its behavior under different input conditions.
Record the resulting output.
2. Designing a Simple Model using Nonblocking Assignment
a. Modify your D flip-flop code using nonblocking assignments.
b. Compare the Verilog code with the blocking assignment version.
c. Simulate the circuit and observe its behavior. Record the resulting output.
3. Analyzing the Differences
a. Compare the outputs of the two circuits under the same input conditions.
b. Discuss the differences in behavior due to the use of blocking and nonblocking
assignments.
c. Explain how the execution order affects the timing of state updates.
4. Designing a More Complex Model
a. Write the following code using both blocking and nonblocking assignments and
observe the differences in simulation.
b. Simulate both versions of the code and observe the timing of signals a and b.
c. Record the difference between how blocking and nonblocking assignments
handle data propagation and update.
d. Answer the following questions:
i. What is the main difference in simulation output between blocking and
nonblocking assignments?
ii. In what situations would you prefer one over the other?
1. Designing a Simple Model using Blocking Assignment

A. Design a simple sequential circuit (e.g. a D flip-flop) using blocking

assignments.
B. Write the Verilog code for the circuit, including the input, output, and internal state
variables.
 C. Simulate the circuit and observe its behavior under different
input conditions. Record the resulting output.

The Verilog code models a D flip-flop circuit that captures the input value of D on the falling edge of
the clock signal, with a reset feature that sets the output Q to 0. In my testbench, named TBblocking,
I initialize the clock, reset, and D signals. I start by activating the reset signal for 50 time units to
ensure Q is cleared to 0, then deactivate it to resume normal operation. Subsequently, I apply
different values to D: setting it to 1 for 100 time units, switching it to 0 for another 100 time units,
changing it back to 1 for 95 time units, and finally setting it to 0 again. The clock is toggled every 10
time units to maintain a regular clock cycle. Throughout the simulation, I use the $monitor function
to display the values of clk, reset, D, and Q, providing real-time insights into the flip-flop's behavior.
Running this simulation in a Verilog environment allows me to verify the flip-flop's response to
various input scenarios and validate its functionality.

2. Designing a Simple Model using Nonblocking Assignment

A. Modify your D flip-flop code using nonblocking assignments.

B. Compare the Verilog code with the blocking assignment version.
In my revised D flip-flop code, I implemented nonblocking assignments to ensure correct sequential
operation. In this version, when the reset signal is activated, the output Q is set to 0. On the falling
edge of the clock, Q captures the input D's value using nonblocking assignments (<=). This method
supports concurrent execution, which is essential in sequential logic, as it avoids race conditions
that can occur with blocking assignments (=), where instructions are executed one after another,
potentially causing unintended behavior if multiple updates happen in the same block. By using
nonblocking assignments, I ensure that all updates occur simultaneously at the clock edge,
preserving the flip-flop's proper functionality. This approach also improves readability and
debugging because it closely resembles the actual hardware behavior, capturing all inputs at the
clock edge without side effects from previous instructions. While both blocking and nonblocking
assignments can be used in Verilog, I prefer nonblocking assignments for modeling flip-flops
because of their consistency and precise timing in updating signals.

C. Simulate the circuit and observe its behavior. Record the resulting output.

As you can see, Q updates on the falling edge of the clock and takes on the value of D.

3. Analyzing the Differences

A. Compare the outputs of the two circuits under the same input conditions.

The outputs of the two circuits are the same under the same input conditions because
even when they behave differently due to the nature of their assignments, there are no
dependencies between signals. The lack of dependencies between the signals in the
circuits resulted in both circuits having different executions but coming up with the
same output.

B. Discuss the differences in behavior due to the use of blocking and nonblocking
assignments.

When using blocking assignments, the assignment of variables occurs immediately

after the evaluation of the code, and each line of code is executed one after another. For
example:
x = a+b;
y = 2a;

After evaluating a+b, the result is immediately assigned to x, and only then can we
proceed with evaluating 2*a and assign the result to y. Meanwhile, when using non-
blocking assignments, the assignment does not occur immediately after evaluation
but at the end of the current time step, allowing evaluations to be done concurrently.
In this example, a + b and 2 * a would be evaluated simultaneously, and the
assignment of the respective results would occur at the end of the current time step
 C. Explain how the execution order affects the timing of state updates.
Blocking Assignments: Blocking assignments execute in order of appearance in the code.
When there are multiple assignments in a single always block, the state of the signals in that
block would change before all assignments would be evaluated. This leads to unintended
feedback where a value of a signal immediately affects the following assignments within the
same block. For example, if a is assigned to b and then b is used for another assignment within
the same block, b will reflect the value of a at that exact moment, potentially leading to a race
condition.
Non-Blocking Assignments: Non-blocking assignments evaluate all the assignments first
before assigning them all to their respective signal at the end of the time step. This process
prevents earlier assignments from affecting the following assignments within the same block at
the same clock cycle making the timing of state updates more predictable. For example, if a and
b are both set based on inputs in a clocked process, b will reflect the previous value of a before
the clock edge, which is typically the desired behavior in sequential circuits.

4. Designing a More Complex Model

A. Write the following code using both blocking and nonblocking assignments and
observe the differences in simulation.
 B. Simulate both versions of the code and observe the timing of signals a and b.

C. Record the difference between how blocking and nonblocking assignments

handle data propagation and update.
Blocking assignments process statements sequentially, meaning each assignment
must complete before the next one can begin, which can lead to potential timing
issues. In contrast, nonblocking assignments allow all statements to be evaluated
concurrently, with updates occurring at the end of the time step, ensuring a more
reliable propagation of data.

D. Answer the following questions:

i. What is the main difference in simulation output between blocking and nonblocking
assignments?

The difference between the simulation output between blocking and nonblocking
assignment, is that blocking assignments immediately update their outputs
sequentially which lead to unintended results especially in this case where
dependent variables are involved. Meanwhile, non-blocking assignments update
their outputs at the end of the time step. It allowed all updates to be processed in a
single cycle, making the output more predictable.

ii. In what situations would you prefer one over the other?

I would prefer blocking assignments for combinational logic since it needs immediate
results without concerning time. It is preferable in situations where the next
computations depend on the immediate result of the current computation.
Non-blocking assignment on the other hand would be preferred in sequential logic,
where calculations within a clock cycle must be completed before any outputs change.
Non-blocking assignments help prevent race conditions in these situations making the
design more intuitive.
Conclusions:

In this lab activity, we examined the differences between blocking and non-blocking assignments in
Verilog's behavioral modeling. We created a behavioral model of a D flip-flop using both assignment
types and observed how they affected the output. The results demonstrated that blocking
assignments update variables immediately after being evaluated, whereas non-blocking assignments
evaluate all the code within the block first and then update the variables simultaneously at the end of
the time step.