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AND OR NOT NOR: Buffer

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29 views5 pages

AND OR NOT NOR: Buffer

Uploaded by

bhobbs
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1 1 1 1 1 1

000000
AND OR BUFFER NOT NAND NOR
1 1 1 000
Truth Table
Input A Input B Output
DIRECTIONS
Materials:
*9 - 1's
*9 - 0's
*Logic gate cards: and, nand, or, nor, buffer, not (2 each: 1 w word & 1 w icon)
*Truth table game board (laminated or in plastic sleeve protector)
*Envelopes with materials list on front

Getting Started:
1. Separate cards into two piles: Boolean cards and Logic gate cards
2. Place logic gate cards face down on the game board
3. Shuffle and deal boolean cards to each player until gone.
4. Assign each player an input...either Input A and Input B

How to Play:
1. Each player places one boolean card face up on the board in their input spot (input A
or input B).
2. Input A player flips over a logic gate card from the logic gate pile.
3. Players analyze the inputs and logic gates, then quickly place a card in the output
spot.
4. The irst player to place the CORRECT boolean card in the output space gets all the
boolean cards.
5. Players who places the INCORRECT boolean card in the output space also lose one
card from their hand.
6. Winner is the person with the most cards boolean cards at the end of the game

@Lisa Wenzel please share and credit to author


Answer Key: Go over together in class

AND Gate NAND Gate


Input A Input B Output Input A Input B Output

1 1 1 1
1 0 1 0
0 1 0 1
0 0 0 0

OR Gate NOR Gate


Input A Input B Input A Input B Output

1 1 1 1
1 0 1 0
0 1 0 1
0 0 0 0

NOTE: These are your NOTES for the upcoming assessment.


Add an Logic Gate ICON next to each of the headings above.
Fill in the truth tables

PUT THIS IS YOUR BINDER.

Can you explain each of these terms? boolean, binary, logic gates, truth tables
Answer Key: Teacher Copy

AND Gate NAND Gate


Input A Input B Output Input A Input B Output

1 1 1 1 1 0
1 0 0 1 0 1
0 1 0 0 1 1
0 0 0 0 0 1
OR Gate NOR Gate
Input A Input B Input A Input B Output

1 1 1 1 1 0
1 0 1 1 0 0
0 1 1 0 1 0
0 0 0 0 0 1

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