Unit 1: Introduction

Computer Architecture is a functional description of requirements and design implementation for

the various parts of a computer. It deals with the functional behaviour of computer systems. It comes

before the computer organization while designing a computer.

On the other hand, computer organization refers to the operational units and their interconnections

that implement the architecture specification. It deals with how the components of a computer system are

arranged and how they interact to perform the required operations.

Difference between Computer Architecture and Computer Organization

S.
No. Computer Architecture Computer Organization

1. Architecture describes what the computer does. The Organization describes how it does it.

Computer Architecture deals with the functional Computer Organization deals with a
2. behaviour of computer systems. structural relationship.

Whereas Organization indicates its

Architecture indicates its hardware.
3. performance.

As a programmer, you can view architecture as a

The implementation of the architecture is
series of instruction sets, addressing modes, and
called organization.
4. registers.

For designing a computer, its architecture is For designing a computer, an organization

5. fixed first. is decided after its architecture.

Computer Architecture is also called Instruction Computer Organization is frequently called

6. Set Architecture (ISA). microarchitecture.
Functional Units of Digital Systems and their Interconnection:
Functional units of a computer system are parts of the CPU (Central Processing Unit) that performs the
operations and calculations called for by the computer program. A computer consists of five main
components namely, Input/Output unit, Central Processing Unit, Memory unit, Arithmetic & logical unit,
and Control unit.

functional units of digital systems and their interconnections.

Input unit:
o Input units are used by the computer to read the data. The most commonly used input devices are
keyboards, mouse, joysticks, trackballs, microphones, etc.
o However, the most well-known input device is a keyboard.

Output Unit:
o The primary function of the output unit is to send the processed results to the user. Output devices
display information in a way that the user can understand.
o The most common example of an output device is a monitor.

Central processing unit:

o Central processing unit commonly known as CPU can be referred as an electronic circuitry within a
computer that carries out the instructions given by a computer program by performing the basic
arithmetic, logical, control and input/output (I/O) operations specified by the instructions.

Memory unit:
o The Memory unit can be referred to as the storage area in which programs are kept which are running,
and that contains data needed by the running programs.
o The Memory unit can be categorized in two ways namely, primary memory and secondary memory.
 o It enables a processor to access running execution applications and services that are temporarily stored
in a specific memory location.
o The most common examples of primary memory are RAM (Dynamic RAM, Static RAM) and ROM.
o The most common examples of secondary memory are magnetic disks, magnetic tapes, and optical
disks.

Arithmetic & logical unit:

o Most of all the arithmetic and logical operations of a computer are executed in the ALU (Arithmetic
and Logical Unit) of the processor. It performs arithmetic operations like addition, subtraction,
multiplication, division and also the logical operations like AND, OR, NOT operations.

Control unit:
o The control unit is a component of a computer's central processing unit that coordinates the operation
of the processor. It tells the computer's memory, arithmetic/logic unit and input and output devices
how to respond to a program's instructions.
o The control unit is also known as the nerve centre of a computer system.

Note:
Block diagram of the computer's CPU showing all the basic building blocks such as
program counter, accumulator, address and data registers, instruction register, control unit etc.; and
describe how such an arrangement can work as a computer, if connected properly to memory,
input/output etc.

Block Diagram of Computer’s CPU

Program Counter: A program counter is a register in a computer processor that contains the address
(location) of the instruction being executed at the current time. As each instruction is fetched, the program
counter increases its stored value by 1.
Memory Address Register (MAR): This register holds the address of memory where CPU wants to read or
write data. When the CPU wants to store some data in the memory or reads the data from the memory, it
places the address of the required memory location in the MAR.
Accumulator: The accumulator is a register in which intermediate arithmetic and logical results are stored.
Instruction Register: Once an instruction is fetched from main memory, it is stored in the Instruction
Register. The control unit takes instruction from this register, decodes and executes it by sending signals to
the appropriate component of the computer to carry out the task.
Control Unit: It decodes the instructions, and controls all the other internal components of the CPU to make
it work.
Bus, Bus Architecture, Types of Buses
Bus: A bus is a communication pathway connecting two or more devices. A key characteristic of a bus is
that it is a shared transmission system. Multiple devices connected to the bus and a signal transmitted by one
device is available for reception by all other devices, attached to the bus.

Bus Architecture

• System Bus: A bus that connects major computer components: processor, memory and I/O devices.
• The number of lines in a data bus affects the speed of data transfer between different components.
• Many components are connected to one another through buses.
• Each component is assigned a unique ID.
• This ID is called the address of that component.
• If a component wants to communicate with another component, it uses an address bus to specify the
address of that component.

Types of Buses:
1. Data Bus: Data lines provide a path for moving data between system modules/units, these lines are
collectively called as Data Bus. These data lines are bidirectional.

2. Address Bus: They are used to designate the source/destination of the data on the data bus. Address
lines are unidirectional.

3. Control Bus: Control lines are used to control the access and the use of data in address lines, example:
Memory-Read, Memory-Write.
Typical Control lines include:
Bus Arbitration
Introduction:
In a computer system, multiple devices, such as the CPU, memory, and I/O controllers, are connected to a
common communication pathway, known as a bus. In order to transfer data between these devices, they
need to have access to the bus.
Bus arbitration is the process of resolving conflicts that arise when multiple devices attempt to access the
bus at the same time.
When multiple devices try to use the bus simultaneously, it can lead to data corruption and system
instability. To prevent this, a bus arbitration mechanism is used to ensure that only one device has access to
the bus at any given time.
There are several types of bus arbitration methods, including centralized, decentralized, and
distributed arbitration.
In centralized arbitration, a single device, known as the bus controller, is responsible for managing access to
the bus.
In decentralized arbitration, each device has its own priority level, and the device with the highest priority is
given access to the bus.
In distributed arbitration, devices compete for access to the bus by sending a request signal and waiting for a
grant signal.
The controller that has access to a bus at an instance is known as a Bus master.
The selection of the bus master must take into account the needs of various devices by establishing a priority
system for gaining access to the bus. The Bus Arbiter decides who would become the current bus master.

Applications of bus arbitration in computer organization:

Shared Memory Systems: In shared memory systems, multiple devices need to access the memory to read
or write data. Bus arbitration allows multiple devices to access the memory without interfering with each
other.
Multi-Processor Systems: In multi-processor systems, multiple processors need to communicate with each
other to share data and coordinate processing. Bus arbitration allows multiple processors to share access to
the bus to communicate with each other and with shared memory.
Input/Output Devices: Input/Output devices such as keyboards, mice, and printers need to communicate
with the processor to exchange data. Bus arbitration allows multiple input/output devices to share access to
the bus to communicate with the processor and memory.
Real-time Systems: In real-time systems, data needs to be transferred between devices and memory within
a specific time frame to ensure timely processing. Bus arbitration can help to ensure that data transfer occurs
within a specific time frame by managing access to the bus.
Embedded Systems: In embedded systems, multiple devices such as sensors, actuators, and controllers
need to communicate with the processor to control and monitor the system. Bus arbitration allows multiple
devices to share access to the bus to communicate with the processor and memory.
Methods of Centralized BUS Arbitration:
There are three bus arbitration methods:
(i) Daisy Chaining method: It is a simple and cheaper method where all the bus masters use the same line
for making bus requests. The bus grant signal serially propagates through each master until it encounters the
first one that is requesting access to the bus. This master blocks the propagation of the bus grant signal;
therefore, any other requesting module will not receive the grant signal and hence cannot access the bus.
During any bus cycle, the bus master may be any device – the processor or any DMA controller unit,
connected to the bus.

Advantages:
• Simplicity and Scalability.
• The user can add more devices anywhere along the chain, up to a certain maximum value.
Disadvantages:
• The value of priority assigned to a device depends on the position of the master bus.
• Propagation delay arises in this method.
• If one device fails then the entire system will stop working.

(ii) Polling or Rotating Priority method: In this, the controller is used to generate the address for the
master (unique priority), the number of address lines required depends on the number of masters connected
in the system. The controller generates a sequence of master addresses. When the requesting master
recognizes its address, it activates the busy line and begins to use the bus.
Advantages –
• This method does not favor any particular device and processor.
• The method is also quite simple.

Disadvantages –
• Adding bus masters is difficult as increases the number of address lines of the circuit.
• If one device fails then the entire system will not stop working.
(iii) Fixed priority or Independent Request method –
In this, each master has a separate pair of bus request and bus grant lines and each pair has a priority
assigned to it.
The built-in priority decoder within the controller selects the highest priority request and asserts the
corresponding bus grant signal.

Advantages –
• This method generates a fast response.
Disadvantages –
• Hardware cost is high as a large no. of control lines is required.
Register, bus and Memory Transfer
A digital computer system exhibits an interconnection of digital modules such as registers, decoders,

arithmetic elements, and Control logic.

These digital modules are interconnected with some common data and control paths to form a complete

digital system.

Moreover, digital modules are best defined by the registers and the operations that are performed on the data

stored in them.

The operations performed on the data stored in registers are called Micro-operations.

The internal hardware organization of a digital system is best defined by specifying:

o The set of registers and the flow of data between them.

o The sequence of micro-operations performed on the data which are stored in the registers.

o The control paths that initiate the sequence of micro-operation

The Register Transfer Language is the symbolic representation of notations used to specify the sequence

of micro-operations.

In a computer system, data transfer takes place between processor registers and memory and between

processor registers and input-output systems. These data transfer can be represented by standard notations

given below:

o Notations R0, R1, R2..., and so on represent processor registers.

o The addresses of memory locations are represented by names such as LOC, PLACE, MEM, etc.

o Input-output registers are represented by names such as DATA IN, DATA OUT and so on.

o The content of register or memory location is denoted by placing square brackets around the name of

the register or memory location.

1. Register Transfer
The term Register Transfer refers to the availability of hardware logic circuits that can perform a given

micro-operation and transfer the result of the operation to the same or another register.

Most of the standard notations used for specifying operations on various registers are stated below.

o The memory address register is designated by MAR.

o Program Counter PC holds the next instruction's address.

o Instruction Register IR holds the instruction being executed.

o R1 (Processor Register).

o MBR/MDR: Memory Buffer/Data Register

 o Data Transfer from one register to another register is represented in symbolic form by means of

replacement operator. For instance, the following statement denotes a transfer of the data of register

R1 into register R2.

R2 ← R1

o Typically, most of the users want the transfer to occur only in a predetermined control condition.

This can be shown by following if-then statement:

If (P=1) then (R2 ← R1); Here P is a control signal generated in the control section.

o It is more convenient to specify a control function (P) by separating the control variables from the

register transfer operation. For instance, The following statement defines the data transfer operation

under a specific control function (P).

P: R2 ← R1

The following image shows the block diagram that depicts the transfer of data from R1 to R2.

Here, the letter 'n' indicates the number of bits for the register.
2. Bus Transfers
A digital system composed of many registers, and paths must be provided to transfer information from one

register to another. The number of wires connecting all of the registers will be excessive if separate lines are

used between each register and all other registers in the system.

A bus structure, on the other hand, is more efficient for transferring information between registers in a multi-

register configuration system.

A bus consists of a set of common lines, one for each bit of register, through which binary information is

transferred one at a time. Control signals determine which register is selected by the bus during a particular

register transfer.
The following block diagram shows a Bus system for four registers. It is constructed with the help of

four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection inputs (S1 and S2).

For instance, output 1 of register A is connected to input 0 of MUX1.

The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers. The

selection lines choose the four bits of one register and transfer them into the four-line common bus.

When both of the select lines are at low logic, i.e., S1S0 = 00, the 0 data inputs of all four multiplexers are

selected and applied to the outputs that forms the bus. This, in turn, causes the bus lines to receive the

content of register A since the outputs of this register are connected to the 0 data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content provided by

register B.

The following function table shows the register that is selected by the bus for each of the four possible

binary values of the Selection lines.

Note: The number of multiplexers needed to construct the bus is equal to the number of bits in each register.

The size of each multiplexer must be 'k * 1' since it multiplexes 'k' data lines. For instance, a common bus

for eight registers of 16 bits each requires 16 multiplexers, one for each line in the bus. Each multiplexer

must have eight data input lines and three selection lines to multiplex one significant bit in the eight

registers.
A bus system can also be constructed using three-state gates instead of multiplexers.

The three state gates can be considered as a digital circuit that has three gates, two of which are signals

equivalent to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a high-impedance

state.

The most commonly used three state gates in case of the bus system is a buffer gate.

The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state buffers.
 o The outputs generated by the four buffers are connected to form a single bus line.

o Only one buffer can be in active state at a given point of time.

o The control inputs to the buffers determine which of the four normal inputs will communicate with

the bus line.

o A 2 * 4 decoder ensures that no more than one control input is active at any given point of time.

3. Memory Transfer
Most of the standard notations used for specifying operations on memory transfer are stated below.

o The transfer of information from a memory unit to the user end is called a Read operation.

o The transfer of new information to be stored in the memory is called a Write operation.

o A memory word is designated by the letter M.

o We must specify the address of memory word while writing the memory transfer operations.

o The address register is designated by AR and the data register by DR.

Read operation can be stated as:

Read: DR ← M [AR]

o The Read statement causes a transfer of information into the data register (DR) from the memory

word (M) selected by the address register (AR).

Write operation can be stated as:

Write: M [AR] ← R1

o The Write statement causes a transfer of information from register R1 into the memory word (M)

selected by address register (AR).

Processor Organization, General Register Organization:
General Purpose Register Based Organization:
In this type of organization, computers use two or three address fields in their instruction format. Each
address field may specify a general register or a memory word. Large number of registers are included in the
CPU. It is most efficient to collect them through a common bus system, not only for direct data transfer but
also while performing various micro-operations. Hence, it is necessary to provide a common unit that can
perform all the arithmetic logic and shift micro-operations in the processor.

Stack Organization:
Stack: It is a useful feature that is included in the CPU which follows the LIFO principle (Last In First Out).
It is a storage device that stores info in such a manner that the item stored last is the first item retrieved.
Register Stack: A stack register is a computer central processor register whose purpose is to keep track of a
call stack. It can be placed in a portion of a large memory or it can be organized as a collection of a finite
number of memory words or registers.

Stack Pointer: It is the register that holds the address for the stack, because it’s value always points at the
top of stack.
Operations of Stack:
1. Push: Operation of insertion in stack and increase the value of stack pointer by

2. Pop: Operation of deletion in stack and it decreases the value of stack pointer by1.
Memory Stack:
A stack can be implemented in a RAM attached to a CPU, the implementation of stack is done by assigning
a portion of memory to a stack operation, and using a processor register as a stack pointer.
Memory stacks are linear data structures (locations) used to store data in a computer's memory. Usually, the
stack is used for storing data when subroutines are called.
Subroutine: A subroutine is a reusable program module. A main program can call or jump to the subroutine
one or more times.

Return address of a subroutine is stored in stack memory. As the last Subroutine called is the first one to be
returned (Last in first out format). So, stack data structure is the most efficient way to store the return
addresses of the Subroutines.
Addressing Modes:
1. Direct: In this mode, effective address is equal to the address part of the instruction. Load R1, 1000 is
interpreted as R1 ← [1000]
2. Register Indirect: The address field of the instruction refers to a CPU register that contains the
effective address of the operand. Only one reference to memory is required to fetch the operand.AC ← AC +
[[R]]
3. Implied: In this mode, the operand is specified in the instruction itself. Complement Accumulator
4. Immediate: In this mode, operands are in the registers that reside within the CPU.ADD 10(will
increment the value stored in the accumulator by 10.)
5. Indexed: In this mode, the content of the address register is added to the address part of instruction to
obtain the effective address. It is a special register that contains an index value. And the effective address is
denoted by EA = X + (R)
6. Register Direct Addressing: The instruction which uses processor registers to represent operands is the
instruction in register addressing mode. EA=R.ADD R4, R3
7. Relative Addressing Mode: It is used to load a register with a value stored in program memory a short
distance away from the current instruction.

Auto Increment addressing modes:

1. This is similar to Register Indirect mode, except that register is incremented after its value is used to
access memory.
2. After operand addressing, the contents of the register are incremented.
3. Symbolically it is represented as below: (R)+
4. example: ADD (R2) +, R0
Auto Decrement addressing modes:
1. In this mode, first the value is decremented and then operand value is fetched from the memory.
2. Before operand addressing, the contents of the register are decremented.
3. Symbolically it is presented as -(R)
4. example: ADD -(R2), R0