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Microprocessors - CH 3

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Microprocessors - CH 3

Uploaded by

Mohammed Nafie
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapt er TH REE

Arit hmetic
and Logic
In st ructio ns

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2 . 5: DATA TYPES AND DATA DEFINITION

• Figure 2-7 shows the memory dump of the data


section.
– It is essential to understand the way operands are stored
in memory.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
OBJE CT IVES
this chapter enables the student to:

• Demonstrate how 8-bit and 16-bit unsigned


numbers are added in the x86.
• Convert data to any of the forms:
– ASCII,packed BCD,unpacked BCD.
• Explain the effect of unsigned arithmetic
instructions on the flags.
• Code the following Assembly language unsigned
arithmetic instructions:
– Addition instructions: ADD and ADC.
– Subtraction instructions SUB and SBB.
– Multiplication and division instructions MUL and DIV.
The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
3 . 1: U NSIGNED ADDITION AND SUB TR AC TI O N
addi ti on of unsigned numbers
• The form of the ADD instruction is:

• ADD and ADC are used to add two operands.


– The destination operand can be a register or in memory.
– The source operand can be a register, in memory, or
immediate.
• Memory-to-memory operations are never allowed
in x86 Assembly language.
– The instruction could change ZF, SF, AF, CF, or PF bits of
the flag register.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
3 . 1: U NSIGNED ADDITION AND SUB TR AC TI O N
addi ti on of unsigned numbers

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
3 . 2: U NSIGNED MULTIPLICATION & D IV IS I ON
mult ip lication of unsigned num be rs
• In multiplying two numbers in the x86 processor,
use of registers AX, AL, AH, and DX is necessary.
– The function assumes the use of those registers.
• Three multiplication cases:
– byte times byte; word times word; byte times word.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
3 . 2: U NSIGNED MULTIPLICATION & D IV IS I ON
divi si on of unsigned numbers
• byte/byte - the numerator must be in the AL
register and AH must be set to zero.
– The denominator cannot be immediate but can be in a
register or memory, supported by the addressing modes.
• After the DIV instruction is performed, the quotient is in AL
and the remainder is in AH.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
OBJE CT IVES ( cont )
this chapter enables the student to:

• Code BCD arithmetic instructions:


– DAA and DAS.
• Code the Assembly language logic instructions:
– AND, OR, and XOR.
– Logical shift instructions SHR and SHL.
– The compare instruction CMP.
• Code bitwise rotation instructions
– ROR, ROL, RCR, and RCL.
• Demonstrate an ability to use all of the above
instructions in Assembly language programs.
• Perform bitwise manipulation using the C language.
The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
3 . 3: L OGIC INSTRUCTIONS
SHIF T RIGHT
• SHR - logical shift right.
– Operand is shifted right bit by bit.
• For every shift the LSB (least significant bit)
will go to the carry flag. (CF)
• The MSB (most significant bit) is filled with 0.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
3 . 3: L OGIC INSTRUCTIONS
SHIF T LEFT
• SHL - Logical shift left, the reverse of SHR.
– After every shift, the LSB is filled with 0.
• MSB goes to CF.
– All rules are the same as for SHR.

3-11 can also


be coded as:

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
3 . 3: L OGIC INSTRUCTIONS
COMP AR E of unsigned numbers
• C M P destination,source
– Compares two operands & changes flags according to the
result of the comparison, leaving the operand unchanged.
• Destination operand can be in a register or in memory.
• Source operand can be in a register, in memory, or immediate.
• CF, AF, SF, PF, ZF, and OF flags reflect the result.
– Only CF and ZF are used.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
3 . 5: R OTATE INSTRUCTIONS

– If the operand is to be rotated once, the 1 is coded.


• If it is to be rotated more than once, register CL is used
to hold the number of times it is to be rotated.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458

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