C 0800ECT203122004 Pages: 2

Reg No.:_______________ Name:__________________________

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
Third Semester B.Tech Degree Examination December 2020 (2019 Scheme)

Course Code: ECT203

Course Name: LOGIC CIRCUIT DESIGN
Max. Marks: 100 Duration: 3 Hours

PART A
Answer all questions. Each question carries 3 marks Marks
1 Convert (3A9E.B)16 to binary and decimal. (3)
2 Convert (25)10 to binary, gray and BCD. (3)
__
3 Express the boolean function F(A, B, C)  A  B C as sum of minterms. (3)

4 Write Verilog Code for a NAND gate. (3)

5 Implement a 4-input binary decoder using basic gates. (3)
6 Explain the working of a 4-bit parallel adder. (3)
7 Obtain the excitation table and characteristic equation of a T flip-flop. (3)
8 Convert a JK flip-flop to D flip-flop. (3)
9 Distinguish between fan-in and fan-out. (3)
10 Explain noise margin. (3)

PART B
Answer any one full question from each module. Each question carries 14 marks
Module 1
11 (a) Subtract 27 from 75 using 2’s and 1's complement arithmetic (8)
(6)
(b) Explain fixed and floating point representation of numbers
12 (a) What is Hamming code? How is the Hamming codeword generated? Encode (8)
the data bits 1011 into 7-bit even Hamming code.
(6)
(b) Give a brief description of identifiers and keywords in Verilog
Module 2
13 (a) Implement an EX-OR gate using universal gates (6)
(b) Simplify the Boolean expression F(A,B,C,D) =∑m(1,3,10)+d(0,2,8,12)
using K-Map and implement the simplified expression using universal gates. (8)

Page 1 of 2
 0800ECT203122004

14 (a) Reduce the Boolean expression F=∏M(1,2,3,4,10,11,15) using K-Map (7)

(b) Write Verilog code for implementing the above function
(7)
Module 3
15 (a) Design a BCD adder circuit. (8)
(b) Write Verilog code for full subtractor circuit.
(6)
16 (a) Design a 3-bit magnitude comparator. (8)
(b) Implement the logic function F(A,B,C,D)=∑m(1,3,4,11,12,13,14,15) using (6)
8 : 1 MUX
Module 4
17 (a) Explain the operation of a 4-bit Johnson counter with truth table and (7)
waveforms.
(7)
(b) Design a mod-10 asynchronous counter using T flip-flop.
18 Design a mod -16 synchronous counter using JK flip-flop. (14)
Module 5
19 (a) Explain the working of a transistor level TTL NAND gate. (8)
(b) Draw and explain the working of a transistor level CMOS inverter.
(6)
20 (a) Explain the working of a transistor level CMOS NOR gate. (8)
(b) Compare TTL & CMOS logic families in terms of fan-in, fan-out, supply
(6)
voltage, power supply and propagation delay and power dissipation.
***

Page 2 of 2
C 0800ECT203122005 Pages: 2

Reg No.:_______________ Name:__________________________

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
Third Semester B.Tech Degree Examination December 2021 (2019 scheme)

Course Code: ECT203

Course Name: LOGIC CIRCUIT DESIGN
Max. Marks: 100 Duration: 3 Hours
PART A
Answer all questions. Each question carries 3 marks Marks
1 Convert (231.45)8 to equivalent decimal and binary (3)
2 Give a brief description of keywords in Verilog (3)
3 ___________________
_____ ___
(3)
Reduce the expression F  AB  A  AB using De-Morgan's theorem
4 Write a Verilog code for implementing a NOR gate (3)
5 Explain the working of a multiplexer (3)
6 Write a Verilog code for half subtractor (3)
7 Convert a JK flipflop to T flipflop (3)
8 Write a Verilog code for implementing D flipflop (3)
9 Define noise-margin (3)
10 Define propagation delay and power dissipation (3)
PART B
Answer any one full question from each module. Each question carries 14 marks
Module 1
11 (a)Perform the following operations (6)
(i) (A5C)16 +(8E4)16 (ii) (175.6)8 -(47.7)8
(b)What is Hamming code? The message 1100110 is coded in 7-bit even parity (8)
Hamming code which is transmitted through a noisy channel. Decode the
message assuming that a single error occurred in the codeword
12 (a) Find 11001-10001 using 1's and 2's complement arithmetic (8)
(b)Explain the operators in Verilog (6)
Module 2
13 __ ___
(a) Obtain the canonical POS expression of F(A, B, C)  (A  B)(B  C)(A  C ) (5)
(b) Simply the expression Y=∏M(0,1,4,5,6,8,9,12,13,14) using K-Map and
implement the simplified expression using NOR logic. (9)

Page 1 of 2
 0800ECT203122005

14     (14)
For the logical expression F  A  AB  AB D A B D C
(i) Obtain Canonical SOP expression
(ii)Simplify the expression using K-Map
(iii)Write Verilog code for the simplified expression
Module 3
15 (a)Design a full adder circuit (8)
(b) Write a Verilog code for 1:4 demultiplexer (6)
16 (a)Implement the logic function f(A,B,C)=∑m(0,2,3,5) using (8)
(i) 8:1 MUX (ii) 4:1 MUX
(b)Design a octal to binary encoder (6)
Module 4
17 (a)Explain the operation of a JK flip-flop using NAND gates (6)
(b)Explain the operation of a 4-bit Johnson counter with
truth table and waveforms (8)
18 (a)Design a mod-6 synchronous up-counter using JK flip-flop (7)
_______
(b)Explain a PISO shift register using LOAD /SHIFT (7)
Module 5
19 (a)Compare TTL & CMOS logic families in terms of fan-in, fan-out, supply (5)
voltage, propagation delay and noise margin
(b)Draw the circuit and explain the operation of transistor level TTL NAND (9)
gate
20 (a)Draw the circuit diagram of a transistor level TTL Inverter and explain the (5)
working
(b)Draw the circuit and explain the operation of transistor level CMOS NAND (9)
gate
*****

Page 2 of 2
 C 0800ECT203122101 Pages: 2

Reg No.:_______________ Name:__________________________

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
Third Semester B.Tech Degree Regular and Supplementary Examination December 2022 (2019 Scheme)

Course Code: ECT203

Course Name: LOGIC CIRCUIT DESIGN
Max. Marks: 100 Duration: 3 Hours

PART A
Answer all questions. Each question carries 3 marks Marks

1 Convert the decimal number 215 to following codes (3)

(i)BCD code (ii)Excess 3 code (iii) Gray code
2 Convert the decimal number 18.6875 into binary and hexadecimal. (3)
3 Write Verilog Code for a XOR gate (3)
4 Express f(A,B,C) = AB + AC' + BC in standard SOP form. (3)
5 Design a 1-bit comparator circuit using logic gates. (3)
6 Realize an 8:1 multiplexer using 4:1 multiplexers and gates. (3)
7 Convert a JK flip-flop to D flip-flop. (3)
8 Realize D latch using gates and write the Verilog code. (3)
9 Define the following in terms of Logical families i) Propagation delay ii) fan out
(3)
iii) Noise margin
10 Draw the circuit diagram of a CMOS- NOT gate and explain the working with
(3)
truth table.
PART B

Answer any one full question from each module. Each question carries 14 marks
Module 1
11 a) Find the sum of two hexadecimal numbers (85C) 16 and (23C6) 16 (2)
b) Covert each decimal number to binary and perform the subtraction
21.510 --13.2510 using (i)1’s complement method(ii)2’s complement (4)
method
c) Explain the main differences between the Verilog terms
(i)Wire and Reg
(ii)Task and Function (8)

ns

Page 1of 2
 0800ECT203122101

12 a) How is the Hamming code word generated? The message “1001001” is (8)
coded in 7-bit even parity Hamming code, which is transmitted through
a noisy channel. Decode the message, assuming that at most a single
error occurred in each code word.
b) Explain Verilog operators with examples. (6)

Module 2
13 a) Simplify the Boolean expression F (A, B, C, D) =∑m (0, 1, 2, 6, 8, 9, 10, (8)
11) + d (3, 7, 14, 15) using K-Map and implement the simplified
expression using universal gates.
b) Prove the following Boolean rules
i. A+AB=A (6)
ii. A+A′B=A+B
14 a) Reduce the following function using Karnaugh map technique (8)
f (A, B, C, D) = πM (0, 2, 4, 10, 11, 14, 15) and implement the
simplified expression using NAND gates.
b) Explain the significance of duality principle in Boolean algebra (6)
Module 3
15 a) Implement the following functions using MUX (9)
(i)AND
(ii)XOR (5)
iii) f (A, B, C) = ∑ m (0, 3, 5, 6)
b) Write a verilog code to implement 4:1 multiplexer.
16 a) Implement a Full adder circuit using (9)
(i) 3: 8 decoder (ii) 1:8 demultiplexer (5)
b) Write a Verilog description for a one-bit full adder circuit
Module 4
17 a) Design a 3-bit synchronous up counter using T flip-flop. (9)
b) Explain the operation of a 4-bit Ring counter. (5)

18 a) Design a divide by 2N circuit using N number of flip-flops. Draw the (7)

truth table and waveforms.
b) What is a race around condition related to JK Flip Flop? Explain how to (7)
eliminate the problem.
Module 5
19 a) Describe the working of a 2-bit TTL NAND gate with Totem pole (8)
configuration.
b) Explain the working of a transistor level CMOS NOR gate. (6)
20 a) Describe the working of a tristate TTL inverter (8)
b) Explain the working of a transistor level CMOS NAND gate. (6)

*****

Page 2of 2
C 08000ECT203122201 Pages: 2

Reg No.:_______________ Name:__________________________

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
B.Tech Degree S3 (R, S) / S1 (PT) (S, FE) Examination December 2023 (2019 Scheme)

Course Code: ECT203

Course Name: LOGIC CIRCUIT DESIGN
Max. Marks: 100 Duration: 3 Hours

PART A
Answer all questions. Each question carries 3 marks Marks
1 Convert (202.625)10 to binary. (3)
2 With an example explain Binary Coded Decimals. (3)
3 State De Morgan’s theorem (3)
4 Simplify the following Boolean expression, F = ABC + A’B + ABC’, to a (3)
minimum number of literals using algebraic methods alone.
5 Design a 2-bit decoder (3)
6 Write verilog code for a 1x4 demux. (3)
7 Differentiate between Flip Flop and Latch (3)
8 Implement a T Flip Flop using D Flip Flop (3)
9 With an example explain transition time. (3)
10 Give the names (full form) of 3 logic families. (3)

PART B
Answer any one full question from each module. Each question carries 14 marks
Module 1
11 (a) Represent 543.125 using signed 32-bit floating point representation (8-bit (8)
exponent)
(b) Convert (123B)16 to binary and octal. (6)
12 (a) Compute (232)10 – (325)10 by using 2’s complement method. (9)
(b) Explain the operators in Verilog. (5)
Module 2
13 (a) Minimise the following function into SoP form. (6)
F (w, x, y, z) = Σ m(0,6,8,13,14) + d(2,4,10)
(b) Draw the circuit diagram for the minimised expression.
(3)

Page 1of 2
 08000ECT203122201

(c) Write a Verilog code to implement the same (5)

14 (a) Minimise the following function into PoS form. (6)
F (w, x, y, z) = Π (1, 3, 6, 9, 11, 12, 14)
(b) Draw the circuit diagram for the minimised expression
(3)
(c) Write a Verilog code to implement the same.
(5)
Module 3
15 (a) Implement the boolean function F (A, B, C, D) = Σ (0, 1, 2, 3, 6, 10, 11, 14) (8)
using an 8X1 mux.
(b) Write the verilog code to implement the boolean function F (A, B, C, D) = Σ (6)
(0, 1, 2, 3, 6, 10, 11, 14) using an 8X1 mux.(Code should contain seperate
modules for implementing the mux and the function)
16 (a) Design a Half Adder (3)
(b) Design a Full Adder by taking the Half Adder designed in (a) as the building (4)
block
(7)
(c) Design and implement a BCD Adder.
Module 4
17 (a) Design synchronous 3 bit UP counter using JK Flipflop. (8)
(b) Design and implement 4 bit Johnson counter. (6)
18 (a) Explain the operation of Master Slave JK Flip flop. (7)
(b) Design a mod-10 asynchronous counter. (7)
Module 5
19 (a) Compare TTL & CMOS logic families in terms of logics levels, noise (7)
margin, fan-out, propagation delay, transition time, power consumption and
power-delay product.
(b) List the applications of CMOS and TTL logic families. Justify their use in
(7)
those applications based on the comparison given above.
20 Draw the circuit diagram and explain the working of the following:
(7)
a) CMOS NOR gate
(7)
b) TTL inverter
*****

Page 2of 2