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Unit-4 (VLSI Design Flow)

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87 views4 pages

Unit-4 (VLSI Design Flow)

Vlsi unit 4
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© © All Rights Reserved
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Introduction to VLSI Systems 5

Based on the devices used for implementing the IC, they are classified as follows:
n Bipolar In these ICs, bipolar junction transistors (BJTs) are used to
implement the IC.
n CMOS In the CMOS ICs, combination of nMOS and pMOS transistors are
used to implement the IC.
n BiCMOS In these ICs, combination of BJT and CMOS transistors are used.
n MESFET Metal semiconductor field effect transistors are used in these ICs.
n HBT These ICs use hetero-junction bipolar transistors.
n HEMT High electron mobility transistors are used in these ICs.

1.4 VLSI Design Methodology


VLSI design is a sequential process of generating the physical layout of an IC,
starting from the specification of that circuit. It can be fully or semi-automated
using numerous softwares called electronic design automation (EDA) or computer-
aided design (CAD) tools. The designers first get an idea of a new system or device
for a particular application. This new idea is translated in the form of an integrated
circuit chip using the VLSI design flow.
The concept or idea is first documented in a formal language and then trans-
lated into register transfer level (RTL) using hardware description languages such
as Verilog and VHDL. The RTL netlist is then complied and tested to check if the
functionality expected is correctly described. Usually, an iterative process is used
to describe the circuit behaviour in the RTL netlist. Once the behavioural netlist
is finalized, the constraints are imposed on the design. Some major constraints
are less area, low power, and high speed. Taking the behavioural netlist and de-
sign constraints, different synthesis styles have come up with optimum hardware,
which meet all the constraints and generate correct functional output.
The complexity of the VLSI circuits is usually large. The design complexity is
handled using several approaches. First, the design is viewed at different abstraction
levels and then is decomposed hierarchically. Automated tools are used for synthe-
sis, simulation, design, testing, and verification. If possible, the design is reused.
Typically, an electronic system has two parts: hardware and software. These
can be designed concurrently in a manner so as to save the design cycle time. It
also helps the hardware and software design teams to work in sync to sort out any
incompatibility issues that might arise in the later stages of the design cycle.
There are two design styles used in VLSI design. One is the top–down approach
and another is the bottom–up approach. In the top–down approach, the system is
built starting from the top up to the bottom. While in the bottom–up approach, the
basic building blocks are built first, and they are combined or assembled to build
the entire system. Both approaches have their merits and demerits.

1.5 Design Domains—Y-chart


The IC design can be described in the following three domains:
n Behavioural
n Structural
n Physical

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6 Vlsi design

In the behavioural domain, a circuit is described fully by its behaviour without


describing its physical implementation or structure. In the structural domain, a
circuit is described by its components and their interconnections. The physical
domain deals with actual geometry of the circuit and describes the shape, size, and
locations of its components.
The three design domains are represented pictorially by a chart called the Y-chart
(Fig. 1.4) introduced by Gajski–Kuhn.

Structural Behavioural
Processor Algorithm
register transfer Register transfer language
Gate Boolean expression
transistor Differential equation
Transistor
Cell
Module
Floor plan
Physical
Figure 1.4 Gajski–Kuhn Y-chart

1.6 Hierarchical Abstraction


Hierarchical decomposition or ‘divide and conquer’ is a useful methodology
that partitions the entire system into its components. The components are again
partitioned into modules and this process continues until the basic building blocks
are reached. This methodology is illustrated in Fig. 1.5.

System

Software Hardware

Application OS Module Module Module

Submodule Submodule

Datapath Control

Figure 1.5 Hierarchical decomposition of an electronic system

For example, let us consider a CPU as a system at the top level. It can be partitioned
into two main components: datapath and control logic. Again, the datapath can be

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Introduction to VLSI Systems 7

divided into modules such as ALU, registers, and shift registers. The ALU can be
further divided into basic arithmetic units such as full adders, and so on. This is
illustrated in Fig. 1.6.

CPU

Datapath Control

ALU Registers Shift registers

Full
adder

Figure 1.6 Hierarchical decomposition of CPU

1.6.1 Regularity, Modularity, and Locality


The large complexity of the VLSI design is handled by the hierarchical decom-
position of a system into several functional blocks. While hierarchically decom-
posing, a large system regularity must be followed. Regularity indicates that the
decomposition process must not produce a large number of blocks, and the blocks
need to be similar as much as possible. An array structure normally has a good
regularity. The array multiplier is a perfect example of a regular structure. Regu-
larity avoids a number of different blocks to be designed and verified and can be
maintained at all levels of abstraction.
Modularity is another important aspect of hierarchical decomposition. It means
that the functional blocks must have well-defined interfaces and functionality.
Modular design allows different modules to be designed concurrently and also
enables design reuse.
Hierarchical decomposition must also consider the locality of the functional
blocks. The decomposition should be such that the blocks, exchanging signals
frequently, must be close to each other in order to reduce the interconnect length.
Again, the internal wiring must be local and should not affect other modules.

1.7 VLSI Design Flow


The VLSI design flow is a sequence of steps followed to translate the idea
of a system into a chip. The flow is based on the standard design automation
tools. The basic steps are shown in Fig. 1.7. It starts with system specifications
such as area, speed, and power. Then the functional design is done followed
by functional verification to check if the design is correct. In this phase, the
design is described at the behavioural level. Next, the design is implemented at
the logic level and verified for its correctness. This is followed by the transistor
level or circuit design verification. Up to this step, the flow is known as logical
design. The next phase is the physical design which actually deals with the
geometry of the chip. Once the physical layout is generated, it must be verified
to check if the layout really implements the actual design. The last and final

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8 Vlsi design

System specifications

Functional (architecture) design

Functional verification

Logic design

Logic verification

Circuit design

Circuit verification

Design
Physical design

Physical verification
Evaluation

Fabrication and testing

Figure 1.7 VLSI design flow Figure 1.8 Design iteration loop.

step is the fabrication and testing of the chip. Figure 1.7 illustrates the VLSI
design flow at the top level.
Though a VLSI design flow looks entirely sequential, there are feedback loops
at each stage of the design flow. After each stage, the design is evaluated to see if
the functionality and specifications are met. Otherwise, the designers go back and
redesign, and the process is repeated in an iterative manner till the specifications
are satisfied. The typical design loop is shown in Fig. 1.8.
Generally, top–down is the preferred approach in VLSI design. The bottom–up
approach is infeasible for large systems.

1.8 VLSI Design Styles


Depending on the application, cost of production, performance, and the volume of
production, there are different VLSI design styles that are followed to implement
a chip. Each of the styles has its own advantages and disadvantages and is chosen
on the basis of the target application. The commonly used design styles are as
follows:
n Field programmable gate array (FPGA) design
n Gate array design
n Standard cell-based design
n Full-custom design
n Semi-custom design
n Programmable logic device (PLD)

The following subsections discuss each of the design styles in brief.

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