3828 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 67, NO.

11, NOVEMBER 2020

A Fully Integrated High-Power-Supply-Rejection

Linear Regulator With an Output-Supplied
Voltage Reference
Yan-Peng Chen and Kea-Tiong Tang , Senior Member, IEEE

Abstract— This study proposes an output capacitor-less linear

regulator with high power supply rejection (PSR) for a wireless
power transmission system. To achieve high PSR with a noisy
input voltage, a fully integrated linear regulator with its reference
circuit supplied by the output voltage is proposed. The proposed
technique can isolate the reference circuit from the noisy V I N ,
thereby reducing the requirements of the conventional bulky low-
pass filter loading the reference voltage node while achieving
superior PSR performance. The regulator uses an N-type pass
transistor and a dual-feedback structure to achieve wideband
ripple-filtering and fast transient responses. The proposed regu-
lator is compatible with typical biomedical implants requiring a
10mA load current at 1.1V output voltage while consuming a total
quiescent current of 276µ A. A PSR performance was measured
to be −48 and − 56 dB against the V I N and charge pump
at 10 MHz, respectively. The unity gain bandwidth (UGB) of the Fig. 1. Schematic of the proposed linear regulator.
regulator was 291MHz. The proposed regulator was fabricated
using commercial TSMC 0.18-µm CMOS technology with an
area of 0.1054 mm2 including the reference circuit. To meet the aforementioned requirements, various fully
Index Terms— Fast transient response, fully integrated linear integrated high-PSR low-dropout regulators (LDOs) have been
regulator, power supply rejection (PSR), wireless power trans- reported. Some studies have adopted a multi-feedback struc-
mission. ture to improve their transient responses and high-frequency
PSR performance [10], [11], while some others have improved
I. I NTRODUCTION their PSR performance through cascading double- or triple-
layers of pass transistors [12]–[14]. The feedforward ripple
R ECENT studies have focused on developing miniaturized
integrated systems for wireless power transmission in
biomedical implants [1]–[8]. To reduce the size of the implant
cancellation (FFRC) technique was also reported to have
superior PSR performance [15]–[18]. FFRC technique injects
and to avoid parasitic bond wire inductances [9], the noise- a predefined portion of the ripple current to the output node
sensitive analog-to-digital converters and voltage reference of the regulator to cancel the ripple injection. However, most
circuits are usually integrated on the same die along with noisy of the aforementioned studies that performed ripple analysis
rectifier and digital controllers. A linear regulator with a high did not consider the reference voltage ripple. Because the
PSR and fast settling speed is required to protect sensitive output voltage of the regulator follows the reference voltage,
circuits from noise injection. Conventionally, loading a bulky any small ripples on the reference voltage would also appear
decoupling capacitor on the output node of the regulator on the output of the regulator. Therefore, the overall PSR
can effectively filter out the high frequency components and performance is not as promising even though the regulator
improve PSR and transient performance. However, the usage itself is well designed to reject supply ripples.
of a large off-chip decoupling capacitor to achieve better PSR Conventionally, ripple injection through reference voltage
performance worsens the form factor of the implants. can be alleviated by loading a bulky decoupling capacitor
or using a pre-regulation technique on the reference circuit
Manuscript received March 1, 2020; revised May 18, 2020 and June 15, [19]–[22]. However, these solutions suffer from an increase in
2020; accepted July 2, 2020. Date of publication July 16, 2020; date of current
version October 30, 2020. This work was supported by the Ministry of Science both the die area and quiescent current. To address the issues
and Technology under Grant MOST 109-2218-E-007-019 and Grant MOST pertaining to the reference ripple, a linear regulator (Fig. 1)
108-2262-8-007-017. This article was recommended by Associate Editor M. was proposed with its reference circuit supplied directly by the
Onabajo. (Corresponding author: Kea-Tiong Tang.)
The authors are with the Department of Electrical Engineering, regulator output (VOUT ), instead of the regulator input (VIN ).
National Tsing Hua University, Hsinchu 300044, Taiwan (e-mail: This structure isolates the reference circuit from the noisy
[email protected]; [email protected]). supply voltage and thus achieves better PSR performance.
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org. In the following section, the term “input-supplied” is used to
Digital Object Identifier 10.1109/TCSI.2020.3008031 indicate the structure that the reference circuit is supplied by
1549-8328 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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CHEN AND TANG: FULLY INTEGRATED HIGH-POWER-SUPPLY-REJECTION LINEAR REGULATOR 3829

Fig. 2. Transistor level schematics of the proposed linear regulator. The nominal voltage level of I/O nodes are listed in the figure.

VIN , which is the output of rectifier, and “output-supplied” is of M7 . M7 sums up the signals from the two feedback loops,
used to indicate the reference circuit is supplied by VOUT . The and send the signals to the push-pull structure consisting of
output-supplied reference circuit can considerably enhance the M11 and M12 for further amplification. After amplification, the
PSR performance without additional passive components. DC level of the signal is shifted upwards by MSF for proper
The remainder of this paper is organized as follows. operation of the pass transistor.
Section II introduces the architecture and loop analysis of the The dual-feedback structure enables high low-frequency
regulator. Section III introduces the analysis of the PSR and gain for superior static regulation performance and a wide
concept of the output-supplied reference circuit. Section IV UGB for fast transient responses. To overcome the highly
presents the measurement results. Finally, Section V presents variable output voltage of the rectifier that may swing above
the conclusions of this study. the transistor breakdown voltage, the pass transistor is realized
by deep N-well NMOS with its body connected to its source
(VOUT ). The usage of a deep N-well transistor raises the
II. A RCHITECTURE AND F UNDAMENTALS OF THE
breakdown voltage from 1.8V to 2.8V while avoiding body
P ROPOSED R EGULATOR
effect.
The regulator consists of a N-type Pass Transistor, a dual The small signal model of the regulator is shown in Fig. 3.
feedback system, an output-supplied voltage reference circuit, Open-loop gain (AOL ) of the dual-feedback structure can
and a charge pump. The regulator targets to supply 10mA load be approximated as (1), shown at the bottom of the page,
current with 1.1V output voltage for wireless powered bio- where γ f is the ratio of the resistive divider, A E A is the gain
medical implant devices while avoiding the usage of a bulky of the error amplifier, and k1,2 are the current mirror ratio.
decoupling capacitor. However, the shortage of a decoupling gm7 , gm9 , gms f , andgmp1 are the transconductance of M7 , M9 ,
capacitor makes the regulator more vulnerable to noise injec- M S F , and M P1 . ro.M E A2 ,ro.M E A4 , ro11 , andro12 are the output
tions. In addition, the regulator needs to recover swiftly from impedances of M E A2 , M E A4 , M11 , and M12 . C L is a 10pF
sudden activation of stimulator or micro-controller to provide a on-chip capacitor loaded on the output of the error amplifier.
stable supply for the noise-sensitive circuits. To address these C p− p , C g.M P1 and Cout. par are the parasitic capacitances on
issues, a dual-feedback regulator is proposed. As shown in the drain node of the push-pull structure, gate node of M P1 ,
Fig. 2, the proposed regulator is constructed with a high-gain and source node of M P1 respectively. η M S F and η M P1 are two
path and a wide-bandwidth path that together forms a dual- scalar quantities less than one that indicate the low frequency
feedback structure. The signal is first amplified by the error gain of two source followers consisting of M S F and M P1
amplifier and then reaches the gate of M7 , and the signal of respectively. Branch currents MEA1, M8 , M9 , M12 , MCP2 are
the wide-bandwidth path directly flows into the source node 5.8μA, 8.6μA, 8.6μA, 87μA, and 123μA, respectively. The

 
(k1 gm7+k2 gm9 ) ro11 ro12 ηM S F η M P1 gm7+scz
AOL ≈− γ f A E A   +k1 gm7 −1
 
r0,MEA2 ro,M E A4 C L S+1 (r011 ro12 ) C p− p s+1 gms −1
f C g,M P1 S+1 gmp1 R L cout, p ars+1
gm8+scz
(1)

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3830 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 67, NO. 11, NOVEMBER 2020

Fig. 3. Small signal model of the proposed regulator.

TABLE I
BALLPARK VALUE OF I NDIVIDUAL PARAMETERS

Fig. 4. Breakdown of gain components of the proposed regulator. The

dual- feedback structure increases the DC gain for 27dB while expanding
the bandwidth for more than two decades.

For frequencies below the dominant pole, the gain of the

overall feedback loop is dominated by the high-gain loop.
However, as the frequency goes beyond the dominant pole,
the gain of the error amplifier starts diminishing. This causes
the overall feedback loop to be eventually dominated by the
current of MP1 without a load is 116μA. Table I displays the
wide-bandwidth loop, creating a zero at the frequency where
parameters used in the following analyses.
the magnitude of the high-gain loop is equivalent to that of
A. Low-Frequency AC Analysis of Dual-Feedback Bandwidth the wide-bandwidth loop.
 
Compensation  γ f A E A (k1 gm7 + k2 gm9 ) 
 
    = |k1 gm7 | (5)
The N-type pass transistor has the advantage of intrinsic  j ωz ro,MEA2 ro,M E A4 C L + 1 
ripple filtering ability and higher mobility compared to a
Hence the location of this zero can be calculated to be at
P-type pass transistor [11], [23]. The low-frequency small-
around 3.2M H z.
signal transfer function of the loop can be approximated as
follows:
  B. High-Frequency AC Analysis of Dual-Feedback
γ f A E A (k1 gm7 +k2 gm9 ) Bandwidth Compensation
  +k1 gm7 (ro11 ro12 )η M S Fη M P1
s ro,MEA2 ro,M E A4 C L +1 Following the previous subsection, it is clear that the dual-
(2) loop compensation technique introduces a zero. The overall
The γ f A E A (k1 gm7 + k2 gm9 ) term describes the high-gain transfer function in high frequency region will be dominated
path. VOUT is first amplified by the error amplifier and sent by the wide-bandwidth loop because the dominant pole atten-
into a second stage push-pull for amplification through M7 uates the gain of the high-gain loop significantly as shown in
and M9 . The k1 gm7 term describes the wide-bandwidth path. Fig. 4.
In this case, VOUT is first converted into a current by M7 Following (1), the wide-bandwidth loop consists of three
and then amplified by the push-pull structure. The gain of non-dominant poles, resulting in a total phase shift of 270◦
each feedback path of the regulator is simulated individually and introducing potential stability issues. The dominant pole
as displayed in Fig. 4. Following (2), the DC gain ratio of the at the output of the error amplifier is neglected here because
overall loop to the wide-bandwidth path can be derived as: ωz1 causes the wide-bandwidth loop to be dominant.
The three non-dominant poles in the wide-bandwidth loop
γ f A E A (k1 gm7 + k2 gm9 ) + k1 gm7
= 92.805 = 39.35d B (3) are represented as follows:
k1 gm7   −1
−1
As shown in Fig. 4, the DC gain of the wideband loop is ωpout.100μA = gm.M p1 ||R L C out. par ≈ 583M H z (6)
around 20dB with a DC gain of around 60dB for the dual   −1
−1
feedback structure. ωpout.10mA = gm.M p1 ||R L Cout. par ≈ 15G H z (7)
Equation (2) also indicates that loop transfer function has a  −1
ωP2 = (ro11 |C p− p ≈ 25M H z (8)
dominant pole located at:  −1
−1
ω p1 = ((ro.M E A2 | C L )−1 ≈ 11.6K H z (4) ωp3 = gms f C g.M P1 ≈ 159M H z (9)

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CHEN AND TANG: FULLY INTEGRATED HIGH-POWER-SUPPLY-REJECTION LINEAR REGULATOR 3831

Fig. 6. Small-signal model of M7 , M8 , and CZ .

the transconductance of M7 and M8 can be further derived as

a relationship between the mobility (μ) and the size of M7
and M8 . Because μn is around 3 times larger than μp , this
condition can be easily met as long as the size of M7 is not
significantly larger than that of M8 . In this design, the size of
Fig. 5. Simulation results of loop gain for 10mA and 100μA load current M7 and M8 is 1μm 0.18μm, introducing a zero at 40MHz
with and without the zero introduced by CZ . and a pole at 100MHz.
Fig. 5 shows the pole/zero locations in simulation. The
marked values are not exactly the same as the calculated C. Positive Feedback From the Reference Circuit and the
values but are in the same order of magnitude. ωpout.100μA Error Amplifier
is the output pole at the 100μA load current, ωpout.100μA is In this design, the reference circuit is supplied directly
the output pole at 10mA load current, ωp2 is the output pole by the output voltage to achieve better PSR performance.
of the push–pull structure, and ωp3 is the pole formed by the However, this architecture introduces an additional positive
source impedance of MSF and the gate capacitance of the pass feedback path from VOUT through the voltage reference to the
transistor. DC gain for the 10mA and 100μA load currents positive input of the error amplifier. Although this feedback
are 59.8dB and 61.1 dB respectively. The 3db bandwidths in path is, in general, not significant because of the reference
both cases with Cz are 11.6KHz with UGBs of 213MHz and circuit’s PSR performance, it is still worthwhile to show the
291MHz and phase margins of 73 and 61 degrees, respectively. condition where this positive feedback path could be neglected.
Because the pass transistor has a high transconductance, the To guarantee proper functionality of the regulator, the nega-
output pole is located at a higher frequency than the UGB. tive feedback path from the resistive divider needs to outweigh
The dimensions of the N-type pass transistor can be designed the positive feedback path from the reference voltage. This
to be smaller than its P-type counterparts due to its higher is to ensure the overall transfer function is negative. The
mobility. Furthermore, N-type pass transistors do not exhibit resistive divider ratio should be larger than that of the PSR
Miller Effect that amplifies gate-drain capacitance at the gate of the reference circuit. The ratio of the resistive divider in
node. As a result, ωp3 is located at a frequency higher than ωp2 . the presented circuit is 0.61 (−4.4dB). Thus, the PSR of the
Because the bandwidth of the proposed design is in the reference circuit should be at least 10 (20dB) times lower,
MHz range, many intrinsic poles are close to the UGB. i.e., 0.061 (−24.4dB). This level of PSR performance can
This introduces phase margin degradation even with careful be achieved for most reference circuits, which relaxes the
positioning of the three non-dominant poles in the wide- selection of the reference circuits.
bandwidth loop. An additional zero is introduced to improve Other than the positive feedback path resulting from the
the phase margin by adding CZ across the source and drain reference circuit, the error amplifier supplied by VOUT also
nodes of M7 . Fig. 6 illustrates the small-signal model of M7 , creates a positive feedback path. Similarly, the strength of this
M8 , and CZ . The small-signal gate voltage of M7 is set to positive feedback path is determined by the PSR performance
ground because the gain of the error amplifier is degraded of the error amplifier. In order for this positive feedback path to
severely by CL , which introduces a low-impedance path to be ignored, the PSR of the error amplifier should be 10 (20dB)
AC ground. times smaller than the gain of the error amplifier. As shown
From Fig. 6, we can calculate the small-signal transfer in Fig. 4, the gain of the error amplifier is 30dB, and thus the
function from the output node of the regulator to the drain PSR of the error amplifier should be kept smaller than 10dB.
node of M7 (VX ) as follows: In our design, the PSR of the error amplifier is −1dB and thus
VX gm7 + sC Z the condition is met.
= (10)
VOU T gm8 + sC z
If gm7 is designed to be smaller thangm8, then the introduced D. Design of Voltage Reference Circuit
zero is at a frequency region lower than that of the introduced The transistor level diagram of the reference circuit is shown
pole, thus increasing phase margin. Given that the branch in Fig. 7. An integrated implementation avoids traces on PCBs
currents of M7 and M8 are the same, the relationship between or bonding wires that may couple noise from surrounding

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3832 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 67, NO. 11, NOVEMBER 2020

Fig. 8. Cross-coupled charge pump with 20pF MIM capacitor and 30pF
MOS capacitors. The clock signal 1 and 2 are recovered from the 10Mhz
carrier frequency of the WPT system(VINP and VINN ).
Fig. 7. CMOS fully integrated voltage reference circuit.

environments, and thus isolates the source of interference to

the supplied voltage of the reference circuit. This source of on the input node. Compared with a comprehensive analysis
interference is further suppressed by the proposed structure of the ripple-filtering or cancellation technique, the co-analysis
that supplies the reference circuit with VOUT . of the PSR towards the reference voltage and regulators has
The voltage reference circuit [24] comprises of a current rarely been performed.
source (MR,1,2,3,4 ) and a bias-voltage circuit (M5 -M9 ). The To address the ripples on the reference voltage, the general
current source is a self-biasing circuit with MR operating in solution is to add a decoupling capacitor or a passive low-pass
deep triode as a resistor. The current sources are then fed filter on the reference voltage node. These low-pass filters
into three branches of the bias-voltage circuit to create the are designed to have a very low 3-dB bandwidth, typically
reference voltage. in the range of a few kilohertz, to effectively filter out the
The output of the integrated voltage reference circuit is ripples (Fig. 9(a)). This design increases the overall size
designed to be around 0.7V while consuming a quiescent of on-chip capacitors and resistors. However, as depicted in
current of 138nA. PSR performance of the reference circuit Fig. 10, the filtering capacitor is required to be as large as
is smaller than -28.7dB for all frequencies. This level of PSR tens of nanofarads to achieve similar effects as a structure
performance satisfies the requirements mentioned in section that uses VOUT as the supply of the fully integrated reference
II-C required for the negative feedback loop. circuit. Another solution is to adopt the pre-regulate topology
with an additional regulator to boost the PSR of the voltage
E. Design of Charge Pump reference. However, the pre-regulate topology also requires
Charge pump is used for generating a high voltage level for an extra regulator with additional passive components that
proper function of the pass transistor. Because the source side increase the overall area and power consumption. The ripple
of the pass transistor is at a level of 1.1V, a gate voltage larger injection through the reference circuit can also be alleviated if
than 1.6V (Vgs > VTH ) is expected for the pass transistor the reference voltage connects to one reference circuit that is
to operate in the saturation region. However, VIN might not supplied by VIN during start-up, and another that is supplied
always be higher than the requirement in wireless power by VOUT during normal operation. However, this method
conditions, so a charge pump is preferred to operate with a incurs longer startup time because of the two settling time
wider range of VIN . introduced by the reference circuits before normal operation
In this design, a fully integrated cross-coupled charge pump of the regulator. The timing requirement of the switch also
[25] is used and its structure is shown in Fig. 8. The nominal increases system complexity.
input and output voltages of the charge pump while supplying Therefore, in this study, a technique that uses VOUT as the
a load current of 150μA are 1.5V and 2V, respectively at a supply of the reference circuit is proposed as illustrated in
simulated power efficiency of 72%. 40pF MIM capacitor and Fig. 9(b). Fig. 11 compares a fully integrated voltage reference
30pF MOS capacitors were used for the cross-coupled charge supplied by the input voltage to one by the output voltage.
pump. The clock signal is recovered from the 10MHz carrier The PSR performance of the entire regulator (PSRTOT ) can
frequency. The magnitude of the ripples on VCP is on the scale be defined as the combination of the PSR of the feedback
of 100mV. loop (PSRLoop) and the PSR of the reference circuit (PSRREF ).
In the case that the reference circuit is powered by VIN , the
III. D EISGN OF O UTPUT-S UPPLIED VOLTAGE R EFERENCE reference circuit cannot filter out the ripple components on
AND PSR A NALYSIS VIN , resulting in degradation of the overall PSR performance.
If the reference circuit is powered by VOUT , the ripple on the
A. Output-Voltage-Supplied Voltage Reference
reference voltage is filtered out by the regulator. Therefore,
In a high-PSR linear regulator system, most designs focus the amount of ripple injected into VOUT through the reference
on the structural design of the regulator to suppress the ripple circuit is significantly lower than that through the loop

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CHEN AND TANG: FULLY INTEGRATED HIGH-POWER-SUPPLY-REJECTION LINEAR REGULATOR 3833

Fig. 9. Structure of the voltage reference (Ref) that uses (a) VIN as their
supply voltage and (b) VOUT as their supply voltage.

Fig. 11. PSR performance of (a) output-supplied reference circuit and

(b) input- supplied reference circuit. PSRTOT is the total PSR performance,
PSRLoop is the PSR performance if ideal reference voltage is used, and
PSRREF is the PSR performance of the voltage reference circuit.

Fig. 10. PSR performance of output-supplied voltage reference and input-

supplied voltage reference with different LPF capacitors.

B. PSR for the Input Voltage

As shown in Fig. 12, ripple components on VIN can
be injected onto VOUT through two major paths. The first
path is through the source drain small signal resistance of Fig. 12. The structure of intrinsic filtering against the ripple injection from
MP1 (ro.MP1 ). Through this path, the ripple voltage on VIN is VCP and VIN .
converted into a ripple current by ro.MP1 and then injected
directly into VOUT . The second path is through the gate drain Following (11), PSRint can be approximated as a system with
parasitic capacitance (Cgd.MP1 ) of MP1 . Though this path, the one pole, one zero, and a DC gain of -29dB. The location of
ripple voltage on VIN is converted into a ripple current through the zero and the pole can be calculated as
Cgd.MP1 and then converted back to ripple voltage by the 1
source impedance of MSF before being injected into VOUT . ωz.int = −1
≈ 20.6M H z (12)
To distinguish the PSR performance brought by the usage C gd.M P1 gms f (gmp1ro.M P1 + 1)
of N-type pass transistor and the feedback loop, the PSR of 1
ωp.int = −1
≈ 618M H z (13)
the pass transistor without feedback can be defined as intrinsic C gd.M P1 gms f
filtering (PSRint ). The intrinsic filtering of the pass transistor
against the ripples on VIN can be expressed as: where C gd.M P1 is 270fF.
After the ripple voltages on VIN are intrinsically filtered,
1
P S R int ≈ the ripples are further suppressed by the feedback loop of the
g M P1ro.M P1 + 1 regulator
−1
1 + sC gd.M P1 gms f (g M P1 ro.M P1 + 1)
× −1
(11) PSR VIN =
PSRint
≈
PSR int
(14)
1 + sC gd.M P1 gms f 1 + AO L AO L

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3834 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 67, NO. 11, NOVEMBER 2020

Fig. 14. Small signal ripple injection model for VCP .

Fig. 13. Simulated and measured PSR performances against the ripple
injection from input voltage at IL = 11mA.

Because AOL is now in the denominator, the poles analyzed in

Section II-A and Section II-B become zeros, and vice versa.
The PSR performance on VIN is displayed in Fig. 13.

C. PSR for the Charge Pump Voltage

Although the N-type pass transistor benefits from intrinsic
filtering, it requires an additional charge pump for proper
operation. For a fully integrated regulator, the small on-
chip capacitor cannot effectively filter out the high-frequency
switching noise of the charge pump. If the PSR performance
of the against the charge pump is not designed carefully, the
overall ripple performance of the regulator may not be superior Fig. 15. Simulated and Measured PSR performances against the ripples on
to that of a P-type pass transistor design. charge pump voltage at IL=11mA.
Following the small signal ripple injection model shown Like the case of PSRVIN , the injected ripples are further
in Fig. 14, the transfer function from VCP to VG can be suppressed by the feedback system of the regulator
approximated as (20), shown at the bottom of the next page.
VG
The transfer function contains two poles and two zeros with VC P η M P1 VG 1
a low frequency rejection ratio of PSR VCP = ≈ (19)
1 + AO L VC P A O L
gmcp2 1
= −21dB (15) The PSR against ripples on VCP are displayed in Fig. 15.
gms f gmcp1 Rb2 + 1
The location of the two complex zeros can also be calculated D. Startup of the Regulator
as:
Although the reference circuit that is supplied by VOUT can
−1 −1
gm ± j 4gmcp2 Rb2 C F F C gd.MC P2 − gm
2
considerably reduce ripple injections, startup process of the
ωz1cp,z2cp = regulator is still an issue. Most regulators activate the startup
2C F F
≈ (18 ± j16) MHz (16) procedure after sensing a steady reference voltage. Under this
circumstance, the regulator does not need to consider a varying
where gm represents gmcp1 + gmcp2 . The value of C F F is 1.5p, reference voltage during startup. However, for the case that
and C gd.MC P2 is 22.5f. the reference circuit is supplied by VOUT , the regulator must
Because C F F is significantly larger than C gd.MC P2 , the perform startup alongside the startup of the reference circuit.
location of the poles can be approximated as In other words, the regulator must perform startup without its
  reference voltage being ready.
−1
gms f − gms2 −4g
f ms f g mcp1 + 1
Rb2 C F F C gd.MC P2 Fig. 16 displays the circuit diagram of the co-startup
ωp1cp ≈ structure of the regulator, where VStartup is the output of the
2C gd.MC P2
power-on-reset (POR) circuit depicted in Fig. 17. The current
= 2.4MHz (17)
  source is scaled down 1000x by one n-type current mirror and
−1 two p-type current mirrors to charge the MOSFET capacitor,
gms f + gms2 −4g
f ms f gmcp1 + Rb2 C F F C gd.MC P2
1

ωp2cp ≈ reducing the size of this capacitor to 50fF.

2C gd.MC P2 During the startup process, the POR circuit outputs a digital
= 4.4GHz (18) “LOW” because VOUT is not sufficiently high to charge MCAP

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CHEN AND TANG: FULLY INTEGRATED HIGH-POWER-SUPPLY-REJECTION LINEAR REGULATOR 3835

Fig. 16. Equivalent circuit diagram of the regulator during the startup
condition.

Fig. 18. Simulated startup waveform. (a) shows VIN, VOUT, VREF and
EAOUT waveforms during startup. (b) shows Vstartup waveform during
startup.

sub-circuits of the regulator can be supplied by the input

voltage during start-up.
Fig. 17. Power-on-reset circuit diagram. The branch current is marked at
After a short period of time, VOUT is high enough to charge
VOUT=1.09V. MCAP and trigger a digital transition of Vstartup, disconnecting
VOUT and the gate of the MSF . At the first instance of normal
operation, VOUT still maintains the same level as VIN . The
for digital signal transition. Therefore, MUP , which operates error amplifier (EA) senses this high VOUT by comparing the
as a switch, connects the output voltage of the regulator to output of resistive divider to the reference voltage, and thus
the gate of MSF . The equivalent structure of the regulator sets its output to low. When Vstartup transitions from “LOW”
during startup stage would comprise of two source followers, to “HIGH,” the feedback loop pulls the gate voltage of the
namely one P-type follower and one N-type follower con- pass transistor down to return VOUT to the targeted value,
nected together. This structure is similar to a latch but with a causing a sharp droop in the voltage at the moment that the
loop gain lower than unity. POR toggles. Due to the wide-bandwidth characteristic of
The relation between the output voltage and the gate voltage the regulator, the feedback loop of the regulator recovers the
of MP1 can be described as follows: droop in approximately 3 μs. Then, the entire startup operation
is completed, and the regulator is ready to supply the other
VG.M P1 (t + t) = VOU T (t) + |VT H.P | (21) circuits in the implant system. The overall startup time of the
VOU T (t + t) = VG.M P1 (t + t) − VT H.N (22) regulator is simulated to be 14 μs including the startup time
of the rectifier, linear regulator, and reference circuit.
Therefore, the large-signal loop transfer function of the The startup time of the regulator can be further reduced if
output voltage during startup can be derived as follows: the rectifier reaches steady state faster. This can be achieved
by placing a smaller decoupling capacitor at the output of
VOU T (t + t) = VOU T (t) + |VT H.P | − VT H.N (23)
the rectifier; however, the regulator would suffer from larger
In (23), VG.MP1 , VTH.N , and VTH.P are the gate voltage ripples during normal operation. Increasing the voltage level
of MP1 and threshold voltages of N- and P-type MOSFETs, of VIN would also accelerate the startup sequence.
respectively. VOUT (t+t) and VOUT (t) are the voltage levels
after and before the DC loop gain increment, respectively. IV. M EASUREMENT R ESULTS
Because the threshold voltage (515mV) of MP1 is smaller in The proposed fully integrated linear was fabricated using
magnitude than that of MSF (-700mV), the DC loop gain of commercial TSMC 0.18-μm CMOS technology. Fig. 19 illus-
the regulator is a positive value, which indicates that VOUT trates the chip micrograph with a floor plan including the
would be pulled upward to the highest DC level, namely proposed linear regulator, charge pump, and a testing rectifier.
VIN (Fig. 18). Therefore, the reference circuit and the other The designed linear regulator can operate at a minimum

  g
VG s 2 C F F C gd.MC P2 + sC gd.MC P2 gmcp1 + gmcp2 + Rmcp2
≈  
b2
  (20)
VC P s C F F C gd.MC P2 + sgms f C F F + sC gd.MC P2 gms f + gmcp2 + gmcp1 + Rb2 + gms f gmcp1 +
2 1 1
Rb2

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3836 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 67, NO. 11, NOVEMBER 2020

TABLE II
P ERFORMANCE S UMMARY AND B ENCHMARK

Fig. 19. Die photo of the regulator (Reg), reference circuit (Ref), charge Fig. 20. Measured transient load response between 11 mA and 100μA.
pump and the rectifier for testing.

capacitor. Total area consumption of the regulator and the

VIN of 1.3 V to supply an output voltage of 1.09 V. The charge pump was 0.1054 mm2 . A performance comparison
maximum output current was 10mA while consuming a total between the proposed regulator and other output capacitor-less
quiescent current of 276μA. The proposed linear regulator regulators are shown in TABLE II.
did not require an off-chip capacitor but did integrate a 70pF The load transient response of the regulator was measured
on-chip charge pump capacitor, and 10.3pF loop compensation while the load current was varied between 10 mA and 100μA

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CHEN AND TANG: FULLY INTEGRATED HIGH-POWER-SUPPLY-REJECTION LINEAR REGULATOR 3837

Fig. 21. Measured transient line response between 2.5 and 1.5 V.

Fig. 23. Measured startup waveform during inductive link with a load current
of 11mA.

regulator successfully provided a stable DC output voltage

from a relatively noisy condition. Fig. 23 displays the mea-
surement results of the startup waveform and agree well with
the simulated results. Under the startup condition, the output
of the regulator was connected to the input voltage. The output
voltage followed the input voltage for 5μs, as controlled by the
POR circuit, and exhibited a droop before normal operation as
analyzed in Section III-B. The output of the regulator required
approximately 20μs to fully settle, which was limited by the
settling speed of the reference circuit. This settling time can be
reduced by using a reference circuit with faster settling speeds.
V. C ONCLUSION
Fig. 22. Transient measurement result of the ripple filtering ability of the A fully integrated linear regulator is proposed for a wireless
presented regulator under wireless powered condition. power transmission system. The proposed regulator achieves
high PSR with reference to both the input voltage and charge
within 50 ns, as displayed in Fig. 20. The maximum overshoot pump voltage with a built-in reference circuit supplied by the
and undershoot voltages were less than 27 mV with a load output voltage of the regulator. The regulator uses the intrinsic
settling time of 476ns. Static load regulation performance was ripple-filtering ability of the N-type pass transistor to suppress
0.015 V/A. the ripple injection from VIN , and uses a source follower
Fig. 21 indicates that when the input voltage is varied connecting to the gate of MP1 to suppress ripple injections
within 1 V, the linear regulator achieved an overshoot per- from the charge pump. Furthermore, the reference circuit that
formance of 10.5 mV and a droop performance of 12 mV is supplied by VOUT eliminates the usage of a bulky low-pass
within a line settling time of 100 ns. The static line regulation filter while achieving superior PSR performance.
performance was 0.6 mV/V. At 10 MHz, which is the carrier frequency of the wireless
As shown in Fig. 13, PSR performance with reference power system, a PSR performance of −48 and −54 dB was
to VIN was measured to be −71 and −54 dB at 10 kHz achieved with reference to the supply voltage and charge
and 10 MHz, respectively. Fig. 15 depicts the PSR perfor- pump, respectively. The fully integrated linear regulator with
mance with reference to the charge pump. The PSR per- a high PSR is beneficial for decreasing the number of off-chip
formance was −67 and −48 dB at 10 kHz and 10 MHz components, which leads to decreased PCB cost and a better
respectively. The measured PSR performance is limited to form factor.
-70dB because of the environment noise level. This noise ACKNOWLEDGEMENT
level consists of the noise of the regulator, probe, and the
oscilloscope. The authors would like to thank the Chip Implementation
√ Environment noise level is measured to be Center, Taiwan for fabricating the chip.
0.117mV/ H z at 10mA IOUT . For a 500mV PSR testing
signal, the lowest measurable PSR performance is −72dB. R EFERENCES
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Circuits Syst., Kobe, Japan, May 2005, pp. 4245–4248. His research interests include inductive power
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for artificial retina application,” in Proc. VLSI Design, Autom. Test (LDO) design, ac-to-dc converter design, and bio-
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“High PSR low drop-out regulator with feed-forward ripple cancellation
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Mar. 2010. Kea-Tiong Tang (Senior Member, IEEE) received
[17] E. N. Y. Ho and P. K. T. Mok, “Wide-loading-range fully integrated the Ph.D. degree in electrical engineering from
LDR with a power-supply ripple injection filter,” IEEE Trans. Circuits the California Institute of Technology, Pasadena,
Syst. II, Exp. Briefs, vol. 59, no. 6, pp. 356–360, Jun. 2012. CA, USA, in 2001. His research interests include
[18] Y. Lim, J. Lee, S. Park, Y. Jo, and J. Choi, “An external capacitorless bio-inspired learning chip, in-memory computing-
low-dropout regulator with high PSR at all frequencies from 10 kHz to based deep learning accelerator, miniature electronic
1 GHz using an adaptive supply-ripple cancellation technique,” IEEE J. nose system, and biomedical implantable prosthetic
Solid-State Circuits, vol. 53, no. 9, pp. 2675–2685, Sep. 2018. device. He was a recipient of numerous awards,
[19] C. Soell, A. Baenisch, J. Roeber, L. Shi, and R. Weigel, “A multi- including the Outstanding Young Scholar Award,
functional reconfigurable low-power ultra-high PSRR CMOS reference- Wu Ta-You Memorial Award, National Innovation
system,” in Proc. 11th Conf. Ph.D. Res. Microelectron. Electron. Award, and Outstanding Electrical Engineering Pro-
(PRIME), Glasgow, U.K., Jun. 2015, pp. 220–223. fessor Award. He is a TC member of IEEE Biomedical and Life Science
[20] A. I. Kamel, A. Saad, and L. S. Siong, “A high wide band PSRR and fast Circuits Systems Technical Committee (BioCAS), and currently serving as
start-up current mode bandgap reference in 130nm CMOS technology,” a TC Chair. He is currently the Associate Editor-in-Chief of the IEEE
in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Montreal, QC, Canada, T RANSACTIONS ON B IOMEDICAL C IRCUITS AND S YSTEMS (TBioCAS),
May 2016, pp. 506–509. an Associate Editor of the IEEE S ENSORS J OURNAL, and a Guest Editor
[21] Y. Zhu, F. Liu, Y. Yang, G. Huang, T. Yin, and H. Yang, “A −115dB of the IEEE J OURNAL ON E MERGING AND S ELECTED T OPICS IN C IRCUITS
PSRR CMOS bandgap reference with a novel voltage self-regulating AND S YSTEMS (JETCAS). He was an IEEE CAS Chapter Chair of Taipei
technique,” in Proc. IEEE Custom Integr. Circuits Conf., San Jose, CA, Section, from 2017 to 2018. He is currently a Vice Chair of IEEE Taipei
USA, 2014, pp. 1–4. Section. He is serving as a Board of Governor (BoG) of CAS Society.

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