ELX304 : ELECTRONIC

SYSTEM DESIGN
BEng(Hons) Electrical & Electronic Engineering

By:
Sanira Lasantha
BEng ,MSc(Elec. Eng)
Module details

Title Electronic System Design

Module code ElX304
Credit value 20
Leaning hours 200

• Module content and learning outcomes

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PART 1: SYNCHRONOUS SEQUENTIAL DESIGN

LESSON 1 :
SYNCHRONOUS DESIGN CONCEPTS

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INTRODUCTION TO SEQUENTIAL DESIGN
• Combinational vs. sequential logic

In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit

State

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

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Synchronous vs. Asynchronous circuits

Synchronous circuits - only responds when a

clock signal is present
Asynchronous circuits - circuit responds to input changes immediately

Q. Which system do you think is faster: synchronous or asynchronous? And which

is the harder to design?

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Synchronous logic design

• Based on its basic building block - clocked Flipflop.

• A flip-flop is a device which stores a single bit (binary digit) of data

• A flip-flop or latch is a circuit that has two stable states and can be
used to store state information

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FLIPFLOP TYPES
SR LATCH
S R Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X

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• Characteristic table • Excitation table

S R Qn+1 Qn Qn+1 S R
0 0 Qn 0 0 0 X
0 1 0 0 1 1 0
1 0 1 1 0 0 1
1 1 X 1 1 X 0

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• Clocked (synchronous) SR Flip Flop • Clocked (synchronous) SR Flip Flop
with pre-set and clear

S Pr
Q
ck
S
Q Q
R
ck
Q
R

Cr
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D TYPE FLIP FLOP

• The output takes the value of the D input or Data input, and Delays it
by one clock count
• The D flip-flop can be interpreted as a primitive memory cell

Pr Pr
S
D Clocked Q D Q
Clocked
ck
SR FF Q ck D FF Q
R
Cr Qn+1=Dn Cr
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JK FLIP FLOP
Pr Excitation Table
Qn Qn+1 J K
J S 0 0 0 X
Q
0 1 1 X
ck 1 0 X 1
R Q
K 1 1 X 0

Cr

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T TYPE FLIP FLOP

• A Toggle Type FlipFlop can be derived from a JK by

connecting the JK inputs together
T Qn+1
0 Qn
1 𝑄!

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GENERAL SYNCHRONOUS DESIGN
CONSIDERATIONS

The design problem is specified in terms of

its
• Inputs
• outputs and
• sequence of operation.
The number (and type) of Flip flops and
their interconnection with combinational
logic arises from the design process.

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SYNCHRONOUS COUNTER DESIGN
EXAMPLE
1. Problem statement – Design a synchronous counter as it will count
continuously from 0 to 5

2. State diagram -
Each state is shown by a circle, and
identified by a letter A to F. The arrows
show the transitions from state to state,
i.e. it is a
defined sequence. The required outputs
are also shown inside the state circle

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3. State table

The information contained in the State Diagram is transferred to a

State Table

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4. Flipflop choice

Q. How many Flipflops do we need?

Q. What kind of Flipflop should we choose?

Possible to design with any flip flop type. In general the following
considerations apply.

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• JK: Almost always leads to the simplest circuit, but is
complicated, so is best utilized for small problems.
• SR: A very simple Flip-flop structurally, but because we must
take care never to let S=R=1, the logic tends to be more
complex.
• D: Used in registers and in conjunction with programmable
logic, because it is suitable for use in arrays.
• T:Often used for simple counters, asynchronous as well as
synchronous

We shall use the T Type in this example

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5. State assignment
• Although a number of state assignments will lead to circuits of the
same complexity, they will all be different.
• Selecting a good state assignment is a problem which is addressed in
a later lesson.

Example assignment :
A = 000
B = 001
C = 010
D = 011
E = 100
F = 101

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6. Excitation table

Convert the state table to an excitation table

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• Knowing the exitation tables of Flipflops is important !

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7. Flipflop inputs and Output equations
Minimise the T inputs as functions of the Present State in Kmaps

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8. Circuit diagram

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9. Simulation/Implementation

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Q&A
Question 1

Design synchronous counters to count from 0 to 5 using

(a) D Type,
(b) SR Type and
(c) JK type Flipflops.
In each case follow the design process of the example in the previous section.

Determine what happens if you start in an unwanted state.

Compare the solutions in terms of the numbers of gates required and the number
of inputs to these gates

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Answer 1
Applying the Change Table rules for the problem in question we get a
combined Excitation Tables shown below

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Answer 1
Applying the Change Table rules for the problem in question we get a
combined Excitation Tables shown below

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Answer 1
Applying the Change Table rules for the problem in question we get a
combined Excitation Tables shown below

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Answer 1
Applying the Change Table rules for the problem in question we get a
combined Excitation Tables shown below

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Using Kmaps to solve for these inputs we get

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Question 2
Design a synchronous circuit using JK Flipflops which will give outputs
sequentially as follows:

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PART 1: SYNCHRONOUS SEQUENTIAL DESIGN

LESSON 2 :
DESIGN WITH INPUTS

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WORKED EXAMPLE 1

Problem statement: pattern generator

The problem is to generate a pattern as shown below. If the input,

X, is a logic ‘0’, then the pattern to be generated is in 6 steps. If
X=1, then a shortened pattern is produced, but the change can
only be initiated starting from the state whose output is 000.

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State diagram

It can easily be seen that if the input X=0, then we

cycle round the states ABCDEF and back to A. If
X=1, the cycle is shortened
ABEF and back to A.

Q. If there are N inputs, how many arrows leave a state? If a state has no arrows leading to it, what
conclusion can you draw?

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State table

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Excitation table

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WORKED EXAMPLE 2

Problem statement: Pattern detector

Design a synchronous circuit which will give a logic 1 for one clock
period when the following pattern is detected in a series data stream
….0 1 1 0… The final 0 can be the first 0 in the next pattern. Use JK
Flipflops.

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Next : Analysis & optimisation of syncronous designs
• State reduction
• State assignment

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