ee457_Quiz_fl2006_r1.

fm 10/6/06
EE457 Homework #1B 1/10

Fall 2006 EE457 Instructor: Gandhi Puvvada

Quiz (10%) Date: 10/6/2006, Friday
Calculators are allowed.
Closed-book, closed-notes, no cheat-sheets Time: 4:00 - 6:15 PM SGM124
Name: Total points: 145
Student ID: Do NOT write any student ID or SSN Perfect score: 135 / 145

1 ( 12 + 12 + 12 = 36 points) 20 min.
j
State diagram design: 0 1 2 3 4 5 6 7

You are given a 2-dimensional 8x8 array of

0 1 1 1 1 1 1 1 1
single bit locations which is viewed as 8
arrays A[i], each of which has 8 elements 1 1 1 1 1 1 1 1 1
A[i][j] (an array of arrays notation). All the
bit locations are initially filled with 1’s. 2 1 1 1 1 1 1 1 1

12
i3 1 1 1 1 1 1 1 1
pts 1.1 You need to clear a line of bits (a 450 degrees
line going south-east) starting from the given 4 1 1 1 1 1 1 1 1
START
start point I_ini and J_ini. You stop
5 1 1 1 0 1 1 1 1
when you hit the southern or eastern boarder
as shown on the side for I_ini = 5 and 6 1 1 1 1 0 1 1 1
J_ini =3.
7 1 1 1 1 1 0 1 1
END
The C code on the side precisely describes
the requirement.
i = I_ini;
j = J_ini;
while ((i <= 7) && (j <=7))
Complete the incomplete state diagram on
{
the next page. Complete it after considering A[i][j] = 0;
what the following 6 students are saying. i = i + 1;
You do not have to comment on them or j = j + 1;
agree or disagree with them. }

1.1.1 State C: Student #1 wrote the RTL shown on Student #1 Student #3

the side for state C. C C
(Compute)
(Compute)
i<= i + 1; A[i][j] <= 0;
Student #2 said that the order of RTL statements j<= j + 1; if (i < 7)
should be revised so as to make the statement A[i][j] <= 0; i <= i + 1;
if (j < 7)
A[i][j] <= 0 the first statement. j <= j + 1;

Student #3 further wanted to attach conditions as

shown.

Student #4 asked student #3 to correct the "<" (less than) relational operators to "<=" (less than
or equal) relational operators as per the C code.

EE457 Quiz - Fall 2006 1 / 13 C Copyright 2006 Gandhi Puvvada

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1.1.2 Student #5 and Student #6 wrote state transition conditions for state transition arrows diverging
from state C as shown below.
(I = 7) or (J = 7) (I = 8) or (J = 8)
Student #5 Student #6
C C
(Compute) (I = 7) or (J = 7) (Compute) (I = 8) or (J = 8)

1.1.3 Complete the state diagram.

S C
(Compute)

I D
(Initial) S (Done)
i<=I_ini;
j<=J_ini;

12
pts 1.2 In this slightly different design, you need to clear bits along the southern border or eastern border
after clearing bits on the 450 degrees line and reaching one of the borders as shown below.
The goal is to reach A[7][7] and clear that location too.
Obviously you should not clear any other location and you should not waste clocks.
Complete the state diagram for this revised task.
Note: Which ever counter reaches 7 first, should remain stay-put at 7 so that you walk along the
border.

j j
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1

i3 1 1 1 1 1 1 1 1 i3 1 1 1 1
START
1 0 1 1

4 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 0 1
START
5 1 1 1 0 1 1 1 1 5 1 1 1 1 1 1 1 0

6 1 1 1 1 0 1 1 1 6 1 1 1 1 1 1 1 0

7 1 1 1 1 1 0 0 0 END 7 1 1 1 1 1 1 1 0
END

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S C
(Compute)

I D
(Initial) S (Done)
i<=I_ini;
j<=J_ini;

12 This is another variation of question 1.1 above. Instead of travelling at 450, here you travel in a
pts 1.3
"steps" like pattern as shown below. In the design A we take the first step horizontally where
as in the design B we take the first step vertically as shown. Any of them can reach any border
depending on the start point.

A j B j
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
START
1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1

2 1 1 1 1 0 0 1 1 2 1 1 1 1 1 1 1 1

i3 i3
START
1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1

4 1 1 1 1 1 1 0 0 END 4 1 1 0 0 1 1 1 1

5 1 1 1 1 1 1 1 1 5 1 1 1 0 0 1 1 1

6 1 1 1 1 1 1 1 1 6 1 1 1 1 0 0 1 1

7 1 1 1 1 1 1 1 1 7 1 1 1 1 1 0 1 1
END

1.3.1 The following state diagram needs only state transition conditions to be added. The RTL is
complete! Find whether it is suitable for A or B and complete it. Suitable for
____________ ( A / B)

1.3.2 Make sure that your state diagram performs the task correctly for all starting points including
starting points on the borders such as A[7][4] or A[2][7] or A[7][7]. In these cases, your state
machine should clear that single-bit at the starting point and go to the DONE state.

EE457 Quiz - Fall 2006 3 / 13 C Copyright 2006 Gandhi Puvvada

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Inc. J
j <= j + 1;
A[i][j] <= 0;
S

I D
(Initial) (Done)
i<=I_ini;
j<=J_ini; S

Inc. I 1

i <= i + 1;
A[i][j] <= 0;

2 ( 4 points) 2 min.
Cancelled
After START is given, light L should be lit for 1 minute (60 seconds). A slow clock of 1 cycle/
sec. has been provided for this purpose. Note that the I is initiated to 61 (sixty one) in the initial
state.
Three Bruins are asked to find the exit condition EC.

T Bruin #1’s answer: I = 0 is the exit condition EC.

AR EC
ST
RESET

QI START QC EC Bruin #2’s answer: I = 1 is the exit condition EC.

I = 61; I = I - 1;
L = 0; L = 1;
Bruin #3’s answer: I = 2 is the exit condition EC.

The three Bruins have applied for transfer to USC. You want to admit Bruin __________.

3 ( 1 + 10 + 10 = 21 points) 20 min. Cancelled

Datapath unit design and OFL design:

Unlike in lab 1 where you find minimum and maximum, here we need to find the LARGEST
PAIR_SUM (sum of two consecutive memory elements). We only process the first 8 elements of
the array, M(0) through M(7). The numbers, M(0) to M(7) are 4-bit UNSIGNED numbers.
The running largest pair_sum is maintained in a 5-bit register called LPS (LPS for Largest Pair
Sum).

EE457 Quiz - Fall 2006 4 / 13 C Copyright 2006 Gandhi Puvvada

ee457_Quiz_fl2007_r1.fm 10/6/07
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Fall 2007 EE457 Instructor: Gandhi Puvvada

Quiz (10%) Date: 10/5/2007, Friday
Calculators are allowed.
Closed-book, closed-notes, no cheat-sheets Time: 4:00 - 6:15 PM SGM123/124
Name: Total points: 172
Student ID: Do NOT write any student ID or SSN Perfect score: 160 / 172

1 ( 12 + 4 + 14 + 6 + 4 = 40 points) 25 min.
12
pts 1.1 After START is given, light L should be lit for one minute (60 seconds) and then should be off
for half a minute (30 seconds). It should keep repeating this ON/OFF operation until END signal
is given. However, if END signal is given when the light is lit, the light should complete its 60
seconds of ON period before returning to the initial state. A Q_ON_R (Q ON Remaining) state
is provided for this purpose of completing the 60-seconds of ON period. There is no need to
complete the 30 seconds OFF period if END is given while you are in Q_OFF state.

A slow clock of 1 cycle/sec. has been provided for this purpose. Complete the Mealy machine
below. All states and state transition arrows are in place.

Mr. Bruin is a little (?) confused about the terminal count for I and is looking at the following
choices: I = 29 / I = 30 / I = 31 for 30 seconds and I = 59 / I = 60 / I = 61 for 60 seconds.

T
AR
ST
RESET

Q_ON Q_OFF
L = 1; L = 0;
QI START if I = if I =
L = 0;
I <= 0; I <= 1; I <= ;
else else
I <= I + 1; I <= I + 1;
Note:
I <= 0; Note:
You are already given
Q_ON_R I <= 1. Do not change this.
L = 1;
I <= I + 1;
Carefully decide if this
should be
I <= 0; or I <= 1;

4
pts 1.2 Please note that we have written L = 1 and L = 0 (rather than L <= 1 and L <= 0). What could be
the possible difference? Does it matter? __________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

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14 1.3 Convert the above design to a Moore machine. In the incomplete design below, Q_ON_C stands
pts for "Q ON CONTINUATION". This is the last clock of the ON period. Here (while keeping the
light ON) we want to initialize I in preparation to transiting to the Q_OFF state. Similarly
Q_OFF_C stands for "Q OFF CONTINUATION".

Q_OFF_C
L = 0;
I <= ;

Think!

T
AR
ST
RESET

Q_ON Q_OFF
QI START L = 1; L = 0;
L = 0; I <= I + 1; I <= I + 1;
I <= 0;

Q_ON_R Q_ON_C
L = 1; L = 1;
I <= I + 1; I <= 1 ;

Note

6
pts 1.4 If we were to implement the Moore machine using one-hot state assignment, show how you
would complete NSL and asynchronous initialization for the QI Flip-Flop (for the Initial state).

?
? PRE QI
D Q
CLK

CLK Q
CLR
?

4
pts 1.5 If the state machine is put in a box as shown on the
right, can you tell if it is the Mealy machine of START State L LED 330
Q1.1 or the Moore machine of Q1.3?
END Machine Ohm

Yes / No
CLOCK RESET

EE457 Quiz - Fall 2007 2 / 12 C Copyright 2007 Gandhi Puvvada

 EE354L_Final_Fall2016.fm

5 ( 8 + 8 = 16 points) 10 min. Schematic => Verilog Coding

Given below is a small schematic and the associated Verilog code containing two assign
statements and three always clocked blocks. Rewrite the code without any assign statements in
two ways: Method #1: one clocked always block Method #2: Q1 and Q2 generated in one always
clocked block and Q3 generated in a separate clocked block. Do not worry about the data types
of signals (wire or reg). Let us assume that they are adjusted accordingly.
module Inputs/Outputs
D1
D Q Q1
D1 Q1 CLK I0
D3_Int
Q Q3
CLK
Q2 D3 I1 SY D
D2
CLK
D2 CLK
D3 Q3 D Q Q2 EN
X CLK
CLK
EN and D3_Int are internal
signals (not module port pins) X

Method #1: one clocked always block Method #2: Q1 and Q2 in one always block
Q3 in another

8+8
pts

We enjoyed teaching this course. Several of you made very interesting projects. Hope to see you in EE457. - Gandhi

December 11, 2016 7:46 pm EE354L Final - Fall 2016 8/8

C Copyright 2016 Gandhi Puvvada
ee457_Quiz_fl2010.fm 10/1/10 9/10

Fall 2010 EE457 Instructor: Gandhi Puvvada

Quiz (~ 10%) Date: 10/1/2010, Friday in SGM123
Name: Calculators and Cadence Verilog guides are allowed; Closed-book, Closed-notes, Time: 12:00-2:15PM
Total points: 185
Student ID: Do NOT write any student ID or SSN Perfect score: 170 / 185

1 ( 9 + 8 + 1.5 + 2.5 + 30 = 51 points) 40 min.

9
pts 1.1 A and B are negative numbers represented in 2’s complement notation. A is 16-bit in size and B
is 8-bit in size.

For A to be equal to B, all the 8 A bits (A[14:7]) shall be ________________ (all zeros / all ones)
__________ (and / or)
the rest of the 7 A bits (A[6:0]) shall be equal to the corresponding 7 B bits (B[6:0]) .

For A to be less than B (like in -3 is less than -2), it is enough if any of the 8 A bits (A[14:7]) is
a ________ (zero / one). On the other hand , if all those 8 A bits (A[14:7]) are _______________
(all zeros / all ones), then, for A to be less than B, we need the 7-bit A (A[6:0]) to be ___________
(lower / higher) than the corresponding 7-bit B (B[6:0]). Here we compare the two 7-bit numbers
treating them as __________ (signed / unsigned) 7-bit numbers.

1.2 Mealy machine design: Browse through the state diagram on the next page first. Here, we perform
serial inspection of bits of A (or bits of A and B) to compare them. A is a 16-bit number, but
for this part of the question, B can be any where between 8-bit to 16-bit number. Here, we are
allowed to inspect at a time (in a clock) one bit of A (A[I]) and (simultaneously, if needed) one
bit of B (B[J]). The I and the J are indices into the A and B respectively. I is initialized to 15.
J is initiated to Jini (Jinitial) which can be anywhere between 7 through 15 (corresponding
to the B sizes of 8-bit to 16-bit ). You will be needing to compare I and J to see when they are
equal.

Note: Your TA says that ,after START is given, you should not take more than 16 clocks. After
all, A is 16 bits and B is at most 16 bits. So decrement I and/or J as soon as possible!
8
pts 1.2.1 Suppose B is an 8-bit number.
State an example of A and B (in binary) such that the conclusion is drawn in the least number of clocks.
A = _______________________________ ; B = _______________ ;
How many clocks are spent in INS_AI_BJ state for the above numbers? ________
State an example of A and B (in binary) such that the conclusion is drawn in the most number of clocks.
A = _______________________________ ; B = _______________ ;
How many clocks are spent in INS_AI_BJ state for the above numbers? ________
1.5
pts 1.2.2 Since A and B are negative, there is no point looking at A[15] and B[Jini]. True / False
2.5
pts 1.2.3 Since A’s size is fixed at 16-bit, if A is equal to B (equal in value, but not necessarily in size),
it takes the same number of clocks to compare A and B, irrespective of the size of B. True / False

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30 1.2.4 State diagram: Complete the 7 missing state transition conditions for 7 transitition arrows.
pts Complete RTL for the three states. In state C_I_J (compare I and J), you would like to
decrement _______________________________________________ (I / J / I or J / I and J / I
unconditionally and J conditionally / neither I nor J). Crucial point: You want to arrive in
INS_AI_BJ with the right combination of I and J whether you arrive from C_I_J or INS_AI .
If B is an 8-bit number (B[7:0]), the first pair to be compared in INS_AI_BJ is ______________
(A[7],B[7] / A[6],B[6] / neither). And if B is a 16-bit number (B[15:0]), the first pair to be
compared in INS_AI_BJ is __________________ (A[15],B[15] / A[14],B[14] / neither).

RESET START
C_I_J
Compare I, J
I
Initial
A <= Aini; START
B <= Bini;
I <= 15;
J <= Jini;

INS_AI
Inspect A[I]

INS_AI_BJ
Inspect A[I],B[J]
ACK

D_AGTB D_AEQB D_ALTB

Done, A greater than B Done, A equal to B Done, A less than B

ACK ACK ACK

ACK
ACK
EE457 Quiz - Fall 2010 2 / 9 C Copyright 2010 Gandhi Puvvada