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 22CS302-
COMPUTER
ORGANIZATION AND
ARCHITECTURE
DEPARTMENT OF COMPUTER SCIENCE AND
ENGINEERING

BATCH 2022-2026 & II-YEAR

Created By,
Dr.R.SASIKUMAR, Professor, CSE, R.M.D.E.C
Dr.S.MUTHUSUNDARI, Associate Professor, CSE, R.M.D.E.C
Mr.N.SATHISHKUMAR, Assistant Professor, CSE,R.M.D.E.C

Date: 8th August 2023

Table of Contents
Sl. No. Contents Page No.

1 Contents 5

2 Course Objectives 6

3 Pre Requisites (Course Name with Code) 8

4 Syllabus (With Subject Code, Name, LTPC details) 10

5 Course Outcomes (6) 12

6 CO-PO/PSO Mapping 14

Lecture Plan (S.No., Topic, No. of Periods, Proposed date,

7 Actual Lecture Date, pertaining CO, Taxonomy level, Mode 18
of Delivery)

8 Activity based learning 19

Lecture Notes ( with Links to Videos, e-book reference,

9 21
PPTs, Quiz and any other learning materials )
Assignments ( For higher level learning and Evaluation -
10 75
Examples: Case study, Comprehensive design, etc.,)

11 Part A Q & A (with K level and CO) 77

12 Part B Qs (with K level and CO) 85

Supportive online Certification courses (NPTEL, Swayam,

13 87
Coursera, Udemy, etc.,)

14 Real time Applications in day to day life and to Industry 89

Contents beyond the Syllabus ( COE related Value added

15 91
courses)

16 Assessment Schedule ( Proposed Date & Actual Date) 94

17 Prescribed Text Books & Reference Books 96

18 Mini Project 98
Course Objectives
COURSE OBJECTIVES
To describe the basic principles and operations of digital computers.
To design arithmetic and logic unit for various fixed and floating point
operations
To construct pipeline architectures for RISC processors.
To explain various memory systems & I/O interfacings
To discuss parallel processor and multi-processor architectures
PRE REQUISITES
PRE REQUISITES

❖ 22CS101 Problem Solving using C+ + ( Lab Integrated)

❖ 22EC101 Digital Principles and Systems Design ( Lab
Integrated)
❖ 22CS202 Java Programming (LabIntegrated)
Syllabus
 Syllabus
22CS302 COMPUTER ORGANIZATION AND ARCHITECTURE LTPC
(Common to CSE, ADS and CSD) 3 00 3
OBJECTIVES:

The Course will enable learners to:

To describe the basic principles and operations of digital computers.
To design arithmetic and logic unit for various fixed and floating point operations
To construct pipeline architectures for RISC processors.
To explain various memory systems & I/O interfacings
To discuss parallel processor and multi-processor architectures.
UNIT I COMPUTER FUNDAMENTALS 9
Computer Types - Functional Units – Basic Operational Concepts - Number Representation
and Arithmetic Operations - Performance Measurements- Instruction Set Architecture:
Memory Locations and Addresses - Instructions and Instruction Sequencing - Addressing
Modes
UNIT II COMPUTER ARITHMETIC 9
Addition and Subtraction of Signed Numbers - Design of Fast Adders - Multiplication of
Unsigned Numbers - Multiplication of Signed Numbers - Fast Multiplication - Integer Division
- Floating-Point Numbers and Operations
UNIT III BASIC PROCESSING UNIT AND PIPELINING 9
Basic Processing Unit: Concepts - Instruction Execution - Hardware Components -
Instruction Fetch and Execution Steps - Control Signals - Hardwired Control Pipelining - Basic
Concept - Pipeline Organization - Pipelining Issues - Data Dependencies - Memory Delays -
Branch Delays - Resource Limitations - Performance Evaluation - Superscalar Operation.
UNIT IV I/O AND MEMORY 9
Input/Output Organization: Bus Structure - Bus Operation - Arbitration The Memory System:
Basic Concepts - Semiconductor RAM Memories - Read-only Memories - Direct Memory
Access - Memory Hierarchy - Cache Memories - Performance Considerations - Virtual
Memory - Memory Management Requirements Memory Management Requirements -
Secondary Storage.
UNIT V PARALLEL PROCESSING AND MULTICORE COMPUTERS 9
Parallel Processing: Use of Multiple Processors - Symmetric Multiprocessors - Cache
Coherence - Multithreading and Chip Multiprocessors - Clusters - Nonuniform Memory Access
Computers - Vector Computation - Multicore Organization.
TOTAL: 45 PERIODS
TEXTBOOKS:
1.Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer organization, Tata McGraw Hill,
Sixth edition, 2012.
2.David A. Patterson and John L. Hennessy Computer Organization and Design-The
Hardware / Software Interface 5th edition, Morgan Kaufmann, 2013.
Course Outcomes
Course Outcomes
Course Description Knowledge
Outcomes Level

Explain the basic principles and operations of

CO1 K2
digital computers

Design Arithmetic and Logic Unit to perform fixed

CO2 K3
and floating point operations
Develop pipeline architectures for RISC
CO3 K3
Processors.
Summarize Various Memory systems & I/O
CO4 K4
interfacings.

Recognize Parallel Processor and Multi Processor

CO5 K5
Architectures.

Knowledge Level Description

K6 Evaluation

K5 Synthesis

K4 Analysis

K3 Application

K2 Comprehension

K1 Knowledge
CO – PO/PSO Mapping
 CO – PO /PSO Mapping Matrix
CO PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO PS0
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3

1 3 2 1 1 3

2 3 3 2 2 3

3 3 3 1 1 3

4 3 3 1 1 3

5 3 3 1 1 3

6 2 2 1 1 3
 UNIT – I
COMPUTER
FUNDAMENTALS
Lecture Plan
 Lecture Plan – Unit 1– COMPUTER
FUNDAMENTALS
Sl. Topic Number of Proposed Actual CO Taxono Mode of
No. Periods Date Lecture my Delivery
Date Level

Computer Types Chalk &

1 1 07.08.2023 CO1 K2
- Functional Talk
Units
Basic
Chalk &
2 Operational 1 CO1 K2
Talk
Concepts 08.08.2023

Number
Representation Chalk &
3 1 CO1 K2
and Arithmetic Talk
Operations - 10.08.2023
Chalk &
4 Performance - 1 CO1 K2
Talk
Measurements 11.08.2023

Instruction Set
Architecture: Chalk &
5 Memory 1 CO1 K2
Talk
Locations and
Addresses 14.08.2023

Instruction Set
Architecture: Chalk &
6 1 CO1 K2
Memory Talk
Locations and
Addresses 16.08.2023
Instructions and Chalk &
7. Instruction 1 CO1 K4
Talk
Sequencing 17.08.2023

Instructions and Chalk &

8 Instruction 1 CO1 K4
Talk
Sequencing 18.08.2023

Addressing Chalk &

9 1 CO1 K4
Modes Talk
22.08..2023
Activity Based Learning
Activity Based Learning
Sl. No. Contents Page No.

1 QUIZ 72

JAM:
2 72
1-minute Speech Topics
Lecture Notes – Unit 1
1.1 Computer Types
Modern computers can be divided roughly into four general categories:
Embedded computers
▪ This computers are integrated into a larger device or system in order to
automatically monitor and control a physical process or environment.
▪ They are used for a specific purpose rather than for general processing tasks.
▪ Applications: Industrial and home automation, appliances, telecommunication
products, and vehicles.
Personal computers
▪ It is mainly used in homes, educational institutions, and business and
engineering office settings, primarily for dedicated individual use.
▪ Applications: General computation, document preparation, computer-aided
design, audiovisual entertainment, interpersonal communication, and Internet
browsing.
▪ A number of classifications are used for personal computers.
▪ Desktop computers serve general needs and fit within a typical personal
workspace.
▪ Workstation computers offer higher computational capacity and more
powerful graphical display capabilities for engineering and scientific work.
▪ Finally, Portable and Notebook computers provide the basic features
of a personal computer in a smaller lightweight package. They can
operate on batteries to provide mobility.
Servers and Enterprise systems
▪ These are large computers that are meant to be shared by a potentially large
number of users who access them from some form of personal computer over
a public or private network.
▪ Applications: Government agency or a Commercial organization.
Supercomputers
▪ It is most expensive and physically the largest category of computers.
▪ Supercomputers are used for the highly demanding computations needed
in weather forecasting, engineering design and simulation, and scientific
work.
▪ High cost.
❖ Grid computers
▪ Grid computers provide a more cost-effective alternative.
▪ It combines a large number of personal computers an disk storage units
in a physically distributed high-speed network, called a grid, which is
managed as a coordinated computing resource.
▪ By evenly distributing the computational workload across the grid, it is
possible to achieve high performance on large applications ranging from
numerical computation to information searching.
1.2 Functional Units
Functional Units
A computer consists of five functionally independent main parts:
• Input
• Memory
• Arithmetic and Logic Unit (ALU)
• Output
• Control Units
Program: A list of instructions that performs a task.
Data: Numbers and encoded characters that are used as operands by the
Instructions.
Bit: String of binary digits called bits.
Binary-coded decimal (BCD)
Alphanumeric characters:
ASCII (American Standard Code for Information Interchange)
EBCDIC (Extended Binary-Coded Decimal Interchange Code)
I. Input Unit
• Computers accept coded information through input units.
• The most common input device is the keyboard.
• Whenever a key is pressed, the corresponding letter or digit is
automatically converted into its corresponding binary code and
transmitted to the processor.,
• Ex: keyboard, joysticks, trackballs, mouse and touchpad – graphical
input devices
• Ex: Microphones: It is used to captures audio input and converted into
digital code for storage and processing
• Ex: Cameras can be used to capture video input.
II. Memory Unit
• The function of memory unit is to store programs and data.
• It is divided into ‘n’ number of blocks. Each block is divided into ‘n’
number of cells.
• Each cell is capable of storing one bit information at a time.
• There are two classes of storage: primary and secondary.
Primary storage
▪ It is made up of semiconductor material. So it is called Semiconductor
memory.
▪ Data storage capacity is less than secondary memory. Cost is too
expensive than secondary memory.
▪ CPU can access data directly. Because it is an internal memory.
▪ Data accessing speed is very fast than secondary memory.
▪ When the memory is accessed, usually only one word of data is read or
written.
▪ The number of bits in each word is referred to as the
word length of the computer, typically 16,32 or 64 bits.
▪ Ex.RAM & ROM
 1.2. Functional Units
RAM ROM
Random Access Memory Read Only Memory
Volatile memory Non volatile memory
Data lost when the power It retains data even in the
turns off and that is used absence of a power
to hold data and program source and that is store
while they are running. programs between runs.
Temporary storage Permanent storage
medium medium
User perform both read User can perform only
and write operation read operation
Cache Memory:
▪ A small, fast memory that acts as a buffer for a slower, larger memory.
▪ At the start of program execution, the cache is empty. All program
instructions and required data are stored in the main memory.
▪ As execution proceeds, instructions are fetched into the processor chip
and a copy of each is placed in the cache.
▪ Cache memory contains the user frequently accessed information.
Secondary memory
▪ Secondary memory (Nonvolatile storage) is a form of storage that
retains data even in the absence of a power source.
▪ It is made up of magnetic material. So it is called magnetic memory.
▪ Data storage capacity is high than primary memory.
▪ Cost is too low than primary memory.
▪ CPU cannot access data directly. Because it is an external memory.
▪ Data accessing speed is very slow than primary memory.
▪ Ex. Magnetic disk, Hard Disk, CD, DVD, Floppy Disk
III. Arithmetic and Logic Unit (ALU)
▪ Computer programs are executed in the ALU of the processor.
▪ Arithmetic or logic operations such as addition, subtraction,
multiplication, division or comparison of numbers are bringing the
required operands into the processor and the operation is performed by
the ALU
▪ The operands for operations are stored in high-speed storage elements
called registers. Each register can store one word of data.
▪ Access times to registers are somewhat faster than access times to the
fastest cache unit in the memory hierarchy.
1.2 Functional Units
IV. Output
Its function is to send processed results to the outside such as
monitor or printer.
Ex: Printer - mechanical impact heads, ink jet scanners, laser
printers.
Ex: Monitor – CRT, LCD and LED
V. Control Units
The control unit coordinates the following operations like memory,
arithmetic and logic, input and output units, store and process
information and perform input and output operations and sends
control signals to other units and senses their states.
The timing signals that govern the I/O transfers are generated by
the control circuits.
Timing signals also control data transfer between the processor
and the memory.
Timing signals are the signals that determine when a given action
is to take place.
A physically separate unit that interacts with other parts of the
machine.
A large set of control lines (wires) carries the signals used for
timing and synchronization of events in all units.

Figure 1 Basic Functional Units of a Computer

The operations of a computer:
The computer accepts information in the form of programs and data
through an input unit and stores it in the memory.
Information stored in memory is fetched, under program control, into
an ALU, where it is processed.
Processed information leaves the computer through an output unit.
All activities inside the machine are directed by the control unit.
1.3. Basic Operational Concepts
Basic Operational Concepts
To perform a given task, an appropriate program consisting of a list of
instructions is stored in the memory.
Individual instructions are brought from the memory into the
processor, which executes the specified operations.
Data to be used as instruction operands are also stored in the
memory.
A typical instruction might be
Load R2, LOC
❖This instruction reads the contents of a memory location whose
address is represented symbolically by the label LOC and loads them
into processor register R2.
❖The original contents of location LOC are preserved, whereas those of
register R2 are overwritten.
Execution of this instruction requires several steps.
First, the instruction is fetched from the memory into the processor.
Next, the operation to be performed is determined by the control unit.
The operand at LOC is then fetched from the memory into the
processor.
Finally, the operand is stored in register R2.
After operands have been loaded from memory into processor registers,
arithmetic or logic operations can be performed on them. For example,
the instruction
Add R4, R2, R3
adds the contents of registers R2 and R3, then places their sum into
register R4.
The operands in R2 and R3 are not altered, but the previous
value in R4 is overwritten by the sum.
1.3. Basic Operational Concepts
❖After completing the desired operations, the results are in processor
registers.
❖They can be transferred to the memory using instructions such as
Store R4, LOC
❖This instruction copies the operand in register R4 to memory location
LOC. The original contents of location LOC are overwritten, but those
of R4 are preserved.
❖ For Load and Store instructions, transfers between the
memory and the processor are initiated by sending the
address of the desired memory location to the memory unit
and asserting the appropriate control signals.
❖The data are then transferred to or from the memory.
❖Figure shows how the memory and the processor can be connected.
❖In addition to the ALU and the control circuitry, the processor contains
a number of registers used for several different purposes.
❖The instruction register (IR) holds the instruction that is currently
being executed. Its output is available to the control circuits, which
generate the timing signals that control the various processing
elements involved in executing the instruction.
❖The program counter (PC) is another specialized register. It
contains the memory address of the next instruction to be
fetched and executed.
❖During the execution of an instruction, the contents of the PC are
updated to correspond to the address of the next instruction to be
executed.
1.3 Basic Operational Concepts
In addition to the IR and PC, Figure shows general-purpose registers
R0 through Rn−1, often called processor registers. They serve a
variety of functions, including holding operands that have been loaded
from the memory for processing.

Figure 2 – Connection between the processor and the main

memory
The other two registers which facilitate communication with memory
are:
1. MAR – (Memory Address Register):- It holds the address of the
location to be accessed.
2. MDR – (Memory Data Register):- It contains the data to be written
into or read out of the address location.
1.3 Basic Operational Concepts
The processor-memory interface is a circuit which manages the
transfer of data between the main memory and the processor.
If a word is to be read from the memory, the interface sends the
address of that word to the memory along with a Read control
signal.
The interface waits for the word to be retrieved, then transfers it to
the appropriate processor register.
If a word is to be written into memory, the interface transfers both the
address and the word to the memory along with a Write control
signal.
A program must be in the main memory in order for it to be executed.
Operating steps are
Programs reside in the memory & usually get these through the I/P
unit.
Execution of the program starts when the PC is set to point at the first
instruction of the program.
Contents of PC are transferred to MAR and a Read Control Signal is
sent to the memory.
After the time required to access the memory elapses, the address
word is read out of the memory and loaded into the MDR.
Now contents of MDR are transferred to the IR & now the instruction
is ready to be decoded and executed.
If the instruction involves an operation by the ALU, it is necessary to
obtain the required operands.
An operand in the memory is fetched by sending its address to MAR &
Initiating a read cycle.
When the operand has been read from the memory to the MDR, it is
transferred from MDR to the ALU.
After one or two such repeated cycles, the ALU can perform the
desired operation.
If the result of this operation is to be stored in the memory, the result
is sent to MDR.
Address of location where the result is stored is sent to MAR & a write
cycle is initiated.
The contents of PC are incremented so that PC points to the next
instruction that is to be executed.
1.4 Number Representation and Arithmetic
Operations
To represent a number in a computer system is by a string of bits called
binary number.
I. INTEGERS:
Three systems are used for representing integer numbers:
Sign-and-magnitude
1’s-complement
2’s-complement
In all three systems, the leftmost bit is 0 for positive numbers and 1
for negative numbers.

Positive values have identical representations in all systems, but

negative values have different representations.
1.4 Number Representation and Arithmetic
Operations
In the sign-and-magnitude system, negative values are represented by
changing the most significant bit b3 from 0 to 1 in the B vector of the
corresponding positive value.
In 1’s-complement representation, negative values are obtained by
complementing each bit of the corresponding positive number.
The 2’s-complement of a number is obtained by adding 1 to the 1’s-
complement of that number.
There are distinct representations for +0 and −0 in both the sign-and
magnitude and 1’s-complement systems, but the 2’s-complement
system has only one representation for 0.
2’s-complement system leads to the most efficient way to carry out
addition and subtraction operations.

Addition of Unsigned Integers

We add bit pairs starting from the low-order (right) end of the bit
vectors, propagating carries toward the high-order (left) end.
The carry-out from a bit pair becomes the carry-in to the next bit pair
to the left.
The carry-in must be added to a bit pair in generating the sum and
carry-out at that position.
1.4 Number Representation and Arithmetic Operations
Addition and Subtraction of Signed Integers
The 2’s-complement system is the most efficient method for performing
addition and subtraction operations.
To add two numbers, add their n-bit representations, ignoring the carry-out
bit from the most significant bit (MSB) position. The sum will be the
algebraically correct value in 2’s-complement representation if the actual
result is in the range−2n−1 through +2n−1 − 1.
To subtract two numbers X and Y , that is, to perform X − Y , form the 2’s-
complement of Y , then add it to X using the add rule. Again, the result will
be the algebraically correct value in 2’s-complement representation if the
actual result is in the range −2n−1 through +2n−1 − 1.
For example of adding +7 to −3. The 2’s-complement representation for
these numbers is 0111 and 1101, respectively.
If we perform this addition by adding bit pairs from right to left, we obtain

If we ignore the carry-out from the fourth bit position in this addition, we
obtain the correct answer.
If cn = 0, the result obtained is correct. If cn = 1, then a 1 must be added
to the result to make it correct.

Sign Extension
We often need to represent a value given in a certain number of bits by
using a larger number of bits.
For a positive number, this is achieved by adding 0s to the left.
For a negative number in 2’s-complement representation, the leftmost bit,
which indicates the sign of the number, is a 1.
To represent a signed number in 2’s-complement form using a larger
number of bits, repeat the sign bit as many times as needed to the left.
This operation is called sign extension.

Overflow in Integer Arithmetic

When adding unsigned numbers, a carry-out of 1 from the most significant
bit position indicates that an overflow has occurred.
The addition of numbers with different signs cannot cause overflow
because the result is always within the representable range.
1.4 Number Representation and Arithmetic
Operations

2’s-complement Add and Subtract operations.

1.4 Number Representation and Arithmetic
Operations
II. FLOATING POINT NUMBERS
A floating-point number representation is one in which a number is
represented by its sign, a string of significant digits, commonly called
the mantissa, and an exponent to an implied base for the scale factor.

Floating point:
Computer arithmetic that represents numbers in which the binary
point is not fixed.

Fraction:
The value, generally between 0 and 1, placed in the fraction field. The
fraction is also called the mantissa.

Exponent:
In the numerical representation system of floating-point arithmetic,
the value that is placed in the exponent field.

Single precision:
A floating-point value represented in a single 32-bit word. Floating-
point numbers are usually a multiple of the size of a word.
Where s is the sign of the floating-point number (1 meaning
negative), exponent is the value of the 8-bit exponent field (including
the sign of the exponent), and fraction is the 23-bit number.
F involves the value in the fraction field and E involves the value in the
exponent field.
1.4 Number Representation and Arithmetic
Operations
Double precision:
One way to reduce chances of underflow or overflow is called double,
and operations on doubles are called double precision floating-point
arithmetic.
It has a larger exponent. A floating-point value represented in two 32-
bit words.
Where s is still the sign of the number, exponent is the value of the
11-bit exponent field, and fraction is the 52-bit number in the fraction
field.

Normalized number:
A number in floating-point notation that has no leading 0s is known as
normalized number. i.e., a number start with a single nonzero digit.
For example, 1.0ten×10-9 is in normalized scientific notation, but
0.1ten×10-8 and 10.0ten ×10-10 are not.
IEEE 754 Format:
IEEE 754 makes the leading 1-bit of normalized binary numbers
implicit.
Hence, the number is actually 24 bits long in single precision (implied
1 and a 23-bit fraction), and 53 bits long in double precision (1+52).
1.4 Number Representation and Arithmetic
Operations

The desirable notation must therefore represent the most negative

exponent as 00 … 00two and the most positive as 11 … 11two.
This convention is called biased notation, with the bias being the
number subtracted from the normal, unsigned representation to
determine the real value.
IEEE 754 uses a bias of 127 for single precision, so an exponent of -1
is represented by the bit pattern of the value -1+127ten, or
126ten=0111 1110two, and +1 is represented by 1+127, or 128ten =
1000 0000two.
The exponent bias for double precision is 1023. Biased exponent
means that the value represented by a floating-point number is really
1.5 Performance Measurement
The most important measure of the performance of a computer is how
quickly it can execute programs.
The speed with which a computer executes programs is affected by
the design of its instruction set,
its hardware and its software, including the operating system, and
the technology in which the hardware is implemented.
Because programs are usually written in a high-level language,
performance is also affected by the compiler that translates programs
into machine language.
1.TECHNOLOGY
The technology of Very Large Scale Integration (VLSI) that is used to
fabricate the electronic circuits for a processor on a single chip is a critical
factor in the speed of execution of machine instructions.
The speed of switching between the 0 and 1 states in logic circuits is
largely determined by the size of the transistors that implement the
circuits. Smaller transistors switch faster.
Advances in fabrication technology over several decades have reduced
transistor sizes dramatically.
This has two advantages:
instructions can be executed faster, and
more transistors can be placed on a chip, leading to more logic
functionality and more memory storage capacity.
2. PARALLELISM
Performance can be increased by performing a number of operations in
parallel. Parallelism can be implemented on many different levels.
2.1 Instruction-level Parallelism
The simplest way to execute a sequence of instructions in a processor is to
complete all steps of the current instruction before starting the steps of
the next instruction.
If we overlap the execution of the steps of successive instructions, total
execution time will be reduced.
For example, the next instruction could be fetched from memory at the
same time that an arithmetic operation is being performed on the register
operands of the current instruction.
This form of parallelism is called pipelining.
1.5 Performance Measurement
2.2 Multicore Processors
Multiple processing units can be fabricated on a single chip.
The term core is used for each of these processors.
The term processor is then used for the complete chip.
Hence, we have the terminology dual-core, quad-core, and octo-core
processors for chips that have two, four, and eight cores, respectively.

2.3 Multiprocessors
Computer systems may contain many processors, each possibly containing
multiple cores. Such systems are called multiprocessors.
These systems either execute a number of different application tasks in
parallel, or they execute subtasks of a single large task in parallel.
All processors usually have access to all of the memory in such systems,
and the term shared-memory multiprocessor is often used to make
this clear.
The high performance of these systems comes with much higher
complexity and cost, arising from the use of multiple processors and
memory units, along with more complex interconnection networks.
In contrast to multiprocessor systems, it is also possible to use an
interconnected group of complete computers to achieve high total
computational power.
The computers normally have access only to their own memory units.
When the tasks they are executing need to share data, they do so by
exchanging messages over a communication network.
This property distinguishes them from shared-memory multiprocessors,
leading to the name message passing multicomputer.
1.5 Performance Measurement
3. PERFORMANCE AND METRICS refer 1st 4 points

❖The most important measure of the performance of a computer is how

quickly it can execute programs.
❖The speed with which a computer executes programs is affected by
the design of its hardware and its machine language instructions.
❖Because programs are usuaI1y written in a high-level language,
performance is also affected by the compiler that translates programs
into machine language.
❖For best performance, it is necessary to design the compiler, the
machine instruction set, and the hardware in a coordinated way.
❖The operating system overlaps processing, disk transfers, and printing
for several programs to make the best possible use of the resources
available.
❖It is affected by the speed of the processor, the disk, and the printer.
3.1 Elapsed Time:-
❖The total time required to execute the entire program.
❖The elapsed time for the execution of a program depends on all units
in a computer system.
3.2 Processor Time:-
The periods during which the processor is active during the execution of
the program is called the processor time.
The processor time depends on the hardware involved in the execution
of individual machine instructions.
This hardware comprises the processor and the memory, which are
usually connected by a bus.
1.5 Performance Measurement
4. CACHE MEMORY
At the start of execution, all program instructions and the required
data are stored in the main memory.
As execution proceeds, instructions are fetched one by one over the
bus into the processor, and a copy is placed in the cache.
When the execution of an instruction calls for data located in the main
memory, the data are fetched and a copy is placed in the cache.
Later, if the same instruction or data item is needed a second time, it
is read directly from the cache.
The processor and a relatively small cache memory can be fabricated
on a single integrated circuit chip.
The internal speed of performing the basic steps of instruction
processing on such chips is very high and is considerably faster than
the speed at which instructions and data can be fetched from the
main memory.
A program will be executed faster if the movement of instructions and
data between the main memory and the processor is minimized, which
is achieved by using the cache.
For example, suppose a number of instructions are executed
repeatedly over a short period of time, as happens in a program loop,
these instructions are made avai1able in the cache; and they can be
fetched quickly during the period of repeated use.
The same applies to data that are used repeatedly.
1.5 Performance Measurement
5. PROCESSOR CLOCK
Processor circuits are controlled by a timing signal called a clock.
The clock defines regular time intervals, called clock cycles.
To execute a machine instruction, the processor divides the action to be
performed into a sequence of basic steps, such that each step can be
completed in one clock cycle.
The length P of one clock cycle is an important parameter that affects
processor performance.
Its inverse is the clock rate, R = 1/P, which is measured in cycles per
second.
The standard electrical engineering terminology for the term “cycles per
second’ is called hertz (Hz).
The term “million” is denoted by the prefix Mega (M) and “billion’ is
denoted by the prefix Giga (G). Hence, 500 million cycles per second is
usually abbreviated to 500 Megahertz (MHz) and 1250 million cycles per
second is abbreviated to 1.25 Gigahertz (GHz).
6. BASIC PERFORMANCE EQUATION
Let T be the processor time required to execute a program that has been
prepared some high-level language.
The number N is the actual number of instruction executions, and is not
necessarily equal to the number of machine instructions in the object
program.
Some instructions may be executed more than once which is the case for
instructions inside a program loop. Others may not be executed at all,
depending on the input data used.
Suppose that the average number of basic steps needed to execute one
machine instruction is S, where each basic step is completed in one clock
cycle.
If the clock rate is R cycles per second, the program execution time is
given by
NxS
T = R
This is referred to as the basic performance equation.
1.5 Performance Measurement
The performance parameter T for an application program is much more
important to the user than the individual values of the parameters N, S. or
R.
To achieve high performance, by reduce the value of T, which means
reducing N and S, and increasing R.
The value of N is reduced if the source program is compiled into fewer
machine instructions.
The value of S is reduced if instructions have a smaller number of basic
steps to perform or if the execution of instructions is overlapped.
Using a higher-frequency clock increases the value or R, which means
that the time required to complete a basic execution step is reduced.
We must emphasize that N, S, and R are not independent parameters:
changing one may affect another.

7. CLOCK RATE
There are two possibilities for increasing the clock rate, R.
First, improving the integrated-circuit (IC) technology makes logic circuits
faster, which reduces the time needed to complete a basic step.
This allows the clock period P, to be reduced and the clock rate R, to be
increased.
Second reducing the amount of processing done in one basic step also
makes it possible to reduce the clock period. P.
Increases in the value of R that are entirely caused by improvements in IC
technology affect all aspects of the processor’s operation equally with the
exception of the time it takes to access the main memory.
In the presence of a cache, the percentage of accesses to the main
memory is small.
The value of T will be reduced by the same factor as R is increased
because S and N are not affected.
The impact on performance of changing the way in which instructions are
divided into basic steps is more difficult to assess.
1.5 Performance Measurement
8. PIPELINING AND SUPERSCALAR OPERATION
If the instructions are executed one after another, the value of S, which is
the total number of basic steps or clock cycles, required to execute an
instruction.
A substantial improvement in performance can be achieved by over
lapping the execution of successive instructions, using a technique called
pipelining.
Consider the instruction
Add RI, R2, R3
which adds the contents of registers R1 and R2, and places the sum into
R3.The contents of R1 and R2 are first transferred to the inputs of the
ALU. After the add operation is performed, the sum is transferred to R1.
The processor can read the next instruction from the memory while the
addition operation is being performed.
Then, if that instruction also uses the ALU, its operands can be transferred
to the ALU inputs at the same time that the result of the Add instruction is
being transferred to R3.
The ideal value S = 1 cannot be attained in practice for a variety of
reasons. However, pipelining increases the rate of executing instructions
significantly and causes the effective value of S to approach 1.
A higher degree of concurrency can be achieved if multiple instruction
pipelines are implemented in the processor.
This means that multiple functional units are used, creating parallel paths
through which different instructions can be executed in parallel.
With such an arrangement, it becomes possible to start the execution of
several instructions in every clock cycle. This mode of operation is called
superscalar execution.
If it can be sustained for a long time during program execution, the
effective value of S can be reduced to less than one.
Parallel execution must preserve the logical correctness of programs, that
is, the results produced must be the same as those produced by serial
execution of program instructions. Many of today’s high-performance
processors are designed to operate in this manner.
1.5 Performance Measurement
9. INSTRUCTION SET: CISC AND RISC

RISC CISC

It is a Reduced Instruction Set It is a Complex Instruction Set

Computer. Computer.

It emphasizes on software to optimize It emphasizes on hardware to

the instruction set. optimize the instruction set.

It is a hard wired unit of Microprogramming unit in CISC

programming in the RISC Processor. Processor.

It requires multiple register sets to It requires a single register set to

store the instruction. store the instruction.

RISC has simple decoding of CISC has complex decoding of

instruction. instruction.

Uses of the pipeline are simple in Uses of the pipeline are difficult in
RISC. CISC.

It uses a limited number of It uses a large number of instruction

instruction that requires less time to that requires more time to execute
execute the instructions. the instructions.

The execution time of RISC is very The execution time of CISC is longer.
short.

It has fixed format instruction. It has variable format instruction.

The program written for RISC Program written for CISC architecture
architecture needs to take more tends to take less space in memory.
space in memory.

RISC architecture can be used with CISC architecture can be used with
high-end applications like low-end applications like home
telecommunication, image automation, security system, etc.
processing, video processing, etc.
1.5 Performance Measurement
10. PERFORMANCE MEASUREMENT
The only parameter that properly describes performance of a computer is
the execution time.
Computing the value of T is not simple. Moreover, parameters such as the
clock speed and various architectural features are not reliable indicators
of the expected performance.
For these reasons, the computer community adopted the idea of
measuring computer performance using benchmark programs.
To make comparisons possible, standardized programs must be used.
The performance measure is the time it takes a computer to execute a
given benchmark.
Initially, some attempts were made to create artificial programs that
could be used as standard benchmarks.
A nonprofit organization called System Performance Evaluation
Corporation (SPEC) selects and publishes representative application
programs for different application domains, together with test results for
many commercially available computers.
Thus, a SPEC rating of 50 means that the computer under test is 50
times as fast as the selected reference computer for this particular
benchmark.
The test is repeated for all the programs in the SPEC suite, and the
geometric mean of the results is computed.
Let SPEC be the rating for program i in the suite. The overall SPEC rating
for the computer is given by
Running time on the reference computer
SPEC rating = Running time on the computer under test

where n is the number of programs in the suite.

The SPEC rating is a measure of the combined effect of all factors
affecting performance, including the compiler, the operating system, the
processor and the memory of the computer being tested.
1.6 Instruction Set Architecture:Memory
Locations and Addresses
Number and character operands, as well as instructions, are stored in the
memory of a computer.
The memory consists of many millions of storage cells, each of which can
store a bit of information having the value 0 or 1.
The memory is organized a group of n bits and it can be stored or retrieved
in a single, basic operation.
Each group of n bits is referred to as a word of information, and n is called
the word length.
Modern computers have word lengths that typically range from 16 to 64 bits.
If the word length of a computer is 32 bits, a single word can store a 32-bit
2’s-complement number or four ASCII characters, each occupying 8 bits.
A unit of 8 bits is called a byte. Machine instructions may require one or
more words for their representation.
Accessing the memory to store or retrieve a single item of information,
either a word or a byte, requires addresses for each item location.
It is customary to use numbers from 0 through 2k −1, for some suitable
value of k, as the addresses of successive locations in the memory.
The 2 k addresses constitute the address space of the computer, and the
memory can have up to 2 k addressable locations.
A 32-bit address creates an address space of 232 or 4G (4 giga) locations,
where 1G is 230. Other notational conventions that are commonly used are K
(kilo) for the number 210 (1,024), and T (tera) for the number 240.
1.6 Instruction Set Architecture:Memory
Locations and Addresses
BYTE ADDRESSABILITY
There are three basic information quantities to deal with: the bit, byte, and
word.
A byte is always 8 bits, but the word length typically ranges from 16 to 64
bits.
Memory locations assignments refers to successive byte locations in
memory.
Byte locations have addresses 0, 1, 2, . . . . Thus, if the word length of the
machine is 32 bits, successive words are located at addresses 0, 4, 8, . . . ,
with each word consisting of four bytes.
There are two ways that byte addresses can be assigned across words called
as big-endian and little-endian assignments.
BIG-ENDIAN ASSIGNMENTS
The name big-endian is used when lower byte addresses are used for the
more significant bytes (the leftmost bytes) of the word.
LITTLE-ENDIAN ASSIGNMENTS
The name little-endian is used for the opposite ordering, where the lower
byte addresses are used for the less significant bytes (the rightmost bytes)
of the word.
The words “more significant” and “less significant” are used in relation to the
weights (powers of 2) assigned to bits when the word represents a number.
Both little-endian and big-endian assignments are used in commercial
machines. In both cases, byte addresses 0, 4, 8, . . . , are taken as the
addresses of successive words in the memory and are the addresses used
when specifying memory read and write operations for words.
1.6 Instruction Set Architecture:Memory
Locations and Addresses
WORD ALIGNMENT
In the case of a 32-bit word length, natural word boundaries occur at
addresses 0, 4,8, . . . , as shown in Figure. The word locations have
aligned addresses.
In general, words are said to be aligned in memory if they begin at a
byte address that is a multiple of the number of bytes in a word.
The number of bytes in a word is a power of 2. Hence, if the word
length is 16 (2 bytes), aligned words begin at byte addresses 0, 2, 4, .
. . , and for a word length of 64, aligned words begin at byte addresses
0, 8, 16, . . . .
1.7 Instructions and Instruction Sequencing
INSTRUCTIONS AND INSTRUCTION SEQUENCING
The tasks carried out by a computer program consist of a sequence of
small steps such as,
▪ adding two numbers
▪ testing for a particular condition
▪ reading a character from the keyboard
▪ sending a character to be displayed on a display screen.
A computer must have instructions capable of performing four types of
operations:
• Data transfers between the memory and the processor registers
• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers
REGISTER TRANSFER NOTATION
Transfer of information from one location in the computer to another a
data transfer instructions is used. Locations that are involved in such
transfers are,
▪ Memory locations
▪ Processor registers
▪ Registers in the I/O subsystem.
To identify a location a symbolic name instead of its hardware binary
address is used.
For example, names for the addresses of memory locations may be
LOC,PLACE, A,VAR2; processor register names may be R0, R5; and I/O
register names may be DATAIN, OUTSTATUS, and so on.
The contents of a location are denoted by placing square brackets
around the name of the location.
R1 ← [LOC]
Thus, the expression means that the contents of memory location LOC
are transferred into processor register R1.
As another example, consider the operation that adds the contents of
registers R1 and R2, and then places their sum into register R3. This
action is indicated as
R3 ← [R1] + [R2]
This type of notation is known as Register Transfer Notation (RTN). Note
that the right-hand side of an RTN expression always denotes a value,
and the left-hand side is the name of a location where the value is to be
placed, overwriting the old contents of that location.
1.7 Instructions and Instruction Sequencing
ASSEMBLY LANGUAGE NOTATION
To represent machine instructions and programs we use an Assembly
Language Notation or an assembly language format.
For example, an instruction that transfer from memory location LOC to
processor register R1, is specified by the statement
Move LOC,R1
The contents of LOC are unchanged by the execution of this instruction,
but the old contents of register R1 are overwritten.
The second example of adding two numbers contained in processor
registers R1 and R2 and placing their sum in R3 can be specified by the
assembly language statement
Add R1,R2,R3
BASIC INSTRUCTION FORMATS
The operation of adding two numbers is a fundamental capability in any
computer. The statement
C=A+B
In a high-level language program is a command to the computer to add
the current values of the two variables called A and B, and to assign the
sum to a third variable, C.
When the program containing this statement is compiled, the three
variables, A, B, and C, are assigned to distinct locations in the memory.
The variable names are used to refer to the corresponding memory
location addresses.
The contents of these locations represent the values of the three variables.
Hence, the above high-level language statement requires the action
C ← [A] + [B]
To carry out this action, the contents of memory locations A and B are
fetched from the memory and transferred into the processor where their
sum is computed. This result is then sent back to the memory and stored
in location C.
There are four types of Instruction Formats. They are:
• Three address Instructions
• Two address Instructions
• One address Instructions
• Zero address Instructions
7. Instructions and Instruction Sequencing
(i) Three address Instructions
Assume that this instruction contains the memory addresses of the three
operands—A, B, and C. This three-address instruction can be represented
symbolically as
Add A,B,C
Operands A and B are called the source operands, C is called the
destination operand, and Add is the operation to be performed on the
operands. A general instruction of this type has the format
Operation Source1,Source2,Destination
For a modern processor with a 32-bit address space, a 3-address
instruction is too large to fit in one word for a reasonable word length.
Thus, a format that allows multiple words to be used for a single
instruction would be needed to represent an instruction of this type.
(ii) Two address Instructions
An alternative approach is to use a sequence of simpler instructions to
perform the same task, with each instruction having only one or two
operands. Suppose that two-address instructions of the form are
available.
Operation Source, Destination
An Add instruction of this type is
Add A, B
which performs the operation B←[A] + [B]. When the sum is calculated,
the result is sent to the memory and stored in location B, replacing the
original contents of this location. This means that operand B is both a
source and a destination.
A single two-address instruction cannot be used to solve our original
problem, which is to add the contents of locations A and B, without
destroying either of them, and to place the sum in location C.
The problem can be solved by using another two address instruction that
copies the contents of one memory location into another. Such an
instruction is
Move B, C
which performs the operation C←[B], leaving the contents of location B
unchanged.
1.7 Instructions and Instruction Sequencing
❖The “Move” instruction here does a “Copy” operation. The operation C←
[A] + [B] can now be performed by the two-instruction sequence
Move B, C
Add A, C
❖In all the instructions given above, the source operands are specified first,
followed by the destination.

(iii) One address Instructions

Machine instructions that specify only one memory operand. When a
second operand is needed, as in the case of an Add instruction, it is
understood implicitly to be in a unique location, accumulator.
A processor register, usually called the accumulator, is used for this
purpose. Thus, the one-address instruction
Add A
means the following: Add the contents of memory location A to the
contents of the accumulator register and place the sum back into the
accumulator.
The following are the examples of one-address instructions
Load A
and
Store A
The Load instruction copies the contents of memory location A into the
accumulator, and the Store instruction copies the contents of the
accumulator into memory location A.
Using only one-address instructions, the operation C←[A]+[B] can be
performed by executing the sequence of instructions
Load A
Add B
Store C
Note:
❖The operand specified in the instruction may be a source or a destination,
depending on the instruction.
❖In the Load instruction, address A specifies the source operand, and the
destination location, the accumulator, is implied.
❖On the other hand, C denotes the destination location in the Store
instruction, whereas the source, the accumulator, is implied.
1.7 Instructions and Instruction Sequencing
(iv) Zero address Instruction
It is also possible to use instructions in which the locations of all operands
are defined implicitly.
Such instructions are found in machines that store operands in a structure
called a pushdown stack.
In this case, the instructions are called zero-address instructions.

Push A
Push B
Add
Pop C

Operand A is transferred from memory to pushdown stack.

The second operand B from memory is transferred to stack.
The zero address instruction ‘Add’ , pops the top two contents of the stack
and adds them and stores the result by pushing it into the stack.
The result is then popped and stored into the memory location C.

Types of Instructions:
1. Data Transfer Instructions
1.Register Transfer → Eg. Move
2.Memory Transfer → Eg. Load , Store
2. Arithmetic Instructions - Eg. Add , Sub
3. Logical Instructions - e.g. And , Or , Xor , Shift
4. Control transfer Instructions - Eg. Branch Loop , Branch>0 Loop,
Procedure Call, Return
5. Input-Output Instructions - Eg. Read , Write

Register Transfer Instruction:

Move Source, Destination
which places a copy of the contents of Source into Destination. When data are
moved to or from a processor register, the Move instruction can be used rather
than the Load or Store instructions because the order of the source and
destination operands determines which operation is intended. Thus,
Move A, Ri
is the same as
Load A, Ri
and
Move Ri, A
is the same as
Store Ri, A
1.7 Instructions and Instruction Sequencing
Example: C=A+B
Move A,Ri
Move B,Rj
Add Ri,Rj
Move Rj,C
Inprocessor where one operand may be in the memory bt the other
must be in a register, an instruction sequence for the required task
would be,
Move A, Ri
Add B,Rj
Move Ri,C
INSTRUCTION EXECUTION AND STRAIGHT-LINE SEQUENCING
Figure shows a program segment for the task C ← [A] + [B] as it
appears in the memory of a computer.
This code is written with the assumption that the computer allows only
one memory operand per instruction and has a number of processor
registers.
The next assumption is that the word length is 32 bits and the
memory is byte addressable.
The three instructions of the program are in successive word locations,
starting at location i. Since each instruction is 4 bytes long, the second
and third instructions start at addresses i + 4 and i + 8.
1.7 Instructions and Instruction Sequencing
Steps of program execution:
• The processor contains a register called the program counter (PC), which
holds the address of the instruction to be executed next. To begin
executing a program, the address of its first instruction (i in our example)
must be placed into the PC.
• Then, the processor control circuits use the information in the PC to fetch
and execute instructions, one at a time, in the order of increasing
addresses. This is called straight-line sequencing.
• During the execution of each instruction, the PC is incremented by 4 to
point to the next instruction. Thus, after the Move instruction at location i
+ 8 is executed, the PC contains the value i + 12, which is the address of
the first instruction of the next program segment.
• Executing a given instruction is a two-phase procedure.
First phase:
o In the first phase, called instruction fetch, the instruction is
fetched from the memory location whose address is in the PC.
o This instruction is placed in the instruction register (IR) in the
processor.
Second phase:
o At the start of the second phase, called instruction execute, the
instruction in IR is examined to determine which operation is to be
performed.
o The specified operation is then performed by the processor.
o This often involves fetching operands from the memory or from
processor registers, performing an arithmetic or logic operation, and
storing the result in the destination location.
o At some point during this two-phase procedure, the contents of the
PC are advanced to point to the next instruction. When the execute
phase of an instruction is completed, the PC contains the address of
the next instruction, and a new instruction fetch phase can begin.
o In most processors, the execute phase itself is divided into a small
number of distinct phases corresponding to fetching operands,
performing the operation, and storing the result.
1.7 Instructions and Instruction Sequencing
BRANCHING
In the Figure 2.9 the addresses of the memory locations containing the n
numbers are symbolically given as NUM1, NUM2, . . . , NUMn, and a
separate Add instruction is used to add each number to the contents of
register R0.
After all the numbers have been added, the result is placed in memory
location SUM.
Instead of using a long list of Add instructions, it is possible to place a
single Add instruction in a program loop, as shown in Figure 2.10.
The loop is a straight-line sequence of instructions executed as many times
as needed.
It starts at location LOOP and ends at the instruction Branch>0. During
each pass through this loop, the address of the next list entry is
determined, and that entry is fetched and added to R0.
The address of an operand can be specified in various ways.
Assume that the number of entries in the list, n, is stored in memory
location N, as shown. Register R1 is used as a counter to determine the
number of times the loop is executed.
Hence, the contents of location N are loaded into register R1 at the
beginning of the program. Then, within the body of the loop, the
instruction
1.7 Instructions and Instruction Sequencing
Decrement R1
reduces the contents of R1 by 1 each time through the loop. Execution of
the loop is repeated as long as the result of the decrement operation is
greater than zero.
A branch instruction is used to for the purpose of loop. This type of
instruction loads a new value into the program counter.
As a result, the processor fetches and executes the instruction at this new
address, called the branch target, instead of the instruction at the location
that follows the branch instruction in sequential address order.
A conditional branch instruction causes a branch only if a specified
condition is satisfied. If the condition is not satisfied, the PC is incremented
in the normal way, and the next instruction in sequential address order is
fetched and executed.
In the program in Figure 2.10, the instruction
Branch>0 LOOP
(branch if greater than 0) is a conditional branch instruction that causes a
branch to location LOOP if the result of the immediately preceding
instruction, which is the decremented value in register R1, is greater than
zero.
This means that the loop is repeated as long as there are entries in the list
that are yet to be added to R0.
At the end of the nth pass through the loop, the Decrement instruction
produces a value of zero, and, hence, branching does not occur.
Instead, the Move instruction is fetched and executed. It moves the final
result from R0 into memory location SUM.

CONDITION CODES
The processor keeps track of information about the results of various
operations for use by subsequent conditional branch instructions. This is
accomplished by recording the required information in individual bits, often
called condition code flags.
These flags are usually grouped together in a special processor register
called the condition code register or status register. Individual condition
code flags are set to 1 or cleared to 0, depending on the outcome of the
operation performed.
Four commonly used flags are
N (negative) Set to 1 if the result is negative; otherwise, cleared to 0
Z (zero) Set to 1 if the result is 0; otherwise, cleared to 0
V (overflow)Set to 1 if arithmetic overflow occurs; otherwise, cleared to 0
C (carry) Set to 1 if a carry-out results from the operation; Otherwise,
cleared to 0
1.7 Instructions and Instruction Sequencing
❖The N and Z flags indicate whether the result of an arithmetic or logic
operation is negative or zero.
❖The N and Z flags may also be affected by instructions that transfer
data, such as Move, Load, or Store.
❖The V flag indicates whether overflow has taken place. Overflow
occurs when the result of an arithmetic operation is outside the range
of values that can be represented by the number of bits available for
the operands.
❖The processor sets the V flag to allow the programmer to test whether
overflow has occurred and branch to an appropriate routine that
corrects the problem.
❖Instructions such as BranchIfOverflow are provided for this purpose.
❖A program interrupt may occur automatically as a result of the V bit
being set, and the operating system will resolve what to do.
Overflow Condition
1. Overflow can occur only when adding two numbers that
have the same sign.
2. The carry-out signal from the sign-bit position is not a
sufficient indicator of overflow when adding signed
numbers.
A simple way to detect overflow is to examine the signs of
the two summands X and Y and the sign of the result. When
both operands X and Y have the same sign, an overflow
occurs when the sign of S is not the same as the signs of X
and Y.
Overflow cannot occur
The addition of numbers with different signs cannot cause
overflow.
Carry Flag
The C flag is set to 1 if a carry occurs from the most
significant bit position during an arithmetic operation.
1.8 Addressing Modes

ADDRESSING MODES
❖ In general, a program operates on data that reside in the computer’s
memory. These data can be organized in a variety of ways.
❖ The different ways in which the location of an operand is specified in an
instruction are referred to as addressing modes.
IMPLEMENTATION OF VARIABLES AND CONSTANTS
In assembly language, a variable is represented by allocating a register or a
memory location to hold its value.
Thus, the value can be changed as needed using appropriate instructions.

Variables → Register mode, Absolute mode

Constants → Immediate mode
Pointers → Indirect mode
Arrays → Index mode, Base with index , Base with index and
offset
1.8 Addressing Modes
The definitions of these two modes are:
1) Register mode — The operand is the contents of a processor register;
the name (address) of the register is given in the instruction.
Move R1, R2
The processor registers are used as temporary storage locations
where the data in a register are accessed using the register mode. In
the above data transfer ‘Move’ instruction R1, R2 are register names
and hence are register addressing modes.
2) Absolute mode (Direct Mode) — The operand is in a memory
location; the address of this location is given explicitly in the instruction.
Move LOC, R2
Processor registers are used as temporary storage locations where the
data in a register are accessed using the Register mode. The Absolute
mode can represent global variables in a program. ‘LOC’ is a name for
the memory address, so the data in memory is referred in Direct
mode. A declaration such as
Integer A, B;
in a high-level language program will cause the compiler to allocate a
memory location to each of the variables A and B. Whenever they are
referenced later in the program, the compiler can generate assembly
language instructions that use the Absolute mode to access these
variables.
3) Immediate mode — The operand is given explicitly in the instruction.
Address and data constants can be represented in assembly language using
the Immediate mode.
Move 200immediate, R0
places the value 200 in register R0. Clearly, the Immediate mode is
only used to specify the value of a source operand.
A common convention is to use the sharp sign (#) in front of the value
to indicate that this value is to be used as an immediate operand.
Hence, we write the instruction above in the form
Move #200, R0
1.8 Addressing Modes
Constant values are used frequently in high-level language
programs. For example, the statement
A=B+6
contains the constant 6. Assuming that A and B have been
declared earlier as variables and may be accessed using the
Absolute mode, this statement may be compiled as follows:
Move B, R1
Add #6, R1
Move R1, A
Constants are also used in assembly language to increment a
counter, test for some bit pattern, and so on.
4) Indirect mode —
❖In the following addressing modes, the instruction does not give the
operand or its address explicitly.
❖Instead, it provides information from which the memory address of
the operand can be determined.
❖This address is referred to as the effective address (EA) of the
operand. The effective address of the operand is the contents of a
register or memory location whose address appears in the instruction.
❖This indirection is denoted by placing the name of the register or the
memory address given in the instruction in parentheses as illustrated
in Figure 2.11 and Table 2.1.
❖Indirection can be done in two ways. They are
• Through a general purpose register
Add (R1), R0
To execute the Add instruction in Figure 2.11a, the
processor uses the value B, which is in register R1, as the
effective address of the operand.
It requests a read operation from the memory to read the
contents of location B. The value read is the desired
operand, which the processor adds to the contents of
register R0.
• Through a memory location
Add (A), R0
Indirect addressing through a memory location is also
possible as shown in Figure 2.11b.
In this case, the processor first reads the contents of
memory location A then, requests a second read
operation using the value B as an address to obtain the
operand.
1.8 Addressing Modes

The register or memory location that contains the address of an

operand is called a pointer. Indirection and the use of pointers are
important and powerful concepts in programming.
For example, by changing the contents of register R1 or location A in
Figure 2.11, the same Add instruction fetches different operands to
add to register R0.
In the program in Figure 2.10 for adding a list of numbers, indirect
addressing can be used to access successive numbers in the list,
resulting in the program shown in Figure 2.12.
Register R2 is used as a pointer to the numbers in the list, and the
operands are accessed indirectly through R2.
The initialization section of the program loads the counter value n
from memory location N into R1 and uses the Immediate
addressing mode to place the address value NUM1, which is the
address of the first number in the list, into R2.
Then it clears R0 to 0.
The first two instructions in the loop in Figure 2.12 implement the
unspecified instruction block starting at LOOP in Figure 2.10. The
first time through the loop, the instruction
Add (R2),R0
fetches the operand at location NUM1 and adds it to R0. The
second Add instruction adds 4 to the contents of the pointer R2, so
that it will contain the address value NUM2 when the above
instruction is executed in the second pass through the loop.
1.8 Addressing Modes

Consider the C-language statement

A=∗B;
where B is a pointer variable. This statement may be compiled into
Move B,R1
Move (R1),A
Using indirect addressing through memory, the same action can be
achieved with
Move (B),A
The disadvantage of this indirect addressing mode is that these
instructions access the memory twice to get an operand, which is
not suited to pipelined execution.
Indirect addressing through registers is used extensively.
Advantages are: it is flexible. Also, when absolute addressing is
not available, indirect addressing through registers makes it
possible to access global variables by first loading the operand’s
address in a register.

5) Index mode — The effective address of the operand is generated

by adding a constant value to the contents of a register. It is useful in
dealing with lists and arrays.
The register used may be either a special register provided for this
purpose, or, more commonly; it may be any one of a set of
general-purpose registers in the processor. In either case, it is
referred to as an index register. The Index mode is symbolically
represented as
X(Ri )
1.8 Addressing Modes
where X denotes the constant value contained in the instruction and Ri
is the name of the register involved. The effective address of the
operand is given by
EA = X + [Ri ]
The contents of the index register are not changed in the process of
generating the effective address.
In an assembly language program, the constant X may be given either
as an explicit number or as a symbolic name representing a numerical
value.
When the instruction is translated into machine code, the constant X,
represented as a symbolic name as a part of the instruction, is usually
represented by fewer bits than the word length of the computer.
Since X is a signed integer, it must be sign-extended to the register
length before being added to the contents of the register.
Figure 2.13 illustrates two ways of using the Index mode.
(1) Offset is given as a constant:
❖In Figure 2.13a, the index register, R1, contains the address of a memory
location, and the value X defines an offset (also called a displacement)
from this address to the location where the operand is found.
(2) Offset is in the index register:
❖An alternative use is illustrated in Figure 2.13b.
❖Here, the constant X corresponds to a memory address, and the contents
of the index register define the offset to the operand.
❖In either case, the effective address is the sum of two values; one is given
explicitly in the instruction, and the other is stored in a register.
1.8 Addressing Modes
6) Base with Index -- A variation of the basic index addressing mode
provides a very efficient access to memory operands in practical
programming situations. For example, a second register may be used to
contain the offset X, in which case we can write the Index mode as
(Ri,R j )
The effective address is the sum of the contents of registers Ri and
Rj . The second register is usually called the base register.

Effective Address (EA) = Base register (Ri) + Index register (Rj)

This form of indexed addressing provides more flexibility in

accessing operands, because both components of the effective
address can be changed.
7) Base with index and offset -- This mode is another version of the
Index mode which uses two registers plus a constant, which can be
denoted as
X (Ri, R j )
In this case, the effective address is the sum of the constant X and
the contents of registers Ri and Rj .
This added flexibility is useful in accessing multiple components
inside each item in a record, where the beginning of an item is
specified by the (Ri, R j ) part of the addressing mode.
In other words, this mode implements a three-dimensional array.
1.8 Addressing Modes
8) Relative Addressing mode -- The Index mode uses general-
purpose processor registers. In relative addressing mode, the
program counter, PC, is used instead of a general purpose register.
Then,
X (PC)
can be used to address a memory location that is X bytes away from
the location presently pointed to by the program counter.
The effective address is determined similar to the Index mode but
using the program counter in place of the general-purpose register
Ri.
This mode can be used to access data operands. But, its most
common use is to specify the target address in branch instructions.
An instruction such as
Branch>0 LOOP
causes program execution to go to the branch target location
identified by the name LOOP if the branch condition is satisfied.
This location can be computed by specifying it as an offset from the
current value of the program counter.
Since the branch target may be either before or after the branch
instruction, the offset is given as a signed number.
During the execution of an instruction, the processor increments the
contents of the PC register, such that it points to the next instruction
to be executed.
Most computers use this updated value in computing the effective
address in the Relative mode.
1.8 Addressing Modes
9) Autoincrement mode
❖After accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
❖The Autoincrement mode is represented by putting the specified
register in parentheses, to show that the contents of the register are
used as the effective address, followed by a plus sign to indicate that
these contents are to be incremented after the operand is accessed.
❖Thus, the Autoincrement mode is written as
(R i )+
❖ Implicitly, the increment amount is 1 when the mode is given in
this form.
❖ The Auto increment mode automatically increment the contents
of the register by a value that corresponds to the size of the
accessed operand.
❖ Thus, the increment is 1 for byte-sized operands, 2 for 16-bit
operands, and 4 for 32-bit operands.
10) Autodecrement mode
❖The contents of a register specified in the instruction are first
automatically decremented and are then used as the effective address
of the operand.
❖The Auto decrement mode is denoted by putting the specified register
in parentheses, preceded by a minus sign to indicate that the contents
of the register are to be decremented before being used as the
effective address.
❖Thus, we write
−(Ri )
In this mode, operands are accessed in descending address order.
Advantages:
The main reason for this is that these two modes can be used
together to implement an important data structure called a stack.
The actions performed by the Auto increment and Auto decrement
addressing modes can obviously be achieved by using two
instructions, one to access the operand and the other to increment
or decrement the register that contains the operand address.
Combining the two operations in one instruction reduces the
number of instructions needed to perform the desired task.
Disadvantages:
It is not always advantageous to combine two operations into a
single instruction especially in a pipelined processor.
1.8 Addressing Modes

9 Reduced Instruction Set Computers (RISC)

i. This architecture simplifies the instruction set (i.e.) simple
instructions
ii. Each instruction requires a small number of basic steps to execute.
Hence faster instruction sets.
iii. Relatively few instructions in a RISC processor’s instruction set.
iv. Relatively few simple addressing modes – e.g. register addressing,
immediate operands and relative mode .
v. Memory access is limited to load and store instructions.
vi. All operations are done within the registers of the CPU.
vii. Fixed-length, easily decoded instruction format.
viii. Hardwired rather than micro-programmed control unit, for faster
operations.
ix. Has the ability to execute one instruction per clock cycle by
overlapping in a pipeline.
x. For a processor that has only simple instructions, a large number of
instructions may be needed to perform a given programming task.
xi. So a large value of N and a small value of S.
xii. A relatively large number of registers in the processor unit.
xiii. Efficient instruction pipeline.
10 Complex Instruction Set Computers (CISC)
i. Individual instructions are more complex.
ii. A large number of instructions – typically from 100 to 250
instructions.
iii. Some instructions that perform specialized tasks and are used
infrequently.
iv. A large variety of addressing modes – typically from 5 to 20
different modes.
v. Variable length instruction formats.
vi. Instructions that manipulate operands in memory.
EXAMPLE PROBLEMS
Problem1 :
List the steps needed to execute the machine instruction Load R2, LOC in terms
of transfers between the components and some simple control commands.
Assume that the address of the memory location containing this instruction is
initially in register PC.
Solution: The required steps are:
• Send the address of the instruction word from register PC to the memory and
issue a Read control command.
• Wait until the requested word has been retrieved from the memory, then
load it into register IR, where it is interpreted (decoded) by the control circuitry
to determine the operation to be performed.
• Increment the contents of register PC to point to the next instruction in
memory.
• Send the address value LOC from the instruction in register IR to the memory
and issue a Read control command.
• Wait until the requested word has been retrieved from the memory, then
load it into register R2.

Problem 2:
Quantify the effect on performance that results from the use of a cache in the
case of a program that has a total of 500 instructions, including a 100-
instruction loop that is executed 25 times. Determine the ratio of execution
time without the cache to execution time with the cache. This ratio is called
the speedup.
Assume that main memory accesses require 10 units of time and cache
accesses require 1 unit of time. We also make the following further
assumptions so that we can simplify calculations in order to easily illustrate the
advantage of using a cache:
• Program execution time is proportional to the total amount of time needed
to fetch instructions from either the main memory or the cache, with operand
data accesses being ignored.
• Initially, all instructions are stored in the main memory, and the cache is
empty.
• The cache is large enough to contain all of the loop instructions.

Solution: Execution time without the cache is

EXAMPLE PROBLEMS

Problem 3 :
Problem: Convert the following pairs of decimal numbers to 5-bit 2’s-
complement numbers, then perform addition and subtraction on each pair.
Indicate whether or not overflow occurs for each case. (a) 7 and 13 (b) −12 and
9.
Solution:
The conversion and operations are:
(a) 710 = 001112 and 1310 = 011012 Adding these two positive numbers, we
obtain 10100, which is a negative number. Therefore, overflow has
occurred. To subtract them, we first form the 2’s-complement of 01101,
which is 10011. Then we perform addition with 00111 to obtain 11010,
which is −610, the correct answer.
(b) (b) −1210 = 101002 and 910 = 010012 Adding these two numbers, we
obtain 11101 = −310, the correct answer. To subtract them, we first form
the 2’s-complement of 01001, which is 10111. Then we perform addition
of the two negative numbers 10100 and 10111 to obtain 01011, which is a
positive number. Therefore, overflow has occurred.
ACTIVITY BASED LEARNING
ACTIVITY BASED LEARNING
QUIZ:

https://www.javatpoint.com/computer-architecture-mcq

JAM:
1-minute Speech Topics
IR
PC
MAR
MDR
COA
CA
Generation of Computers
Processor
ALU
Input and Output Unit
Addressing Modes
Read Cycle
Write Cycle

ROLE PLAY:

Basic Operational Concepts

Addressing Modes
Video Links
Video Links
Sl. Topic Video Link
No.
1 Basic Operational https://nptel.ac.in/courses/106105163htt
Concepts ps://www.youtube.com/watch?v=FrKkJb
ZDJ0k
2 Number Representation https://nptel.ac.in/courses/106105163

3 Addressing Modes https://www.youtube.com/watch?v=_CH

4cm5PhK8
4 Instruction Set https://www.youtube.com/watch?v=9-
Architecture 9z32T-5WU
Assignments
Unit - I
Assignment Questions
1. Register R1 and R2 of a computer contain the decimal values 1200
and 4600. What is the effective address of the memory operand in
each of the following instruction? [CO3, K4]
a) Load 20(R1), R5
b) Add –(R2), R5
c) Move #3000, R5
d) Sub (R1)+, R5

2. The memory locations 1000, 1001 and 1020 have data values 18, 1
and 16 respectively before the following program is executed. What
is the value of the memory locations after execution? [CO3, K4]

3. Write a sequence of instructions that will compute the value of y =

x2 + 2x + 3 for a given x using [CO3, K4]

✓ three-address instructions

✓ two-address instructions

✓ one-address instructions
Part A – Questions &
Answers
Part A - Questions & Answers
1. Write the basic functional units of computer ?[CO1, K2 ]
The basic functional units of a computer are input unit ,output unit ,
memory unit , ALU unit and control unit.

2. Define ALU. What are the various operations performed in

ALU? [CO1, K2 ]
ALU is a part of computer that performs all arithmetic and logical
operations. It is a component of central processing unit.
Arithmetic operations: Addition, subtraction, multiplication, division,
increment and decrement;
Logical operations: AND, OR, XOR, NOT, compare, shift, rotate.-

3. Compute the effective CPI for a processor, for the following

instruction mix: [CO1, K 3]
Instruction type Clock cycle count Frequency
ALU operations 1 40
Loads 3 20
Stores 2 10
Branches taken 3 20
Branches untaken 2 10
An enhancement to the processor is made by adding a branch
prediction unit. This decreases the number of cycles taken to execute a
branch from 3 to 2. What is the improvement in performance ?
Speed up =execution time old /execution time new
Execution time old or CPU time=I.C.* Clk Cycles * cycle time
Execution time old =[40*1+20*3+10*2+20*2+10*2]
Cycles*cycles time
The enhancement decreases the number of cycles taken for branch
instruction from 3 to 2. Execution time new
=[40*1+20*3+10*2+20*2+10*2]
=180 cycles *cycle time
Speed up = (200*cycles time)/(180 cycles *cycles time) =1.1
4. What is a bus? What are the different buses in a CPU? [CO1,
K2]
A group of lines that serve as a connecting path for several devices is
called bus. The different buses in a CPU are
->Data bus
-> Address bus
-> Control bus
Part A - Questions & Answers
5. Why data bus is bidirectional and address bus is
unidirectional in most microprocessor? [CO1, K3 ]
Data bus:
The data bus consists of 8, 16, 32 or more parallel signal lines. These
lines are used to send data to memory and output ports ,and to
receive data from memory and input port. Therefore, data bus lines
are bidirectional. This means that CPU can read data on these lines
from memory or from a port, as well as send data out of these lines
to a memory location or to a port. The data bus is connected in
parallel to all peripherals. The communication between peripherals
and CPU is activated by giving output enable pulse to the peripherals.
Outputs of peripherals are floated when they are not in use.
Address bus:
It is a unidirectional bus. The address bus consists of 16, 20, 24 or
more parallel signal lines. On these lines the CPU sends out the
address of the memory location or IO port that is to be written to or
read from. Here, the communication is one-way, the address is send
from CPU to memory and IO port and hence these lines are
unidirectional.

6. What is meant by stored program concepts? Discuss. [CO1,

K2 ]
Stored program concept is an idea of storing the program and data in
the memory.

7. Define multiprogramming. [CO1, K2 ]

Multiprogramming is a technique in several jobs are in main memory
at once and the processor is switched from job as needed to keep
several jobs advancing while keeping the peripheral devices in use.

8. Define multiprocessing. [CO1, K2]

Multiprocessing is the ability of an operating system to support more
than one process at the same time.

9. Define time sharing. [CO1, K2 ]

Time sharing is the process in which the system is designed to allow
many users to use the CPU simultaneously.
Part A - Questions & Answers
10. What is a super computer? [CO1, K2 ]
A computer with high computational speed, very large memory and
expansive parallel structured hardware is known as a super computer.
EX: CDC 6600

11. What is meant by VLSI technology? [CO1, K2 ]

VLSI is the abbreviation for Very Large Scale Integration. In this
technology millions of transistors are put inside a single chip as tiny
components. The VLSI chips do the function of millions of transistors.
These are used to implement parallel algorithms directly in hardware.

12. What are the characteristics of Von Neumann computers?

[CO1, K3]
❖ The program can data were represented in digital form and stored in
the memory.
❖ The architecture has 5 basic parts -> the memory, the ALU, Control
Unit, Input unit and output unit.
❖ It uses binary arithmetic.
❖ There were only fixed point arithmetic and no floating point
arithmetic.
❖ used a special general purpose register called Accumulator.
❖ The first general purpose machine.

13. Define parallel processing. [CO1, K2]

It is an efficient form of information processing to exploit the
concurrent events in the computing process.

14.Define pipelining. [CO1, K2]

Pipelining is technique of decomposing a sequential process in to
number of sub operations and each of these sub operations are carried
out independently in dedicated segments concurrently.

15. Mention some applications of parallel processing. [CO1, K2]

❖ In simulation and Modeling -> weather forecasting, oceanography,
socio economy
❖ Engineering design and automation -> Aerodynamics, finite element
analysis AI
❖ Medical, military and research -> computer assisted topography
genetic engineering etc
❖ Energy resource explosion.
Part A - Questions & Answers
16. Distinguish between hardware and firmware. [CO1, K3 ]
The hardware deals with all electronics and electrical components of a
computer.
EX: IC’s, diodes, resistors, power supplies, tapes etc
The firmware is embedded
software of certain electronic
circuits. EX: ROMBIOS.

17. What is an operating system? [CO1, K2 ]

A System software which acts as an interface between the user and the
machine.

18. Define system throughput. [CO1, K2 ]

It is defined as the number of instructions executed per unit time (sec).

19. What is mainframe computer? [CO3, K2]

It is the large computer system containing thousands of IC’s. It is a
room- sized machine placed in special computer centers and not
directly accessible to average users. It serves as a central computing
facility for an organization such as university, factory or bank.

20. What is mini computer? [CO1, K2]

Minicomputers are small and low cost computers are characterized by
❖ Short word size i.e. CPU word sizes of 8 or 16 bits.
❖ Limited hardware and software facilities.
❖ Physically smaller in size.

21. Define micro computer. [CO1, K2 ]

Microcomputer is a smaller, slower and cheaper computer packing all
the electronics of the computer in to a handful of IC’s, including the CPU
and memory and IO chips.

22. What is workstation? [CO1, K2]

The more powerful desktop computers intended for scientific and
engineering applications are referred as workstations.
Part A - Questions & Answers
23. Write the features of the third generation computers? [CO1,
K2]
❖ Pipelining concept was introduced.
❖ Cache memory concept was introduced to close the speed gap
between the CPU and main memory
❖ Multiprogramming was introduced.
❖ Time sharing concept was introduced.
❖ Virtual memory concept was introduced to close the speed gap
between the CPU and main memory.
❖ Multiprogramming was introduced.
❖ Time sharing concept was introduced.
❖ Virtual memory concept was introduced.
Ex: IBM 360/370, CDC 6600/7600, Texas Instrument’s ASC
(Advanced Scientific Computer), Digital Equipment’s PDP-8.

24. What is load – store architecture? [CO1, K2 ]

In a load / store architecture, operands must be in registers before
they can be processed. The instructions that refer to memory
Locations are load, store and jump / branch .It supports limited set of
addressing modes and use hardware to execute instructions.

25. Explain the absolute and auto increment addressing modes

with an example instruction. [CO1, K2 ]
Absolute or direct addressing: To fetch an operand, the address of the
operand in the memory is given in the instruction. This form is called
direct addressing. This type of addressing mode is used for handling
STATIC data
Add B=> A = A + M [B]
Auto-increment addressing mode: It is similar to register indirect
mode except that register is incremented after its value is used to
access memory.
Add R1, (R2) +;
R1 <- R1 + M [R2]
R2 <- R2 +d

This type of addressing mode is useful for stepping through arrays in a

loop. R2 – start of array d – size of an element
Part A - Questions & Answers
26. Explain the following addressing modes with an example: [CO1, K 2]
❖ Register indirect addressing
❖ Relative addressing
Register indirect addressing:
The effective address of the operand is the contents of the register or memory
location, whose address appears in the instruction.
Add R1, R2 [R3] R1 = R2+ [R3]
Contents of memory pointed by R3.
Application:
1. used in pointers
Add R1, R2, [R3]
Operand R3
2. Memory
Relative addressing:
The effective address is obtained by adding contents of program counter with
displacement.
Effective address = [PC] + displacement
Ex: near, far, short, jump instructions
mem address instruction displacement
1000 near 10
EA for next instruction = [PC] + 10
= 1001 + 10 = 1011
mem address instruction displacement
4000 JC 50
EA = 4001 + 50 = 4051

27. Define index mode. [CO1, K2 ]

In this mode the contents of the index register is added to the address part of the
instruction to get the EA of the operand. The index register is a special purpose
CPU register that contains the index value. The address part of the instruction
determines the starting address of the data array in the memory. Each operand in
the array is stored in the memory relative to the starting address of the array. The
distance between the starting address of the array and the location of the operand
in the array is the index value present in the index register. Any operand in the
array can be accessed with the same instruction provided that the index register
contains the correct index value. The index register can be incremented to
facilitate access to the consecutive operands. Some computers dictate one CPU
register to function as index register. This register is involved implicitly when the
index mode instruction is used.
USE:
The indexed mode is used to access the array type data structure.
Part A - Questions & Answers
28. What is the role of program counter in addressing? [CO1, K2 ]
In this addressing mode the contents of program counter is added to the address
part of the instruction in order to obtain the EA. When the address part of the
instruction is added to the contents of the PC the result produces the EA whose
position is relative to the next instruction.

29. What are the different addressing modes? [CO1, K2 ]

Direct addressing, indirect addressing, immediate addressing, base addressing,
Index addressing, based index addressing, based indexed with displacement
addressing, relative addressing.

30. What are condition codes? Can a processor be designed without any
condition codes? [CO1, K2 ]
Condition codes are 1- bit flag that store information regarding the result of
various operations. These are used in conditional branch instructions. They give
elegant way of handling the conditional control flow.
A processor may be designed without condition codes, but it must have some other
means of handling change in flow control – may be instructions like compare and
branch if equal to zero.

31. Which data structures can be best supported using (a) indirect
addressing mode (b) indexed addressing mode? [CO1, K3 ]
indirect addressing mode – pointer data structure.
indexed addressing mode – array data structure.

32. What are the four basic types of operations that need to be supported
by an instruction set? [CO1, K2 ]
❖ Data transfer between memory and the processor register.
❖ Arithmetic and logic operations on data.
❖ Program sequencing and control.
❖ i/o transfer

33. What are the limitations of assembly languages? [CO1, K2 ]

❖ Limitations of assembly language:
❖ Assembly language is processor dependent hence requires knowledge of
internal details of processor to write a program.
❖ It is less user friendly than higher level languages.
❖ program development is slower than the program development using high level
languages.

34. List the steps involved in the instruction execution. [CO1, K2 ]

❖ Fetch the instruction from the memory.
❖ Decode the instruction.
❖ Fetch the operands from the memory for executing the instruction/
❖ Execute the instruction.
❖ Store the results.
Part B – Questions
Part B Questions
Q. Questions K CO
No. Level Mapping
1 Compare and contrast CISC & RISC K4 CO1
architecture.
2 Classify and explain with examples various K4 CO1
Instructions based on the functions.
3 Classify and explain with examples various K4 CO1
Instructions based on the formats.
4 Explain the architecture of a basic Computer. K2 CO1

5 Explain the various generations of Computer. K2 CO1

6 Describe the basic operations in an instruction K2 CO1

execution.
7 Identify the various performance parameters K3 CO1
for the evaluation of a processor and explain.
8 Explain briefly the Instruction Set K2 CO1
Architecture.
9 Write in detail about various addressing K2 CO1
modes.
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Real time Applications in
day to day life and to
Industry
Real time Applications

Latest Smart TVs

GPS Navigation Systems

Almost all Modern Day Smart Phones

Missile Guidance Systems

Space Exploration (Rovers)

Automobiles (ABS, Airbags)

Industries (Assembly Robots)

Road Safety Systems (Traffic Monitoring and

Collision Alert Systems)

Content Beyond Syllabus
GREAT IDEAS IN COMPUTER ARCHITECTURE
Application of the following great ideas has accounted for much of
the tremendous growth in computing capabilities over the past 50
years.
❖ Design for Moore's law
❖ Use abstraction to simplify design
❖ Make the common case fast
❖ Performance via parallelism
❖ Performance via pipelining
❖ Performance via prediction
❖ Hierarchy of memories
❖ Dependability via redundancy

Design for Moore's Law

❖ Gordon Moore, one of the founders of Intel made a prediction in
1965 that integrated circuit resources would double every 18–
24 months.
❖ This prediction has held approximately true for the past 50
years. It is now known as Moore's Law.
❖ When computer architects are designing or upgrading the
design of a processor they must anticipate where the
competition will be in 3-5 years when the new processor
reaches the market.
❖ Targeting the design to be just a little bit better than today's
competition is not good enough.
VON NEUMANN ARCHITECTURE
John von Neumann coined and developed this architecture. The
computer we are using nowadays is based on the von Neumann
architecture. It has some concepts. It is also known as Princeton
architecture. It renders a unique design for the electronic digital
systems having the following components:
❖ A Central Processing Unit (CPU) with arithmetic and logic unit
(ALU) and processors with attached registers.
❖ A memory that can store data and instructions.
❖ External mass storage or secondary storage.
❖ A Control Unit (CU) with the ability to hold instructions in the
program counter (PC) or instruction register (IR).
❖ Input and output mechanisms and peripherals.

MICRO-ARCHITECTURE
❖ Micro-architecture is the structural design of a microprocessor.
❖ This computer organization leverages a method where the
instruction set architecture holds a built-in processor.
❖ Engineers and hardware scientists implement instruction set
architecture (ISA) with various micro-architectures that vary
because of changing technology.
❖ It includes the technologies used, resources, and methods. Using
this, the processors physically devised to administer a particular
instruction set.
❖ Simply, it is a logical form of all electronic elements and data
pathways present in the microprocessor, designed in a specific
way.
❖ It allows for the optimal completion of instructions. In academe,
it is called computer organization.
Assessment Schedule
(Proposed Date & Actual
Date)
Assessment Schedule
(Proposed Date & Actual Date)
Sl. ASSESSMENT Proposed Actual
No. Date Date

1 FIRST INTERNAL ASSESSMENT 09.09.2023

to
15.09.2023
2 SECOND INTERNAL 26.10.2023
ASSESSMENT to
01.11.2023
3 MODEL EXAMINATION 15.11.2023
to
25.11.2023
4 END SEMESTER EXAMINATION Tentatively
05.12.2023
Prescribed Text Books &
Reference
Prescribed Text Books & Reference
TEXT BOOK:
Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer organization,
Tata McGraw Hill, Sixth edition, 2012.
David A. Patterson and John L. Hennessy Computer Organization and
Design-The Hardware/Software Interface 5th edition, Morgan
Kaufmann, 2013.
REFERENCES:
1. John P.Hayes, Computer Architecture and Organization, Third Edition,
TataMcGraw Hill, 2012John P.Hayes, Computer Architecture and
Organization, Third Edition, TataMcGraw Hill, 2012.
2. David A. Patterson and John L. Hennessy Computer Organization and
Design-The Hardware/Software Interface, 6th edition, Morgan
Kaufmann, 2021David A. Patterson and John L. Hennessy Computer
Organization and Design-The Hardware/Software Interface, 6th
edition, Morgan Kaufmann, 2021
3. John L. Hennessy and David A. Patterson, Computer Architecture – A
Quantitate Approach, Morgan Kaufmann / Elsevier Publishers, Fifth
Edition,2012. John L. Hennessy and David A. Patterson, Computer
Architecture – A Quantitate Approach, Morgan Kaufmann / Elsevier
Publishers, Fifth Edition,2012.
EBOOK LINKS:
https://drive.google.com/file/d/1ZxZ7d5dVERbiCwb5Md5L137fWoMwOF
Bh/view?usp=sharing
Mini Project Suggestions
Mini Project Suggestions
1. Construct an interpreter written in C language to interpret an
assembly language based on the following basic instructions for a
machine having only one register, which is accumulator, and all the
operands are in memory

Opcode, operand comment

ADD X Add memory location x into acc.

SUB X Substract X from Acc.

MUL X Multiply X with Axcc.

DIV X Divide acc. by X.

AND X And X with acc.

NOT X Complement acc.

OR X Or X with acc.

LD X Load memory location X at acc.

ST X Store acc. at memory location X

2. Design a instruction set for a limited functionality machine having all

instructions of 8-bits fixed length only, including opcode and operands.
 Thank you

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