Lesson 006

Boolean Algebra
Boolean algebra is a set of rules, laws and theorems by which logical operations (reasoning)
can be mathematically expressed. It was developed by an English mathematician, educator,
philosopher and logician called George Boole. In Boolean algebra, there exist two statements:
true and false, represented by number 1 and 0 respectively. For Boolean algebra the following
postulates hold:

P1a: 0.0 = 0 P4a: 0  1

P1b: 1+1 = 1 P4b: 1  0

P2a: 0.1 = 1.0 = 0 P5a: X = 1 If X ≠ 0

P2b: 1+0 = 0+1 = 1 P5b: X = 0 If X ≠ 1

P3a: 1.1 = 1
P3b: 0+0 = 0

A check of the first three postulates may be obtained by reference to Fig. 6.0

Fig (a) 0.0 = 0

Fig (b) 1+1 = 1

Fig (c) 0.1 = 0 Fig (d) 1.0 = 0

Fig (d) 1+0 = 1 Fig (e) 0+1 = 1

Fig (g) 1+1 = 1

Fig (h) 0+0 = 0

Fig. 6.0

The theorems given below can be proved with the aid of postulate given above and can easily
be check by use of switch diagrams. Capital letters will be used to label and describe the
states of switches. A bar over letter, e.g. X will indicates an open switch (state 0), while the
same switch in its closed condition i.e. in state 1, will be described by X.

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Theorem 1: Commutative law
Th1a: X  Y  Y  X
Th1b: X  Y  Y  X

Theorem 2: Associative law

Th2a: X  Y  Z  X  Y   Z
Th2b: X  Y  Z  X  Y   Z

Theorem3: distributive law

Th3a: X  Y  Z  X  Y  X  Z
Th3b: X  Y  Z  X  Y   X  Z

Theorem 4: Identities
Th4a: X  1  X
Th4b: X  0  X

Theorem 5: Null element

Th5a: X  0  0
Th5b: X  1  1

Theorem 6: Complements
Th6a X  X  0
Th6b: X  X  1

Theorem7: Idempotent property

Th7a: X  X  X
Th7b: X  X  X

Theorem 8: Absorption
Th8a: X  X  Y  X
Th8b: X  X  Y   X

Theorem 9 Involution (or double negation)

 
Th9 X  X

Theorem 10: Demogan’s theorem

 
Th10 X  Y  Z......  X  Y  Z  ......

Theorem 11: Duality theorem

In this theorem, replace any + by with  and vice-versa and 0 with 1 and vice-versa i.e.
A  0  A 1

Examples 10
Show that
(a) X  X  X
(b) X  X  X

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Solutions

(a) X  X  X
L.H.S X  X  X  X   1 by postulate X  1  X
 
 X  X   X  X by postulate X  X  1
 X  X  XX  X  X  XX
 X0X0
XX X

(b) X  X  X  X  0
R.H.S X  X  0  X  X  X  X
XXX  
 X 1  X
Exercise 11
Show that
(a) X  0  0
(b) X  X  1
(c) X  X  Y  X
Logic Gate
Logic gate is an electronics circuit whose inputs and output are logically related. A logic gate
has one or more inputs but only one output. According to the type of logical operation
between the input and output, the number of standard gates is eight and they are: AND, OR,
INVERTER (COMPLEMENT), TRANSFER (BUFFER), NAND, NOR, EXCLUSIVE-OR
(XOR (or) EX-OR) and EXCLUSIVE NOR (EQUIVALENCE).
The three basic logical operators are: AND, OR and NOT.
An AND operator is denoted by  , sometimes this sign may be omitted, i.e. A  B or AB has
same meaning. Table 6.1 and Fig. 6.1 show the truth table and the symbol for a two inputs
AND gate respectively. A truth table is a table that lists every possible input state and shows
the corresponding output states only.

From Table 6.1, the output is high (1) only when all inputs variables are high (1). The output
is low (0) when one or more inputs are high (0).

Table 6.1
Inputs Output

X Y F

0 0 0 Fig.6.1

0 1 0

1 0 0

1 1 1

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The truth table for a two inputs OR gate is as shown in Table 6.2, The OR operation
produces a high (1) output when any of the inputs is high (1) and produce low (0) when all
inputs variables are low (0). The symbol is as shown in Fig. 6.2

Table 6.2
Inputs Output

X Y F
Fig. 6.2
0 0 0

0 1 1

1 0 1

1 1 1

NOT gate truth table is as shown in Table 6.3. The output is always the complement of the
input variable. The symbol is as shown in Fig. 6.3
Table 6.3
X F

0 1 Fig. 6.3

1 0

The truth table and the symbol of a NAND gate are as shown in Table 6.4 and Fig. 6.4
respectively. The output is low (0) only when all inputs are high (1). The output is high (1)
only if and only if at least one of the inputs is low (0). It is cascading of AND & OR gates. It
is a universal gate because any gate can be constructed with this gate.

Table 6.4
Inputs Output

X Y F
Fig.6.4
0 0 1

0 1 1

1 0 1

1 1 0

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The truth table and the symbol of a NOR gate are as shown in Table 6.5 and Fig. 6.5
respectively. The output is high (1) only when all inputs are low (0). The output is low (0) iff
at least one of the inputs is high (1). NOR gate is a cascading of OR & NOT gates. NOR gate
is also a universal gate.

Table 6.5
Inputs Output

X Y F

0 0 1
Fig. 6.5
0 1 0

1 0 0

1 1 0

The truth table and the symbol of an EXCUSIVE-OR gate are as shown in Table 6.6 and
Fig. 6.6 respectively. EX- OR gate is used to find the number of 1’s in the input, if number of
1’s are even the output is ‘0’ else the input is ‘1’. EX- OR gate can be realized by using
NAND, NOR or (AND & NOT) or (OR & NOT) gates.

Table 6.6
Inputs Output

X Y F

0 0 0
Fig. 6.6
0 1 1

1 0 1

1 1 0

The truth table and the symbol for EXCLUSIVE - NOR gate is as shown in Table 6.7 and
Fig. 6.7 respectively. The output is high (1) only when the inputs are of the same i.e. both low
and both high. The gate can be realized by using NAND/NOR or AND, OR & NOT gate.

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 Table 6.7
Inputs Output

X Y F

0 0 1 Fig. 6.7

0 1 0

1 0 0

1 1 1

The truth table and the symbol of a BUFFER (TRANSFER) gate are as shown in Table 6.8
and Fig. 6.8 respectively. It is a single input single output gate.

Table 6.8
X F
Fig. 6.8
0 0

1 1

AND Gate with Inverted Input

Fig. 6.9 shows the symbol while Table 6.9 shown inputs and output relationship of a two
inputs AND gate with inverted input. It can be seeing from the output of Table 4.9 that AND
gate with inverted input is equivalent to a NOR gate

Table 6.9
Inputs Inverted Output
inputs

A B A B F  AB  AB

0 0 1 1 1 Fig. 6.9
0 1 1 0 0

1 0 0 1 0

1 1 0 0 0

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 NAND Gate with Inverted Input
Fig. 6.10 shows the symbol while Table 6.10 shown inputs and output relationship of a two
inputs NAND gate with inverted input. It can be seeing from the output of Table 4.10 that
NAND gate with inverted input is equivalent to an OR gate.

Table 6.10
Inputs Inverted inputs Output

A B A B F  AB  AB
Fig. 6.10
0 0 1 1 0

0 1 1 0 1

1 0 0 1 1

1 1 0 0 1

Fig. 6.11 shows the symbol while Table 6.11 shown inputs and output relationship of a two
inputs OR gate with inverted input. It can be seeing from the output of Table 6.11 that OR
gate with inverted input is equivalent to a NAND gate.

Table 6.11
Inputs Inverted inputs Output

A B A B F  AB  AB

0 0 1 1 1
Fig. 6.11
0 1 1 0 1

1 0 0 1 1

1 1 0 0 0

Fig. 6.12 shows the symbol while Table 6.12 shows the input and the output relationship of a
two-inputs NOR gate with inverted input respectively. It can be seeing from the output of
Table 6.12 that NOR gate with inverted input is equivalent to a AND gate. Fig. 6.12 shows
the symbol.

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 Table 6.12
Inputs Inverted inputs Output

A B A B F  AB  AB
Fig. 6.12
0 0 1 1 0

0 1 1 0 0

1 0 0 1 0

1 1 0 0 1

Example 11
Determine the output waveform of the AND gate shown below given the input waveforms to
the gate to be A and B.
Solution
The output is as shown in waveform F

A
A
F
B
B

Example 12
Implement the figure below with NAND gate only

A
F

B
C

B
E

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Solution

Follow the following steps:

(i) Convert all AND gates to NAND gates with AND-invert symbols
(ii) Convert all OR gates to NAND gates with invert-OR symbols
(iii) Check all small circles in the diagram. For every small circle that is not
compensated by another small circle along the same line, insert an inverter or
complement the input variable.
(iv) Then replace all the AND-invert and invert-OR symbols with NAND symbols.
A
F

B
C

B
E

A
F

B
C

B
E

Exercise 10

Implement example 11 with NOR gate only.

Solution

(i) Draw the AND-OR logic diagram for the given expression.
(ii) Convert all the OR gates to NOR gates with OR-invert graphic symbols
(iii) Convert all AND gates into NOR gates with invert-AND graphic sysmbols
(iv) Check all small circles in the diagram. For every small circle that is not
compensated by another small circle along the same line, insert an inverter or
complement the input variable
(v) Then replace all the AND-invert and invert-OR symbols with NAND symbols.

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 Analysis and Synthesis of switching Network
A switching network is a network that is made up of a number of switches connected in series
or in parallel or in a series-parallel combination. Operators AND, OR and NOT can be use to
realize all switching functions. The result of an analysis of a switching network is an equation
(expression) representing the function performed by the operators such as AND, OR and
NOT that are operating on the input variables of a network. The examples below make the
explanation better.

Example 12
Derive expression representing the network shown in the Fig below.

A
C

A
E F
C

C
D

Solution

To analyze the gate network, we start from the left and write down the result of each
operation at the output of the respective gates. F1 represent by two AND gates and one OR
gates; F2 is represented by an AND gate and one OR gate. The output is derived from a
3-input AND gate describing the function FA, B, C, D., E )  F1  E  F2 

But F1  AC  AC

& F2  B  CD

  
F  A C  AC  E  B  C D 
Example 13

Realize a circuit of 3 variables in which the output always agrees with the majority of the
inputs.

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Solution

Let the three variables be represented by A, B and C.

The truth table is as shown below

A B C F

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

From the truth table,

FA, B, C   ABC  ABC  ABC  ABC

Simplify the derive function using Boolean algebra

i.e. FA, B, C  ABC  ABC  ABC  ABC

 ABC  A BC  ABC  ABC  ABC  ABC

   
 BC A  A  AC B  B  AB C  C 
 BC  AC  AB  AB  BC  AC

B FA, B, C  AB  BC  AC

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Exercise 11
(1) Simply the following functions:
(i) FA, B  A  AB
(ii) FA, B, C, D   ABCD  ABCD  ABCD  ABCD
(2) The vehicular flow through a costly bridge on an important highway is control by
electronically operated barrier. The barrier allows two cars and a lorry only to pass at a
time subject to the following conditions:
(i) Both cars and the lorry carry no load
(ii) Any or both cars are loaded and the lorry is unloaded
(iii) Non or one car iz loaded while the lorry is loaded
(a) Draw the truth table and derive the switching function
(b) Use Boolean algebra to minimize the function
(c) Use basic logic gate to realize the function.

Example 14
Realize AND, OR & NOT gates by using NAND gate.

Solution

A AB
AB
B

AND gate

AB

OR gate

A A

NOT gate

Exercise 12

Realize AND, OR & NOT gates by using NOR gate.

Example 15

Determine the truth table for the circuit shown below.

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 A
B
F

Solution

The Truth Table

A B C C F
0 0 0 1 1
0 0 1 0 0
0 1 0 1 1
0 1 1 0 1
1 0 0 1 1
1 0 1 0 1
1 1 0 1 1
1 1 1 0 1

Combinational logic circuit

Combinational logic circuit is circuits that consist of logic gate/gates whose output at any
time are determined from the present combination of the input.

Example 16
Design a combinational circuit with three inputs variables whose output will produce 1 when
the input value is even number.

Solution

Let the three input variables be represented by A, B and C and the output variable be
represented by F.
F = 1 for even input values. Therefore, the function = ∑(0,2,4,6). The truth table is as
shown bellow.
A B C F
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

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