LTC485

Low Power RS485

Interface Transceiver
U
FEATURES DESCRIPTIO
■ Low Power: ICC = 300µA Typ The LTC485 is a low power differential bus/line transceiver
■ Designed for RS485 Interface Applications designed for multipoint data transmission standard RS485
■ Single 5V supply applications with extended common-mode range (12V to
■ – 7V to 12V Bus Common-Mode Range Permits – 7V). It also meets the requirements of RS422.
±7V Ground Difference Between Devices on the Bus The CMOS design offers significant power savings over its
■ Thermal Shutdown Protection bipolar counterpart without sacrificing ruggedness against
■ Power-Up/Down Glitch-Free Driver Outputs overload of ESD damage.
Permit Live Insertion or Removal of Transceiver
■ Driver Maintains High Impedance in Three-State The driver and receiver feature three-state outputs, with
or with the Power Off the driver outputs maintaining high impedance over the
■ Combined Impedance of a Driver Output and entire common-mode range. Excessive power dissipation
Receiver Allows Up to 32 Transceivers on the Bus caused by bus contention or faults is prevented by a
■ 70mV Typical Input Hysteresis thermal shutdown circuit which forces the driver outputs
■ 30ns Typical Driver Propagation Delays into a high impedance state.
with 5ns Skew The receiver has a fail-safe feature which guarantees a
■ Pin Compatible with the SN75176A, DS75176A high output state when the inputs are left open.
and µA96176
The LTC485 is fully specified over the commercial and
UO extended industrial temperature range.
APPLICATI S
■ Low Power RS485/RS422 Transceiver
■ Level Translator

UO
TYPICAL APPLICATI
Driver Outputs

RO1 VCC1
R
RE1
Rt A
DE1
DI1 D GND1

Rt
RO2 VCC2
R
RE2
DE2
B
DI2 D GND2
LTC485 • TA01

LTC485 • TA02

1
LTC485
W W W U U W U
ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage ....................................................... 12V ORDER PART
TOP VIEW
Control Input Voltages ................... – 0.5V to VCC + 0.5V NUMBER
RO 1 8 VCC
Driver Input Voltage ....................... – 0.5V to VCC + 0.5V R LTC485CJ8
RE 2 7 B
Driver Output Voltage ........................................... ±14V DE 3 A
LTC485CN8
6
Receiver Input Voltage.......................................... ±14V DI 4 D
5 GND
LTC485CS8
Receiver Output Voltages .............. – 0.5V to VCC + 0.5V LTC485IN8
Operating Temperature Range J8 PACKAGE
8-LEAD CERAMIC DIP
N8 PACKAGE
8-LEAD PLASTIC DIP
LTC485IS8
LTC485I...................................... – 40°C ≤ TA ≤ 85°C S8 PACKAGE LTC485MJ8
LTC485C.......................................... 0°C ≤ TA ≤ 70°C 8-LEAD PLASTIC SOIC
S8 PART MARKING
LTC485M.................................. – 55°C ≤ TA ≤ 125°C TJMAX = 155°C, θJA = 100°C/ W (J)
TJMAX = 100°C, θJA = 130°C/ W (N) 485
Lead Temperature (Soldering, 10 sec)................. 300°C TJMAX = 100°C, θJA = 170°C/ W (S)
485I

ELECTRICAL CHARACTERISTICS VCC = 5V ±5%, unless otherwise noted. (Notes 2 and 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOD1 Differential Driver Output Voltage (Unloaded) IO = 0 ● 5 V
VOD2 Differential Driver Output Voltage (with Load) R = 50Ω (RS422) ● 2 V
R = 27Ω (RS485), Figure 1 ● 1.5 5 V
∆VOD Change in Magnitude of Driver R = 27Ω or R = 50Ω, Figure 1 ● 0.2 V
DifferentialOutput Voltage for
Complementary States
VOC Driver Common-Mode Output Voltage R = 27Ω or R = 50Ω, Figure 1 ● 3 V
∆VOC Change in Magnitude of Driver R = 27Ω or R = 50Ω, Figure 1 ● 0.2 V
Common-Mode Output Voltage
for Complementary States
VIH Input High Voltage DE, DI, RE ● 2 V
VIL Input Low Voltage DE, DI, RE ● 0.8 V
IIN1 Input Current DE, DI, RE ● ±2 µA
IIN2 Input Current (A, B) DE = 0, VCC = 0V VIN = 12V ● ±1 mA
or 5.25V VIN = – 7V ● – 0.8 mA
VTH Differential Input Threshold Voltage – 7V ≤ VCM ≤ 12V ● – 0.2 0.2 V
for Receiver
∆VTH Receiver Input Hysteresis VCM = 0V ● 70 mV
VOH Receiver Output High Voltage IO = – 4mA, VID = 200mV ● 3.5 V
VOL Receiver Outpu Low Voltage IO = 4mA, VID = – 200mV ● 0.4 V
IOZR Three-State (High Impedance) Output VCC = Max, 0.4V ≤ VO ≤ 2.4V ● ±1 µA
Current at Receiver
RIN Receiver Input Resistance – 7V ≤ VCM ≤ 12V ● 12 kΩ
ICC Supply Current No Load, Pins 2, Outputs Enabled ● 500 900 µA
3, 4 = 0V or 5V Outputs Disabled ● 300 500 µA
IOSD1 Driver Short-Circuit Current, VOUT = HIGH VO = – 7V ● 35 100 250 mA
IOSD2 Driver Short-Circuit Current, VOUT = LOW VO = 10V ● 35 100 250 mA
IOSR Receiver Short-Circuit Current 0V ≤ VO ≤ VCC ● 7 85 mA

2
 LTC485
U
SWITCHI G CHARACTERISTICS VCC = 5V ±5%, unless otherwise noted. (Notes 2 and 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tPLH Driver Input to Output RDIFF = 54Ω, CL1 = CL2 = 100pF, ● 10 30 50 ns
tPHL Driver Input to Output (Figures 3 and 5) ● 10 30 50 ns
tSKEW Driver Output to Output ● 5 10 ns
tr, tf Driver Rise or Fall Time ● 3 15 25 ns
tZH Driver Enable to Output High CL = 100pF (Figures 4 and 6) S2 Closed ● 40 70 ns
tZL Driver Enable to Output Low CL = 100pF (Figures 4 and 6) S1 Closed ● 40 70 ns
tLZ Driver Disable Time from Low CL = 15pF (Figures 4 and 6) S1 Closed ● 40 70 ns
tHZ Driver Disable Time from High CL = 15pF (Figures 4 and 6) S2 Closed ● 40 70 ns
tPLH Receiver Input to Output RDIFF = 54Ω, CL1 = CL2 = 100pF, ● 30 90 200 ns
tPHL (Figures 3 and 7) ● 30 90 200 ns
tSKD tPLH – tPHL Differential Receiver Skew ● 13 ns
tZL Receiver Enable to Output Low CRL = 15pF (Figures 2 and 8) S1 Closed ● 20 50 ns
tZH Receiver Enable to Output High CRL = 15pF (Figures 2 and 8) S2 Closed ● 20 50 ns
tLZ Receiver Disable from Low CRL = 15pF (Figures 2 and 8) S1 Closed ● 20 50 ns
tHZ Receiver Disable from High CRL = 15pF (Figures 2 and 8) S2 Closed ● 20 50 ns

The ● denotes specifications which apply over the full operating Note 3: All typicals are given for VCC = 5V and TA = 25°C.
temperature range. Note 4: The LTC485 is guaranteed by design to be functional over a supply
Note 1: Absolute maximum ratings are those beyond which the safety of voltage range of 5V ±10%. Data sheet parameters are guaranteed over the
the device cannot be guaranteed. tested supply voltage range of 5V ±5%.
Note 2: All currents into device pins are positive; all currents out ot device
pins are negative. All voltages are referenced to device ground unless
otherwise specified.

TEST CIRCUITS
A

R TEST POINT S1 1k
RECEIVER VCC
OUTPUT
VOD
CRL 1k
S2
R VOC 15pF

LTC485 • F02
B
LTC485 • F01

Figure 1. Driver DC Test Load Figure 2. Receiver Timing Test Load

3V

DE S1
A
A CL1 VCC
DI RO 500Ω
RDIFF OUTPUT
B UNDER TEST S2
B CL2 RE
CL
15pF

LTC485 • F02

LTC485 • F03

Figure 3. Driver/Receiver Timing Test Circuit Figure 4. Driver Timing Test Load #2

3
LTC485
U W W
SWITCHI G TI E WAVEFOR S
3V
DI 1.5V f = 1MHz, t r ≤ 10ns, t f ≤ 10ns 1.5V
0V
t PLH t PLH 1/2 VO
B
VO
A
1/2 VO tSKEW t SKEW
VO 90%
80% VDIFF = V(A) – V(B)
0V
10% 20%
–VO
LTC485 • F05
tr tf

Figure 5. Driver Propagation Delays

3V
DI 1.5V f = 1MHz, t r ≤ 10ns, t f ≤ 10ns 1.5V
0V
t ZL t LZ
5V
A, B 2.3V OUTPUT NORMALLY LOW 0.5V
VOL

VOH
OUTPUT NORMALLY HIGH 0.5V
A, B 2.3V
0V
t ZH t HZ LTC485 • F06

Figure 6. Driver Enable and Disable Times

VOH
R 1.5V OUTPUT 1.5V
VOL
t PHL f = 1MHz, t r ≤ 10ns, t f ≤ 10ns t PLH
VOD2
A, B 0V INPUT
–VOD2 LTC485 • F07

Figure 7. Receiver Propagation Delays

3V
RE 1.5V f = 1MHz, t r ≤ 10ns, t f ≤ 10ns 1.5V
0V
t ZL t LZ
5V
R 1.5V OUTPUT NORMALLY LOW 0.5V

OUTPUT NORMALLY HIGH 0.5V

R 1.5V
0V
t ZH t HZ LTC485 • F08

Figure 8. Receiver Enable and Disable Times

4
 LTC485
U U U U U
FU CTIO TABLES PI FU CTIO S
LTC485 Transmitting PIN # NAME DESCRIPTION
INPUTS LINE OUTPUTS 1 RO Receiver Output. If the receiver output is enabled
RE DE DI CONDITION B A (RE low), then if A > B by 200mV, RO will be
high. If A < B by 200mV, then RO will be low.
X 1 1 No Fault 0 1
2 RE Receiver Output Enable. A low enables the
X 1 0 No Fault 1 0 receiver output, RO. A high input forces the
X 0 X X Z Z receiver output into a high impedance state.
X 1 X Fault Z Z 3 DE Driver Outputs Enable. A high on DE enables the
driver output. A and B, and the chip will function
as a line driver. A low input will force the driver
LTC485 Receiving outputs into a high impedance state and the chip
INPUTS OUTPUTS will function as a line receiver.
4 DI Driver Input. If the driver outputs are enabled
RE DE A–B R
(DE high), then a low on DI forces the outputs A
0 0 ≥0.2V 1 low and B high. A high on DI with the driver
0 0 ≤ – 0.2V 0 outputs enabled will force A high and B low.
0 0 Inputs Open 1 5 GND Ground Connection.
6 A Driver Output/Receiver Input.
1 0 X Z
7 B Driver Output/Receiver Input.
8 VCC Positive Supply; 4.75 < VCC < 5.25

U W
TYPICAL PERFOR A CE CHARACTERISTICS

Receiver Output Low Voltage Receiver Output High Voltage Receiver Output High Voltage
vs Output Current vs Output Current vs Temperature
36 –18 4.8
TA = 25°C TA = 25°C I = 8mA
32 –16 4.6

28 –14 4.4
OUTPUT CURRENT (mA)

OUTPUT CURRENT (mA)

OUTPUT VOLTAGE (V)

24 –12 4.2

20 –10 4.0

16 –8 3.8

12 –6 3.6

8 –4 3.4

4 –2 3.2

0 0 3.0
0 0.5 1.0 1.5 2.0 5 4 3 2 –50 –25 0 25 50 75 100 125
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) TEMPERATURE (°C)
LTC485 • TPC01 LTC485 • TPC02 LTC485 • TPC03

5
 LTC485
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Receiver Output Low Voltage Driver Differential Output Voltage Driver Differential Output Voltage
vs Temperature vs Output Current vs Temperature
0.9 72 2.4
I = 8mA TA = 25°C RI = 54Ω
0.8 64 2.3

DIFFERENTIAL VOLTAGE (V)

0.7 56 2.2

OUTPUT CURRENT (mA)

OUTPUT VOLTAGE (V)

0.6 48 2.1

0.5 40 2.0

0.4 32 1.9

0.3 24 1.8

0.2 16 1.7

0.1 8 1.6

0 0 1.5
–50 –25 0 25 50 75 100 125 0 1 2 3 4 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) OUTPUT VOLTAGE (V) TEMPERATURE (°C)
LTC485 • TPC03 LTC485 • TPC05 LTC485 • TPC06

Driver Output Low Voltage Driver Output High Voltage TTL Input Threshold
vs Output Current vs Output Current vs Temperature
90 –108 1.64
TA = 25°C TA = 25°C
80 –96 1.63

INPUT THRESHOLD VOLTAGE (V)

70 –84 1.62
OUTPUT CURRENT (mA)

OUTPUT CURRENT (mA)

60 –72 1.61

50 –60 1.60

40 –48 1.59

30 –36 1.58

20 –24 1.57

10 –12 1.56

0 0 1.55
0 1 2 3 4 0 1 2 3 4 –50 –25 0 25 50 75 100 125
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) TEMPERATURE (°C)
LTC485 • TPC07 LTC485 • TPC08 LTC485 • TPC09

Receiver tPLH – tPHL

vs Temperature Driver Skew vs Temperature Supply Current vs Temperature
7.5 5.4 640

7.0 4.8 580

6.5 4.2 520

SUPPLY CURRENT (µA)

DRIVER ENABLED
6.0 3.6 460
TIME (ns)

TIME (ns)

5.5 3.0 400

5.0 2.4 340

DRIVER DISABLED
4.5 1.8 280

4.0 1.2 220

3.5 0.6 160

3.0 0 100
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
LTC485 • TPC10 LTC485 • TPC11 LTC485 • TPC12

6
 LTC485
U U W U
APPLICATIO S I FOR ATIO
Basic Theory of Operation (D1) or the N + /P-substrate diode (D2) respectively will
turn on and clamp the output to the supply. Thus, the
Previous RS485 transceivers have been designed using
output stage is no longer in a high impedance state and is
bipolar technology because the common-mode range of
not able to meet the RS485 common-mode range require-
the device must extend beyond the supplies and the device
ment. In addition, the large amount of current flowing
must be immune to ESD damage and latchup. Unfortu-
through either diode will induce the well known CMOS
nately, the bipolar devices draw a large amount of supply
latchup condition, which could destroy the device.
current, which is unacceptable for the numerous applica-
tions that require low power consumption. The LTC485 is The LTC485 output stage of Figure 9 eliminates these
the first CMOS RS485/RS422 transceiver which features problems by adding two Schottky diodes, SD3 and SD4.
ultra-low power consumption without sacrificing ESD and The Schottky diodes are fabricated by a proprietary modi-
latchup immunity. fication to the standard N-well CMOS process. When the
output stage is operating normally, the Schottky diodes
The LTC485 uses a proprietary driver output stage, which
are forward biased and have a small voltage drop across
allows a common-mode range that extends beyond the
them. When the output is in the high impedance state and
power supplies while virtually eliminating latchup and
is driven above VCC or below ground, the parasitic diodes
providing excellent ESD protection. Figure 9 shows the
D1 or D2 still turn on, but SD3 or SD4 will reverse bias and
LTC485 output stage while Figure 10 shows a conven-
prevent current from flowing into the N-well or the sub-
tional CMOS output stage.
strate. Thus, the high impedance state is maintained even
When the conventional CMOS output stage of Figure 10 with the output voltage beyond the supplies. With no
enters a high impedance state, both the P-channel (P1) minority carrier current flowing into the N-well or sub-
and the N-channel (N1) are turned off. If the output is then strate, latchup is virtually eliminated under power-up or
driven above VCC or below ground, the P + /N-well diode power-down conditions.

VCC
VCC
SD3
P1 P1

D1 D1

OUTPUT
LOGIC LOGIC OUTPUT
SD4

N1 D2 N1 D2

LTC485 • F09 LTC485 • F10

Figure 9. LTC485 Output Stage Figure 10. Conventional CMOS Output Stage

7
LTC485
U U W U
APPLICATIO S I FOR ATIO
The LTC485 output stage will maintain a high impedance Propagation Delay
state until the breakdown of the N-channel or P-channel is Many digital encoding schemes are dependent upon the
reached when going positive or negative respectively. The difference in the propagation delay times of the driver and
output will be clamped to either VCC or ground by a Zener the receiver. Using the test circuit of Figure 13, Figures 11
voltage plus a Schottky diode drop, but this voltage is way and 12 show the typical LTC485 receiver propagation
beyond the RS485 operating range. This clamp protects delay.
the MOS gates from ESD voltages well over 2000V.
Because the ESD injected current in the N-well or substrate The receiver delay times are:
consists of majority carriers, latchup is prevented by tPLH – tPHL = 9ns Typ, VCC = 5V
careful layout techniques.
The driver skew times are:
Skew = 5ns Typ, VCC = 5V
10ns Max, VCC = 5V, TA = – 40°C to 85°C

A A
DRIVER DRIVER
OUTPUTS OUTPUTS

B B

RECEIVER RECEIVER
RO RO
OUTPUT OUTPUT

LTC485 • F11 LTC485 • F12

Figure 11. Receiver tPHL Figure 12. Receiver tPLH

100pF
BR
RECEIVER
TTL IN D R
R OUT
t r, t f < 6ns 100Ω
LTC485 • F13

100pF

Figure 13. Receiver Propagation Delay Test Circuit

8
 LTC485
U U W U
APPLICATIO S I FOR ATIO
LTC485 Line Length vs Data Rate Figures 17 and 18 show that the LTC485 is able to
comfortably drive 4000 feet of wire at 110kHz.
The maximum line length allowable for the RS422/RS485
standard is 4000 feet.
RO
100Ω

A C
TTL COMMON-MODE
LTC485 LTC485
D OUT
VOLTAGE (A + B)/2
B
4000 FT 26AWG
NOISE
TTL TWISTED PAIR
GENERATOR
IN DI

LTC485 • F17

Figure 14. Line Length Test Circuit

Figure 17. System Common-Mode Voltage at 110kHz

Using the test circuit in Figure 14, Figures 15 and 16 show

that with ~ 20VP-P common-mode noise injected on the
line, The LTC485 is able to reconstruct the data stream at RO
the end of 4000 feet of twisted pair wire.
COMMON-MODE
VOLTAGE (A – B)

RO
DI

COMMON-MODE LTC485 • F18

VOLTAGE (A + B)/2
Figure 18. System Differential Voltage at 110kHz
DI

When specifying line length vs maximum data rate the

LTC485 • F15 curve in Figure 19 should be used:
Figure 15. System Common-Mode Voltage at 19.2kHz 10k
CABLE LENGTH (FT)

1k
RO

DIFFERENTIAL 100
VOLTAGE A – B

DI
10
10k 100k 1M 2.5M 10M
MAXIMUM DATA RATE
LTC485 • F16 LTC485 • F19

Figure 16. System Differential Voltage at 19.2kHz Figure 19. Cable Length vs Maximum Data Rate

9
LTC485
U
TYPICAL APPLICATIO S

Typical RS485 Network

Rt Rt

LTC485 • TA03

U
PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted.

J8 Package
8-Lead Ceramic DIP

0.405
(10.287)
0.005 MAX
(0.127)
MIN
8 7 6 5

0.025 0.220 – 0.310

(0.635) (5.588 – 7.874)
RAD TYP

1 2 3 4

0.200
CORNER LEADS OPTION 0.290 – 0.320
(5.080)
(4 PLCS) (7.366 – 8.128) MAX

0.015 – 0.060
0.023 – 0.045 (0.381 – 1.524)
(0.584 – 1.143)
HALF LEAD
OPTION 0.008 – 0.018
0.045 – 0.068 0° – 15°
(0.203 – 0.457)
(1.143 – 1.727)
FULL LEAD
0.385 ± 0.025 0.045 – 0.068
OPTION 0.125
(9.779 ± 0.635) (1.143 – 1.727)
3.175
0.014 – 0.026 0.100 ± 0.010 MIN
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP OR TIN PLATE LEADS. (0.360 – 0.660) (2.540 ± 0.254)

J8 0293

10
 LTC485
U
PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted.

N8 Package
8-Lead Plastic DIP
0.400
(10.160)
MAX

8 7 6 5

0.250 ± 0.010
(6.350 ± 0.254)

1 2 3 4

0.300 – 0.320 0.045 – 0.065 0.130 ± 0.005

(7.620 – 8.128) (1.143 – 1.651) (3.302 ± 0.127)

0.065
(1.651)
0.009 – 0.015 TYP
(0.229 – 0.381) 0.125
(3.175) 0.020
+0.025 0.045 ± 0.015 MIN (0.508)
0.325 –0.015

( )
(1.143 ± 0.381) MIN
+0.635
8.255
–0.381 0.100 ± 0.010 0.018 ± 0.003
(2.540 ± 0.254) (0.457 ± 0.076) N8 0392

S8 Package
8-Lead Plastic SOIC

0.189 – 0.197
(4.801 – 5.004)
8 7 6 5

0.228 – 0.244 0.150 – 0.157

(5.791 – 6.197) (3.810 – 3.988)

1 2 3 4

0.010 – 0.020
× 45° 0.053 – 0.069
(0.254 – 0.508)
(1.346 – 1.752)
0.008 – 0.010 0.004 – 0.010
(0.203 – 0.254) 0°– 8° TYP (0.101 – 0.254)

0.016 – 0.050
0.014 – 0.019 0.050
0.406 – 1.270
(0.355 – 0.483) (1.270)
BSC SO8 0392

11
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC485
U.S. Area Sales Offices

NORTHEAST REGION SOUTHEAST REGION SOUTHWEST REGION

Linear Technology Corporation Linear Technology Corporation Linear Technology Corporation
One Oxford Valley 17060 Dallas Parkway 22141 Ventura Blvd.
2300 E. Lincoln Hwy.,Suite 306 Suite 208 Suite 206
Langhorne, PA 19047 Dallas, TX 75248 Woodland Hills, CA 91364
Phone: (215) 757-8578 Phone: (214) 733-3071 Phone: (818) 703-0835
FAX: (215) 757-5631 FAX: (214) 380-5138 FAX: (818) 703-0517

CENTRAL REGION NORTHWEST REGION

Linear Technology Corporation Linear Technology Corporation Linear Technology Corporation
266 Lowell St., Suite B-8 Chesapeake Square 782 Sycamore Dr.
Wilmington, MA 01887 229 Mitchell Court, Suite A-25 Milpitas, CA 95035
Phone: (508) 658-3881 Addison, IL 60101 Phone: (408) 428-2050
FAX: (508) 658-2701 Phone: (708) 620-6910 FAX: (408) 432-6331
FAX: (708) 620-6977

International Sales Offices

FRANCE KOREA TAIWAN

Linear Technology S.A.R.L. Linear Technology Korea Branch Linear Technology Corporation
Immeuble "Le Quartz" Namsong Building, #505 Rm. 801, No. 46, Sec. 2
58 Chemin de la Justice Itaewon-Dong 260-199 Chung Shan N. Rd.
92290 Chatenay Malabry Yongsan-Ku, Seoul Taipei, Taiwan, R.O.C.
France Korea Phone: 886-2-521-7575
Phone: 33-1-41079555 Phone: 82-2-792-1617 FAX: 886-2-562-2285
FAX: 33-1-46314613 FAX: 82-2-792-1619
UNITED KINGDOM
GERMANY SINGAPORE Linear Technology (UK) Ltd.
Linear Techonolgy GMBH Linear Technology Pte. Ltd. The Coliseum, Riverside Way
Untere Hauptstr. 9 101 Boon Keng Road Camberley, Surrey GU15 3YL
D-85386 Eching #02-15 Kallang Ind. Estates United Kingdom
Germany Singapore 1233 Phone: 44-276-677676
Phone: 49-89-3197410 Phone: 65-293-5322 FAX: 44-276-64851
FAX: 49-89-3194821 FAX: 65-292-0398

JAPAN
Linear Technology KK
5F YZ Bldg.
Iidabashi, Chiyoda-Ku
Tokyo, 102 Japan
Phone: 81-3-3237-7891
FAX: 81-3-3237-8010

World Headquarters

Linear Technology Corporation

1630 McCarthy Blvd.
Milpitas, CA 95035-7487
Phone: (408) 432-1900
FAX: (408) 434-0507

06/24/93

LT/GP 0294 5K REV E • PRINTED IN THE USA

Linear Technology Corporation
12 1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977  LINEAR TECHNOLOGY CORPORATION 1994