NPCA110B-Nuvoton Technology

Nuvoton Confidential
NPCA110B Audio Enhancing Engine and CODEC

February 2012
Revision 1.1

General Description Outstanding Features
The Nuvoton NPCA110B device is a member of Nuvoton’s ■ Improves audio quality for low-performance speakers
Sound Enhancing family optimized for low cost TV, portable ■ System-level BOM savings
devices such as docking stations for MP3-players and mobile ■ Stereo operation
phones, Multi-Media speakers, PC monitor speakers and ■ I2C controlled
Boom boxes.
■ 24-bit accuracy
The NPCA110B integrates Waves MaxxAudio-3 Lite ■ Audio algorithms
sound enhancement algorithms. These are proprietary,
patented, psychoacoustic algorithms that compensate for — MAXXBASS ®
the acoustic limitations of small CE devices.

MaxxAudio-3 Lite algorithms enable reproduction of rich — MAXXEQ
content, with a wide dynamic range and a full frequency
range, on a limited audio system. For low-frequency ®
— MAXXVOLUME
reproduction, MaxxBass uses a patented psychoacoustic
technique to create a perceived low bass, which can be ■ Audio input
extended up to 1.5 octaves lower than the original. This
— One I2S or Synchronous Serial Interface (SSI) input
technique reproduces full and rich sounding bass tones.
Power handling is done by MaxxVolume, which utilizes the — Up to two stereo analog inputs: typical SNR of
power amplifiers and speakers to their full extent yet avoids 90 dB; typical THD of 75 dB
clipping and distortion. ■ Audio output
The MaxxAudio-3 Lite software suite provides an additional — One I2S or SSI output
algorithm to design a resonance-free audio system: Maxx- — Two analog outputs: typical SNR of 96 dB; typical
EQ provides a flexible equalizer with 10 bands. THD of 86 dB
The NPCA110B enables digital control over the volume and ■ Several General-Purpose digital signals available to
bass, replacing traditional analog potentiometers. the application (GPIOs)
The Maxx family of devices includes: ■ Typical operational power target of less than 0.15W
■ High-performance, 24-bit audio enhancing engine pre- ■ Power-down target of less than 0.5 mW
programmed with Waves MaxxAudio-3 Lite algorithms ■ 3.3V operation
■ Optional Audio ADC
■ Optional Audio DAC
■ Digital I/O and other features for high-performance
audio systems
The MaxxAudio Graphical User Interface (GUI) enables
sound engineers to easily tune the device and customize
presettings for different audio products.
System Block Diagram Speakers

I2S
R
Analog Audio Power
MP3 Player Analog Amplifiers L
Analog Audio
FM Radio
I2C (Optional) NPCA110B
Controller Analog Audio
Headphones
SPDIF Rx
I2S AMP
or
TV Chipset GPIOs
© 2012 Nuvoton Technology Corporation www.nuvoton.com

NPCA110B
Features
Bus Interfaces ■ MaxxVolume
■ Synchronous Serial Interface (SSI) — MaxxVolume is an all-in-one volume control, with
High-Level Compression to increase RMS levels,
— Compatible with I2S Low-Level Compression to increase the clarity of
— Master and slave timing support soft sounds, Noise Gating to eliminate signal and
■ I2C Interface system noise, and Leveling to smooth out volume
levels.
— Compliant with I2C-BUS Specification Revision 1.0,
1992
Straps, Clocks, Supply and Package Information
— Master or slave interface
■ Strap Input Controlled Operating Modes
— Supports 7-bit address mode
— PLL reference clock select (REF strap)
Audio Enhancing Engine — Test mode select (nTEST strap)
■ Processing Unit — I2C master or slave select (I2CMS strap)
— 24-bit accuracy — Boot options
— 90 MIPs ❏ ROM code operation
❏ Loadable algorithms for new functions or ROM
Audio Algorithms code patching
■ Sample frequency of 44.1 KHz or 48 KHz supported ■ Input Clocks
■ MaxxBass — SSI / I2S clock: 64 x sample frequency
— Patented Waves MaxxBass psycho-acoustic bass — Optional crystal oscillator or input clock
extension delivers a more natural sound than tradi-
■ Power Supply
tional bass boost technologies, which use EQ and
can overpower your system. MaxxBass analyzes — 3.3V supply operation
low frequencies to create harmonics that are per- ■ Power-Save Modes
ceived as lower, deeper tones. — Clock switch to a lower frequency
■ MaxxEQ — WAIT state (clock stopped)
— MaxxEQ provides the ability to design EQ curves — PLL power-down
and shape sound with surgical precision, using up to
10 programmable filters with bell, shelf, low pass, ■ Package
and high pass, plus adjustable frequency, gain, and — 5 x 5 mm, 32-pin Quad Flat No-Lead (QFN) package
Q parameters. MaxxEQ’s intuitive Graphic User In-
terface makes click-and-drag filter design fast and
easy.
Algorithm Processing Chain
Maxx Maxx Maxx

Bass EQ Volume
www.nuvoton.com 2 Revision 1.1

Revision 1.1
Features
(Continued)
One I2S
input Mx =
-inf .. 18 dB Mx =
-inf .. 0 dB
I2S SDI0
M1 Stereo Out
M9
Audio Engine
2x Analog + Processing Path +
inputs One I2S
output
L/RIN1 M12
SDO0
I2S
AG ADC GAIN M4
L/RIN2
-18dB .. 34dB -96dB .. 30dB
M5
3
Bypass
+
M17
L/ROUT2
+ GAIN DAC2
M8
M16 -126dB .. 0dB
Note: All paths in the diagram are stereo
Figure 1. Device Block Diagram
www.nuvoton.com
NPCA110B
NPCA110T
Revision Record
Date Status Comments
February 2011 Revision 0.10 Datasheet first revision.

June 2011 Revision 0.75 Changes:
• Added algorithm processing Chain diagram
• Added block diagram
• Added Clocks section in Chapter 2
• Added current consumption in Electrical Specification
• Various small changes
August 2011 Revision 0.80 Changes:
• Pins: Corrected that SDA and SCL are OD6 pins
• Power and Reset:
— Removed TBD from crystal circuit
— Added Clocks section
• Electrical Specifications:
— Changed input type ST VIH level to minimum 2.0 V, VH to 280 mV
— Section 4.2.5: Changed maximum leakage of all pins from <30 A to <10 A
— Changed pull-up resistor minimum value to 34 K
— Removed DAC current consumption in Analog section
— In DAC Characteristics, for LRCT, changed values to -67 (typical) and -64 (max)
— Added that CLKOUT duty cycle is characterized only
— Changed I2C timing AC levels to 0.8 and 2.0V
— I2C Slave: removed tHD:DS from spec; changed tHD:DAT minimum to 18 ns
— SSI slave: Changed tHR minimum to 2 ns
November 2011 Revision 1.0 Changes:
• Changed device description
• Changed package marking
February 2011 Revision 1.1 Changes:
• Fixed typo: “I2CMS” signal is “I2C Master/Slave Strap” (not I2S).

NPCA110B
Table of Contents
General Description ............................................................................................................................................ 1
Features.............................................................................................................................................................. 2
Revision Record ................................................................................................................................................ 4
1.0 Signal/Pin Description

1.1 CONNECTION DIAGRAM ............................................................................................................. 7
1.2 PIN TYPES ..................................................................................................................................... 8
1.3 PIN DESCRIPTION ........................................................................................................................ 8
1.3.1 Clocks and Reset .............................................................................................................. 8
1.3.2 GPIO ................................................................................................................................ 8
1.3.3 I2S / GPIO / STRAPS ....................................................................................................... 9
1.3.4 I2C / GPIO ........................................................................................................................ 9
1.3.5 CODEC ........................................................................................................................... 10
1.3.6 Power .............................................................................................................................. 10
2.0 Power, Clocks and Reset

2.1 POWER ........................................................................................................................................ 11
2.1.1 Power Planes .................................................................................................................. 11
2.1.2 Power States ................................................................................................................... 11
Illegal Power States ......................................................................................................... 11
2.1.3 Power Connection and Layout Guidelines ...................................................................... 11
Ground Connection ......................................................................................................... 11
Power Connection ........................................................................................................... 12
2.2 CLOCKS ....................................................................................................................................... 15
2.3 RESET SOURCES AND TYPES ................................................................................................. 16
2.3.1 Power-Up Reset .............................................................................................................. 16
2.3.2 Watchdog Reset .............................................................................................................. 16
3.0 Device Specifications

3.1 GENERAL DC ELECTRICAL CHARACTERISTICS .................................................................... 17
3.1.1 Recommended Operating Conditions ............................................................................. 17
3.1.2 Absolute Maximum Ratings ............................................................................................. 17
3.1.3 Capacitance ................................................................................................................... 17
3.1.4 Power Supply Current Consumption under Recommended Operating Conditions ......... 18
3.2 DC CHARACTERISTICS OF PINS BY I/O BUFFER TYPES ...................................................... 18
3.2.1 Input, TTL Compatible ..................................................................................................... 18
3.2.2 Input, TTL Compatible, with Schmitt Trigger ................................................................... 18
3.2.3 Output, TTL/CMOS-Compatible, Push-Pull Buffer .......................................................... 19
3.2.4 Output, TTL/CMOS-Compatible, Open-Drain Buffer ....................................................... 19
3.2.5 Notes and Exceptions ..................................................................................................... 19
3.2.6 Terminology ..................................................................................................................... 19
3.3 INTERNAL RESISTORS .............................................................................................................. 20
3.3.1 Pull-Up Resistors ............................................................................................................. 20
Revision 1.1 5 www.nuvoton.com

NPCA110B
Table of Contents (Continued)
3.4 ANALOG CHARACTERISTICS ................................................................................................... 21

3.4.1 ADC Characteristics ....................................................................................................... 21
3.4.2 DAC Characteristics ....................................................................................................... 21
3.5 AC ELECTRICAL CHARACTERISTICS ...................................................................................... 22
3.5.1 AC Test Conditions ........................................................................................................ 22
3.5.2 Reset Timing ................................................................................................................... 23
3.5.3 Clock Timing .................................................................................................................... 24
3.5.4 Input Signals Detection Timing ........................................................................................ 25
3.5.5 I2C Slave Timing ............................................................................................................. 25
3.5.6 I2C Master Timing ........................................................................................................... 26
3.5.7 SSI Timing ....................................................................................................................... 27
3.6 PACKAGE THERMAL INFORMATION ....................................................................................... 28
Physical Dimensions......................................................................................................................................... 29

NPCA110B
1.0 Signal/Pin Description
1.1 CONNECTION DIAGRAM
GPO07/CLKOUT/REF
GPO06/SDO0/nTEST
GPIO01/SYNC
GPIO00/DCLK
GPO17
Pin 1 Indication
VDD
SDA
SCL
32 31 30 29 28 27 26 25
GPO18/I2CMS 1 24 nRESET
VDD 2 23 VDD
VSS 3 22 VD18
RIN1 4 21 VSSP
NPCA110B
LIN1 5 20 VPLL18
RIN2 6 19 XTALO
LIN2 7 18 XTALI/CLKIN
LOUT2 8 17 GPIO20/SDI0
9 10 11 12 13 14 15 16
AGND
AVDD
VDD
VCM
VSS
DAC_REF
ADC_REF
ROUT2
Note: Bottom Pad is VSS.
32-Pin Quad Flat No-Lead (QFN) Package

Order Number: NPCA110BA0YX

NPCA110B
1.0 Signal/Pin Description (Continued)
1.2 PIN TYPES

Table 1. Abbreviations
Abbreviations Description
GPIO General-Purpose I/O

GPO General-Purpose Output
Ox/y Output, Source x mA, Sink y mA
ODy Output, Open-Drain, Sink y mA
5V Input tolerant to 5 volts
PU Input buffer with a pull-up resistor. This pull-up resistor is intended to maintain unconnected input
pins at high logic level. The voltage measured externally on an unconnected input pin is in the
range of 1.5 to 2.5V, although the input itself is near VDD level.
T Input buffer with CMOS / LVTTL levels

ST Schmitt trigger input buffer with CMOS / LVTTL levels
A Analog input or output
XO Crystal Oscillator
1.3 PIN DESCRIPTION
1.3.1 Clocks and Reset

Note: Crystal oscillator connections are found in Figure 4 on page 13.
Pull-
Power Buffer
Signal I/O Description Up / Comments
Well Type
Down
XTALI/CLKIN I Crystal Clock Input. Used for a crystal VDD XO

connection circuit or as a clock input
(clock input at LVTTL levels). The crystal
should have a frequency of 12.288 MHz
(48 KHz sample rate) or 11.2896 MHz
(44.1 KHz sample rate).
XTALO O Crystal Clock Output. Used for a crystal

connection circuit.
nRESET I Power-Up Reset Input. If driven low, PU VDD 5V, ST

forces reset.
1.3.2 GPIO
Pull-
Power Buffer
Well Type
Down
GPO17 O General-Purpose Output Signal 17. PU VDD T, 5V, O8/8
GPIO20 / I/O General-Purpose I/O Signal 20. / PU VDD T, 5V, O2/2

SDI0 I I2S Serial Data In 0. Carries input stereo
data stream 0.

NPCA110B
1.3.3 I2S / GPIO / STRAPS
Pull-
Power Buffer
Well Type
Down
GPIO00 / I/O General-Purpose I/O Signal 00. / PU VDD T,5V,O2/2

DCLK I/O I2S Clock. Input for an I2S slave and output
for an I2S master. The frequency must be
either 32 or 64 times the sample frequency.
When used as output, a 33 to 100 series
resistor is required.
GPIO01 / I/O General-Purpose I/O Signal 01. / PU VDD T,5V,O2/2

SYNC I/O I2S SYNC. Input for an I2S slave and output
for an I2S master. Indicates the sample
frequency. When used as output, a 33 to
100 series resistor is required.
GPO06 / O General-Purpose Output Signal 06. / PU VDD T,5V,O2/2

SDO0 / O I2S Serial Data Out 0. Carries output stereo
data stream 0. A 33 to 100 series resistor
is required. /
nTEST I Test Strap. Sampled during Power-Up reset.
The pin is pulled up by an internal resistor for
normal operation or set to 0 by an external
8.2 K pull-down resistor.

CLKOUT / O General-Purpose Clock Output. A 33 to
100 series resistor is required. /
REF I Reference Strap. Sampled during Power-Up.
The pin is pulled up by an internal resistor
(selects DCLK in) or set to 0 by an external
8.2 K pull-down resistor (selects crystal
oscillator).

I2CMS I I2C Master/Slave Strap. Sampled during
Power-Up reset. The pin is pulled up by an
internal resistor (selects slave) or set to 0 by
an external 8.2 K pull-down resistor (selects
master).
1.3.4 I2C / GPIO
Pull-
Power Buffer
Well Type
Down
SDA I/O Master/Slave I2C Data Line. VDD ST,5V,OD6
SCL I/O Master/Slave I2C Clock Line. When used VDD ST,5V,OD6
as an input, ignores short pulses of a length
of less than 5 ns and rejects more signal
changes within 20 ns (reducing signal
reflections hazards).

NPCA110B
1.3.5 CODEC
Note: Codec power connections are found in Figure 5 on page 14
Power Buffer
Signal I/O Description
Well Type
LIN1, RIN1 A Analog-to-Digital Converter Input Pair 1. Left Input and Right Input AVDD analog
are analog inputs and require AC coupling with a 1 F capacitor
(0.33 F capacitor if 30 K input impedance is selected).
LIN2, RIN2 A Analog-to-Digital Converter Input Pair 2. Left Input and Right Input AVDD analog
are analog inputs and require AC coupling with a 1 F capacitor
(0.33 F capacitor if 30 K input impedance is selected).
LOUT2 A Digital-to-Analog Converter Left Output. Left Output is an analog AVDD analog
output of DAC2.
ROUT2 A Digital-to-Analog Converter Right Output. Right Output is an analog AVDD analog
output of DAC2.
VCM P CODEC Internally Generated Common-Mode Voltage. Should be AVDD analog

connected via a 0.1 F ceramic capacitor, parallel with a
tantalum/Ceramic 22 F capacitor, to AVSS.
ADC_REF P CODEC Internally Generated ADC Reference Voltage. Should be AVDD analog
tantalum/Ceramic 22 F capacitor to AVSS.
DAC_REF P CODEC Internally Generated DAC Reference Voltage. Should be AVDD analog
tantalum/Ceramic 22 F capacitor, to AVSS.
AVDD P CODEC Analog 3.3V Supply. Should be connected to a filtered supply.

Bypass capacitors of 0.1 F (ceramic) and 22 F should be connected
to AVSS. A 20 series resistor to VDD may be used as the filter.
AVSS G CODEC Analog Ground. Should be connected to ground. The user

may use a separate analog ground plane, connected to the digital
(main) ground plane at one point near the NPCA110B.
1.3.6 Power
Note: Power connections are found in Figure 2 on page 12 and Figure 3 on page 13.
Signal I/O Description
VSSP G PLL Ground. Should be connected to a digital ground plane via a 0 resistor.
VPLL18 P PLL 1.8V Supply. Internally generated for PLL. Should be connected via a 4.7 F ceramic
capacitor to VSSP.
VD18 P Internal 1.8V Supply. Internally generated for internal logic. Should be connected via a 4.7 F
ceramic capacitor to digital ground.
VSS G Digital Ground. Should be connected to a digital ground plane. The QFN32 package bottom pad
must be connected to digital ground.
VDD P 3.3V Digital Supply.

NPCA110B
2.0 Power, Clocks and Reset
2.1 POWER
2.1.1 Power Planes
The NPCA110B has three power plane groups (wells), as shown in Table 2.
Table 2. NPCA110B Power Planes
Power Plane Power Plane

Description Power Pins Ground Pins
Group Notation
Internal group Powers the internal PLL. Supply is generated internally, but VD18 VPLL18 VSSP
requires filtering.
Powers the internal logic of all the device modules. Supply VD18 VD18 VSS
is generated internally but requires filtering.
Active group 3.3V power to the I/O interface and internal regulators. VDD VDD VSS
Analog Active Powers the CODEC; requires filtering AVDD AVDD AGND
For correct NPCA110B operation, AVDD must be applied at the same time that VDD is applied. Protection is provided only
against rise-time differences between the different power planes.
2.1.2 Power States

The NPCA110B has the following main power states:
• Power Fail
All power planes are powered off; (i.e., VDD, AVDD are inactive).
• Power Active
All power planes are powered on (i.e., VDD, AVDD are active).
Illegal Power States

The following power states are illegal (i.e., NPCA110B operation is not guaranteed):
• Active power plane on and analog power plane off.
• Active power plane off and analog power plane on.
2.1.3 Power Connection and Layout Guidelines

The NPCA110B requires a power supply voltage of 3.13V3.47V for the digital supplies (VDD) and 3.00V3.47V for the an-
alog power supply (AVDD).
VDD uses a common ground return named Digital Ground and marked VSS. The analog circuits use a separate ground re-
turn. This ensures effective isolation of the analog modules from noise caused by the digital modules.
The following directives are recommended for the NPCA110B power and ground connections.
Ground Connection
Use two ground planes, one for digital signals (VSS) and one or more for analog signals (AVSS). Make the following ground
connections:
• Connect a specific analog ground plane (AVSS) to the digital ground plane (VSS) at one point only. This point should
be physically located near the relevant NPCA110B analog supply pin, AVDD.
• Connect the analog ground return pin (AGND) of the NPCA110B to the analog ground plane.
• Connect the decoupling capacitors of the analog supply (AVDD) to the analog ground plane, as close as possible to
the AGND pin.
• Connect all VSS pins and the bottom pad of the NPCA110B to the GND plane.
• Locate the decoupling capacitors of the Active power plane’s digital supply (VDD) pins close to a VDD pin; connect
one terminal of each capacitor to the ground plane.
• If there is insufficient room for decoupling capacitors, place smaller capacitors close to the power-ground pins and
larger capacitors further away.
Note that low-impedance ground layers improve noise isolation and reduce ground bounce problems.

NPCA110B
2.0 Power, Clocks and Reset (Continued)
Power Connection
All NPCA110B supply pins must be connected to the appropriate power plane. Decoupling capacitors must be used as rec-
ommended as follows:
• Connect the digital supply pins (VDD) to a 3.3V power supply. A 10 F (or larger) capacitor should be connected be-
tween VDD and the digital ground plane. A 0.1F capacitor should be connected to ground near each VDD pin of the
device.
• Connect the analog supply pins (AVDD) to a low-noise, 3.3V power supply. If the AVDD pin is connected to the same
power supply as the VDD pins, it is recommended to use an external L-C or R-C filter for the AVDD pin.
The recommend power connections are shown below:
NPCA110B
VDD 3.3V
+
C1 C5
VDD
Legend:
C2 Part Designator Value
C1, C2, C3, C4 0.1 F Ceramic
C5 10 F (for linear regulator),
VDD 22 F (for switching regulator)
C3
VDD
C4
VSS
Figure 2. 3.3V Digital Power Connection Diagram

NPCA110B
NPCA110B
VD18 Legend:
Part Designator Value
C1 R1 0
C1, C2 4.7 F Ceramic
VPLL18
C2
VSSP
R1
Figure 3. 1.8V Power Connection Diagram
Legend:
NPCA110B Part Designator Final Values
R1 2 M5%,
C1 C1 20 pF Ceramic 5%,
XTALI/CLKIN C2 20 pF Ceramic 5%
Option 1:
R2 2000 1%,
R1 X1 X1 12.288 or 11.2896 MHz,
CL=12 pF, ESR < 75
Drive level up to 500 W
XTALO
Option 2:
R2 C2
R2 4990 1%,
X1 12.288 or 11.2896 MHz,
CL=12 pF, ESR < 75
Drive level up to 100 W
Figure 4. Typical Crystal Oscillator Connection Diagram

NPCA110B
VDD = 3.3V Legend:

NPCA110B Part Designator Value
R1 20, 5%
R1 C1, C3, C5 0.1 F
C2, C4, C6 22 F, Tantalum/Ceramic
C7 0.1 F
AVDD C8 22 F, Tantalum/Ceramic
+
C1 C2
AGND
Analog Ground “Plane”
Single point connection

VCM to digital Ground
+
C3 C4
DAC_REF
+
C5 C6
ADC_REF
+
C7 C8
Figure 5. Recommended CODEC Power Connection Diagram

NPCA110B
2.2 CLOCKS
The NPCA110B clock structure is shown below. The clock generation parameters are supplied to the device at initialization.
REF
Strap
I2S DCLK
1
Glitch
2
Free
PLL 1 Processor
1 Glitch System and System
Oscillator / CLKIN Free Clock Clock
0 0
Divider
(1 to 32)
0
1
Glitch CLKOUT CLKOUT Clock
Free Clock
Divider Nominally
0
(1 to 32) 256 x Fs
1
Glitch
CODEC
Clock CODEC Clock
Free
Divider
Nominally
(1 to 32) 256 x Fs
0
SSI Clock SSI Clock

Divider
(4 or 8) (64 or 32) x Fs
Figure 6. Clocks in the NPCA110B
Clock Source
The clock source is either DCLK (I2S serial clock, in slave mode) or the crystal oscillator, and is used as the reference clock
of the PLL. The clock is selected initially by the REF strap and may be changed later.
When DCLK is a stable clock, the oscillator may be omitted. The oscillator may be replaced by a clock input.
The best selection for a crystal frequency is 256 times the sample clock used.
PLL
The PLL is used to generate the Processor and the CODEC clock (if the oscillator is omitted) and can be used to generate
the SSI (I2S) clock as well (if the device is in I2S master mode).
The PLL reference clock may be as low as 44 KHz; however, for low jitter, a higher frequency reference clock is recommended.

NPCA110B
2.3 RESET SOURCES AND TYPES

The NPCA110B has one reset domain.
Reset Types
• Power-Up reset - Activated when nReset signal is asserted (when the VDD and VD18 supplies are powered up).
• Watchdog reset - Activated when a watchdog condition is detected.
The following sections describe the sources and effects of the various resets on the NPCA110B, per reset type.
2.3.1 Power-Up Reset

VDD Power-Up reset is generated when nRESET signal is asserted.
On Power-Up reset, the NPCA110B performs the following:
• Puts pins with strap options into TRI-STATE mode and enables the internal pull-up/down resistors on the strap pins.
• Samples the values of the strap pins (after nRESET deassertion).
• Performs all actions done by a Watchdog reset.
Note: The internal reset signal is active for at least 3 ms.
2.3.2 Watchdog Reset

Watchdog reset is generated by the Watchdog module on detection of a watchdog event.
The NPCA110B loads default values to all registers.

NPCA110B
3.0 Device Specifications
3.1 GENERAL DC ELECTRICAL CHARACTERISTICS

3.1.1 Recommended Operating Conditions
Symbol Parameter1 Min Typ Max Unit
VDD 3.3V Supply Voltage (VDD pins) 3.13 3.3 3.47 V

AVDD 3.3V Analog Supply Voltage (AVDD pin) 3.00 3.3 3.47 V
VOFF VDD and AVDD Power Off Voltage 0.3 0 +0.5 V
TA Operating Ambient Temperature 0 +70 C
1. Unless otherwise specified, all voltages are relative to ground.
3.1.2 Absolute Maximum Ratings

Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all volt-
ages are relative to ground. These parameters are characterized and not fully tested.
Symbol Parameter Conditions Min Max Unit
VDD 3.3V Supply Voltage, including AVDD1 0.5 3.6 V

All buffer types (except analog) 0.5 VDD + 0.5 V
VI Input Voltage1 5V buffer types 0.5 5.5 V
VDD < 0.5V, all digital signals 0.5 3.47 V
VO Output Voltage1 All buffer types (except analog) 0.5 VDD + 0.5 V
ISINK Total NPCA110B Sink or Source Total of all output pins

50 mA
Current
ESD Tolerance CZAP = 100 pF, RZAP = 1.5 K2 2000 V
TSTG Storage Temperature 65 +150 C

TBIAS Ambient Temperature Under Bias 0 +70 C
PD Power Dissipation For correct operation 0.5 W
1. All voltages are relative to ground.
2. Value based on test complying with RAI-5-048-RA human body model ESD testing.
3.1.3 Capacitance
Symbol Parameter Conditions Min1 Typ2 Max1 Unit
CIO I/O Pin Capacitance All pins 8 12 pF
1. Not fully tested; characterized only.

2. TA = 25C; f = 1 MHz.

NPCA110B
3.0 Device Specifications (Continued)
3.1.4 Power Supply Current Consumption under Recommended Operating Conditions

These table values are preliminary:
Power
Symbol Parameter
Mode Conditions1 Typ2 Max2 Unit
Active VIL = 0.5V, VIH = 2.4V,

IDD VDD Average3 Supply Current (including
DAC load = 10 K 55 704 mA
ADC, DACs) Processor clock is 125 MHz
IDD VDD Stop5 Supply Current Idle 0.7 mA
IADC ADC Average current Active 4 6 mA

IDAC Each DAC Average current (RL = 10 K) Active 2.5 5 mA
1. Unless stated otherwise, all parameters are specified for 0C  TA  70C, V33 = 3.13V - 3.47V and no resistive
load on outputs.
3. Average current is used for power calculation.
4. Resistive loads (such as I2C) on outputs may increase this current, especially if the LEDs are driven directly
from the device.
5. Stop is defined as: Processor and system clock is halted, PLL is in power-down (Reference clock selected as clock,
PLLPD bit set, crystal oscillator disabled).
3.2 DC CHARACTERISTICS OF PINS BY I/O BUFFER TYPES

The tables in this section summarize the DC characteristics of all device pins described in (Section 1.3 on page 8). The char-
acteristics describe the I/O buffer types defined in Section 1.2 on page 8. For exceptions, see Section 3.2.5 on page 19.
3.2.1 Input, TTL Compatible

Symbol: T
Non-5V types 2.0 VDD+0.5 V

VIH Input High Voltage
5V types 2.0 5.5 V
VIL Input Low Voltage 0.5 0.8 V
IILK1 Input Leakage Current VDD = 3.13V  3.47V and 0 < VIN < VDD 2 A
1. For additional conditions, see Section 3.2.5 on page 19.
3.2.2 Input, TTL Compatible, with Schmitt Trigger

Symbol: ST
Non-5V types 2.0 VDD+0.5 V

VIH Input High Voltage
5V types 2.0 5.5 V
VIL Input Low Voltage 0.5 0.8 V
VH Input Hysteresis 2801 mV
IILK2 Input Leakage Current VDD = 3.13V  3.47V and 0 < VIN < VDD 2 A
1. Not tested; guaranteed by characterization guardband.


NPCA110B
3.2.3 Output, TTL/CMOS-Compatible, Push-Pull Buffer

Symbol: Op/n
Output, TTL/CMOS-compatible, rail-to-rail push-pull buffer that is capable of sourcing p mA and sinking n mA.
IOH = p mA 2.4 V
VOH Output High Voltage
IOH = 50 A VDD 0.2 V
IOL = n mA 0.4 V
VOL Output Low Voltage
IOL = 50 A 0.2 V
IOLK1 Output Leakage Current VDD = 3.13V  3.47V and 0 < VIN < VDD 2 A
3.2.4 Output, TTL/CMOS-Compatible, Open-Drain Buffer

Symbol: ODn
Output, TTL/CMOS-compatible open-drain output buffer capable of sinking n mA. Output from these signals is open-
drain and is never forced high.
IOL = n mA 0.4 V
VOL Output Low Voltage
IOL = 50 A 0.2 V
IOLK1 Output Leakage Current VDD = 3.13V  3.47V and 0 < VIN < VDD 2 A
3.2.5 Notes and Exceptions

1. IILK and IOLK are measured in the following cases (where applicable):
— Internal pull-up or pull-down resistor is disabled
— Push-pull output buffer is disabled (TRI-STATE mode)
— Open-drain output buffer is at high level
2. Pins marked with ‘5V’ in the Buffer Type column in Section 1.3 on page 8 are 5V tolerant.
The analog type pins, are not 5V tolerant. This applies if these buffer types are stand-alone or if they are multiplexed with
5V tolerant buffer types.
3. Maximum leakage of all the NPCA110B pins together is <10 A when input voltage is within the supply rails voltage and
when PU resistors are disabled in Hi-Z (not fully tested; characterized only).
4. A pin (nRESET) that has an internal static pull-up resistor therefore has leakage current from VDD (when VIN = 0).
5. Strap pins have an internal pull-up resistor enabled during Power-Up reset and therefore may have leakage current from
VDD (when VIN = 0).
6. IOH is valid for a GPIO pin only when it is not configured as open-drain.
7. All digital pins of output type Op/n have a back-drive protection capability of up to 3.6V.
3.2.6 Terminology
Back-Drive Protection. Back-drive protected pins sustain any voltage within the specified voltage limits when the device
power supply is off.
5-Volt Tolerance. 5V tolerant pins sustain 5V even if the applied voltage is above the device power supply voltage. A pin is
5V tolerant in the following conditions (where applicable):
● Internal pull-down resistor is disabled. If it is enabled, leakage current is high.
● Push-pull output buffer is disabled (TRI-STATE mode)

NPCA110B
3.3 INTERNAL RESISTORS

DC Test Conditions
Pull-Up Resistor Test Circuit

VSUP
Device
Under RPU IPU
Test Pin
A
V
VPIN
Figure 7. Internal Resistor Test Conditions, TA = 0C to 70C
Internal Pull-Up Strap

VSUP VSUP
Strap Sampled “High” Strap Sampled “Low” VSUP
(VPIN > VIH) (VPIN < VIL)
Device Device 10 A
Under RPU IPU Under IPU
RPU
Test Pin Test Pin
A A
V V
VPIN 10 A VPIN 10 K
Figure 8. Internal Resistor Design Requirements, TA = 0C to 70C
Notes:
1. The equivalent resistance of the pull-up resistor is calculated by RPU = (VSUP  VPIN) / IPU.
2. The equivalent resistance of the pull-down resistor is calculated by RPD = VPIN / IPD.
3.3.1 Pull-Up Resistors

Symbol: PU
Symbol Parameter Conditions1 Min2 Typical Max2 Unit
RPU Pull-Up Equivalent Resistance VPIN = 0V 34 60 95 K

for other pins
1. TA = 0C to 70C, VSUP = 3.3V 5%.

NPCA110B
3.4 ANALOG CHARACTERISTICS

3.4.1 ADC Characteristics
Parameter Symbol Conditions1 Min Typ Max Unit
Resolution RES 24 Bit

Selecting 10 K, AC coupled 10 25 K
Input Impedance2 ZIN
Selecting 30 K, AC coupled 30 75 K
Input Capacitance3 CAIN 20 pF

Dynamic Range DR 80 90 dB
Signal-to-Noise Ratio SNR 80 90 dB
At -9 dB of Full-Scale @1 KHz,
Total Harmonic Distortion THD AVDD= 3.13  3.47V -754 -70 dB
Total Harmonic Distortion THD At -9 dB of Full-Scale @1 KHz3 -75 dB
Full Scale Voltage VFS AVDD/3.3 VRMS
Left and Right Channel Mismatch LRMM 0.1 0.3 dB

Analog Multiplexer DC Offset MOFS 15 mV
Analog Multiplexer Gain Mismatch MGM 0.5 dB
Overall Passband Ripple OPR 0.5 dB
1. All parameters specified for 0C  TA  70C and AVDD= 3.00V  3.47V and using the calibration data, unless
otherwise specified.
2. Defined when ADC Programmable Gain Amplifier (PGA) Volume control is set to 0 dB.
When set to 10 K: Minimum ZIN at highest PGA gain is 1 K.
When set to 30 K: Minimum ZIN at highest PGA gain is 2 K.
4. Typical value is specified for TA = 25C and AV33= 3.30V.
3.4.2 DAC Characteristics
Parameter Symbol Conditions1 Min Typ Max Unit
Resolution RES 24 Bit

Output Load Resistance ZL AC coupled 0.6 10 K
Output Capacitance2 CAOUT AC coupled 30 1000 pF

Dynamic Range DR 90 96 dB
Signal-to-Noise Ratio SNR 90 96 dB
At -1 dB of Full-Scale
Total Harmonic Distortion THD -86 -76 dB
@1 KHz input
Full-Scale Voltage VFS AVDD/3.3 VRMS
Left and Right Channel Mismatch LRMMO 0.1 0.3 dB

Left and Right Channel Crosstalk LRCT -67 -64 dB
1. All parameters specified for 0C  TA  70C and AV33= 3.00V  3.47V and using the calibration data, unless
otherwise specified.

NPCA110B
3.5 AC ELECTRICAL CHARACTERISTICS

3.5.1 AC Test Conditions
Load Circuit VSUP
(Notes 1, 2, 3) S1 AC Testing Input, Output Waveform
0.1 F VOH
VIH VIH
RL Test Points
VIL VIL
Device VOL
Input Under Output
Test
CL
Figure 9. AC Test Conditions, TA = 0C to 70C, VSUP = 3.13V - 3.47V

Notes:
1. VSUP is V33 according to the power well of the pin, relevant for all signals at LVTTL levels.
2. CL = 50 pF for all output pins except the following pin groups (values include both jig and oscilloscope capacitance)
CL = 100 pF for I2C
CL = as otherwise defined
3. S1 = Open  for push-pull output pins
S1 = VSUP  for high-impedance to active low and active low to high-impedance transition measurements
S1 = GND  for high-impedance to active high and active high to high-impedance transition measurements
RL = 1.0 K  for all pins
4. The following abbreviations are used in Section 3.5: RE = Rising Edge; FE = Falling Edge.
Definitions
The timing specifications in this section are relative to VIL or VIH (according to the specific buffer type) on the rising or falling
edges of all the signals, as shown in the following figures (unless specifically stated otherwise).
VIH
Clock
VIL
Input Setup Time tSU tHL Input Hold Time
VIH VIH
Input
VIL VIL
Figure 10. Input Setup and Hold Time
Clock or VIH
Input
VIL
tVAL Output Valid Time
Output Hold Time tOH
VOH VOH
Output
VOL VOL
Figure 11. Clock-to-Output and Propagation Delay

NPCA110B
3.5.2 Reset Timing
Symbol Figure Description Conditions Min Max Units
Power-Up Requirement: all power supplies at After reset delay

tCORD 12 5 ms
valid level until nRESET deasserted1
tPRST 12 nRESET Pulse Width To assure reset 1 ms
REF latched high 11000 12500 tREFCLK

tRSTC 12 Internal reset delay after nRESET deasserted
REF latched low 48000 52000 tREFCLK
tCLKRSTD 12 Stable reference clock to reset end 100 s
Valid straps signals level setup time to nRESET

tSTSU 12 100 s
rising
Valid straps signals level hold after nRESET
tSTH 12 10 tREFCLK
rising
Internal reset end to outputs enabled on strap
tOE 12 -100 tREFCLK
pins
1. Requirement for system.
95%
VDD tCORD
tRSTC
tPRST
nRESET
tCLKRSTD
Selected REF Clock
Internal Reset
tSTSU tSTH tOE
REF, nTEST, I2CMS, Valid Output enabled
Figure 12. Device Reset

NPCA110B
3.5.3 Clock Timing
CLKREF (DCLK or Oscillator) Clock Timing
Symbol Figure Description Conditions Min Typ Max Units
CLKREF Average Clock

tREFCLK 13 From RE to RE of CLKREF 50 1000 ns
Period
ACLK CLKREF Accuracy For a specific system 50 100 ppm
tCLKH 13 CLKREF High Time From RE to FE of CLKREF 35 ns
tCLKL 13 CLKREF Low Time From FE to RE of CLKREF 35 ns
tCLKR 13 CLKREF Rise Time From 0.8V to 2.0V 5 ns
tCLKF 13 CLKREF Fall Time From 2.0V to 0.8V 5 ns
Duty
CLKREF Duty Cycle At 1.4V 40 60 %
Cycle
JPERIOD Period Jitter1 At 1.4V 1.5 ns
1. Measured over a 20 s window.
tCLKH tREFCLK
CLKREF input VIH VIH VIH VIH
VIL VIL VIL
tCLKL tCLKF tCLKR
Figure 13. CLKREF Clock Waveforms
CLKOUT Timing
tCLK 14 CLKOUT Clock Period From RE to RE of CLKOUT, CL = 20 pF 50 ns
tCLKH 14 CLKOUT High Time1 From RE to FE of CLKOUT, CL = 20 pF 15 ns
tCLKL 14 CLKOUT Low Time1 From FE to RE of CLKOUT, CL = 20 pF 15 ns
tCLKR 14 CLKOUT Rise Time1 From VIL to VIH of CLKOUT, CL = 20 pF 5 ns
tCLKF 14 CLKOUT Fall Time1 From VIH to VIL of CLKOUT, CL = 20 pF 5 ns
DCLK CLKOUT Duty Cycle1 CL = 20 pF 28 %
tCLK
CLKOUT VIH
output 1.4V 1.4V 1.4V
VIL
tCLKH tCLKL tCLKF tCLKR
Figure 14. CLKOUT Clock Waveforms

NPCA110B
3.5.4 Input Signals Detection Timing
tSSCL Debounced SCL input pulse width

15 15 ns
(which guarantees detection)
tSSCL
SCL
Figure 15. Input Signal Detection Timing
3.5.5 I2C Slave Timing
fSCL SCL Frequency At 1.2V SCL RE to RE 4001 KHz

16
tLOW SCL Low Time At 0.8V (both edges) 0.5 s
tHIGH 16 SCL High Time At 2.0V (both edges) 0.26 s
tI2CR 16 SCL, SDA Rise Time From 0.8V to 2.0V1 0.252 s
tI2CF 16 SCL, SDA Fall Time From 2.0V to 0.8V1 100 ns
tSU:DAT 16 SDA Setup Time Before SCL RE 50 ns
tHD:DAT 17 SDA Hold Time After SCL FE 18 ns
tSU:STA 17 SCL Setup Time Before Restart condition 0.26 s
tHD:STA 17 SCL Hold Time After Start/Restart condition 0.26 s
tSU:STO 17 SCL Setup Time Before Stop condition 0.26 s
Between Stop and Start
tBUF 17 Bus Free Time 0.5 s
conditions
tVD:DAT 17 Data Valid Time After SCL FE 0.45 s
Data Valid
tVD:ACK 17 After SCL FE 0.45 s
Acknowledge Time
1. Test conditions: RL = 1 K to VDD = 3.3V, CL = 100 pF to GND
2. Not tested; based on design simulation.
fSCL
tHIGH tLOW
2.0 V
SCL 1.2 V
0.8 V
tI2CR tI2CF
Figure 16. I2C SCL Signal Timing

NPCA110B
SDA
SCL
tHD:STA tHD:DAT tSU:DAT tLOW tHIGH tVD:DAT, tVD:ACK
tSU:STA tSU:STO tBUF
SDA
SCL
Figure 17. I2C Timing
3.5.6 I2C Master Timing
SCL Frequency4 Programming capability fAEE / 16384 fAEE / 8

fSCL 16
SCL Frequency4 At 1.2V SCL RE to RE 0 400 1 KHz
tLOW 16 SCL Low Time4 At 0.8V (both edges) 8 x TAEE2 0.5 x TSCL3
tHIGH 16 SCL High Time4 At 2.0V (both edges) 8 x TAEE 0.5 x TSCL
tI2CR 16 SCL, SDA Rise Time From 0.8V to 2.0V1 0.254 s

tI2CF 16 SCL, SDA Fall Time4 From 2.0V to 0.8V1 100 ns
tSU:DAT 17 SDA Setup Time4 Before SCL RE 4 x TAEE 0.25 x TSCL
tHD:DAT 17 SDA Hold Time4 After SCL FE 4 x TAEE 0.25 x TSCL
tSU:STA 17 SCL Setup Time4 Before Restart condition 12 x TAEE 0.5 x TSCL
tHD:STA 17 SCL Hold Time4 After Start/Restart condition 4 x TAEE 0.5 x TSCL
tSU:STO 17 SCL Setup Time4 Before Stop condition 4 x TAEE 0.5 x TSCL
Between Stop and Start

tBUF 17 Bus Free Time4 conditions
16 x TAEE 0.5 x TSCL
tVD:DAT 17 Data Valid Time4 After SCL FE 4 x TAEE 0.5 x TSCL
Data Valid
tVD:ACK After SCL FE 4 x TAEE 0.5 x TSCL
Acknowledge Time4
1. Test conditions: RL = 1 K to VDD = 3.3V, CL = 100 pF to GND.
2. TAEE is the Processor core clock period.
3. TSCL is the SCL clock period (1/fSCL).
4. Not tested; based on design simulation.

NPCA110B
3.5.7 SSI Timing
tT 18 DCLK Cycle Time At 1.3V DCLK RE to RE 1/64 1/64 1/32 1/FS1
fDCLK DCLK Frequency 32 64 64 FS1

tLOW 18 DCLK Low Time At 0.8V (both edges) 0.35 0.5 tT
tHIGH 18 DCLK High Time At 2.0V (both edges) 0.35 0.5 tT
tHTR 18 Output Hold Time After DCLK RE 15 ns 0.5 * tT

tDTR 18 Output Valid Time After DCLK RE 0.5 0.75 tT
tHR 18 Input Hold Time After DCLK RE 2 tT
tSR 18 Input Setup Time Before DCLK RE 0.2 tT
1. FS is the audio sampling frequency
tT
tHIGH tLOW
2.0V 2.0V 2.0V

DCLK 1.3V 1.3V
0.8V 0.8V 0.8V
tHTR
tDTR
2.0V 2.0V
Outputs: SYNC, SDO0-2
0.8V 0.8V
tSR tHR
2.0V 2.0V
Inputs: SYNC, SDI0-2
0.8V 0.8V
Figure 18. SSI Signal Timing

NPCA110B
3.6 PACKAGE THERMAL INFORMATION

Thermal resistance (degrees oC/W) ThetaJA values for the NPCA110B packages are as follows:
Table 3. Theta () J-A Values
JA (Degrees Kelvin/Watt)
Package 0 m/s 1 m/s 2 m/s

32-Pin QFN32 54 46 45
Note: All values apply to a device soldered to a 4-layer PCB.

NPCA110B
Physical Dimensions
Control dimensions are in millimeters.
32-Pin Quad Flat No-Lead (QFN) Package

Order Number: NPCA110BA0YX
Device topside mark specification:

1st Line: Part number - NPCA110B NPCA110B
2nd Line: A0YX YWW.
A0 - End of part number; ‘Y’: QFN package indicator; A0YX YWW
‘X’: Green package finish indicator.
YWW: Date Code. ZZ ZZZZZZ
3rd and 4th Lines: Nuvoton proprietary information. ZZZZZ
Date code: YWW, where Y is the year and WW is the week. For example, date code
035 indicates that device assembly was done on week 35, year 2010.

Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended
for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traf-
fic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore,
Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein
personal injury, death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify
Nuvoton for any damages resulting from such improper use or sales.
Headquarters Nuvoton Technology Corporation America Nuvoton Technology (Shanghai) Ltd.

No. 4, Creation Rd. 3, 2727 North First Street, 27F, 2299 Yan An W. Rd.
Science-Based Industrial Park, San Jose, CA 95134, U.S.A. Shanghai, 200336 China
Hsinchu, Taiwan, R.O.C TEL: 1-408-544-1718 TEL: 86-21-62365999
TEL: 886-3-5770066 FAX: 1-408-544-1787 FAX: 86-21-62365998
FAX: 886-3-5665577
http://www.nuvoton.com.tw (Chinese)
http://www.nuvoton.com (English)
Taipei Office Winbond Electronics Corporation Japan Nuvoton Technology (H.K.) Ltd.
9F, No.480, Rueiguang Rd., NO. 2 Ueno-Bldg., 7-18, 3-chome Unit 9-15, 22F, Millennium City 2,
Neihu District, Taipei, 114, Shinyokohama Kohoku-ku, 378 Kwun Tong Rd.,
Taiwan, R.O.C. Yokohama, 222-0033 Kowloon, Hong Kong
TEL: 886-2-2658-8066 TEL: 81-45-4781881 TEL: 852-27513100
FAX: 886-2-8751-3579 FAX: 81-45-4781800 FAX: 852-27552064
For Advanced PC Product Line information contact: [email protected]
Please note that all data and specifications are subject to change without notice.
All trademarks of products and companies mentioned in this document belong to their respective owners.
www.nuvoton.com

NPCA110B-Nuvoton Technology

Uploaded by

Document Informationclick to expand document information

Document Informationclick to expand document information

Copyright:

Available Formats

NPCA110B-Nuvoton Technology

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

NPCA110B-Nuvoton Technology

Uploaded by

Copyright:

Available Formats

Nuvoton Confidential

NPCA110B Audio Enhancing Engine and CODEC

NPCA110B Audio Enhancing Engine and CODEC

the acoustic limitations of small CE devices.

System Block Diagram Speakers

© 2012 Nuvoton Technology Corporation www.nuvoton.com

Algorithm Processing Chain

Maxx Maxx Maxx

www.nuvoton.com 2 Revision 1.1

M16 -126dB .. 0dB

Note: All paths in the diagram are stereo

Figure 1. Device Block Diagram

February 2011 Revision 0.10 Datasheet first revision.

www.nuvoton.com 4 Revision 1.1

Revision Record ................................................................................................................................................ 4

1.0 Signal/Pin Description

2.0 Power, Clocks and Reset

3.0 Device Specifications

Revision 1.1 5 www.nuvoton.com

3.4 ANALOG CHARACTERISTICS ................................................................................................... 21

www.nuvoton.com 6 Revision 1.1

1.1 CONNECTION DIAGRAM

Note: Bottom Pad is VSS.

32-Pin Quad Flat No-Lead (QFN) Package

Revision 1.1 7 www.nuvoton.com

1.2 PIN TYPES

GPIO General-Purpose I/O

T Input buffer with CMOS / LVTTL levels

1.3 PIN DESCRIPTION

1.3.1 Clocks and Reset

XTALI/CLKIN I Crystal Clock Input. Used for a crystal VDD XO

XTALO O Crystal Clock Output. Used for a crystal

nRESET I Power-Up Reset Input. If driven low, PU VDD 5V, ST

GPO17 O General-Purpose Output Signal 17. PU VDD T, 5V, O8/8

GPIO20 / I/O General-Purpose I/O Signal 20. / PU VDD T, 5V, O2/2

www.nuvoton.com 8 Revision 1.1

1.3.3 I2S / GPIO / STRAPS

GPIO00 / I/O General-Purpose I/O Signal 00. / PU VDD T,5V,O2/2

GPIO01 / I/O General-Purpose I/O Signal 01. / PU VDD T,5V,O2/2

GPO06 / O General-Purpose Output Signal 06. / PU VDD T,5V,O2/2

GPO07 / O General-Purpose Output Signal 07. / PU VDD T,5V,O2/2

GPO18 / O General-Purpose Output Signal 18. / PU VDD T,5V,O2/2

1.3.4 I2C / GPIO

SDA I/O Master/Slave I2C Data Line. VDD ST,5V,OD6

Revision 1.1 9 www.nuvoton.com

VCM P CODEC Internally Generated Common-Mode Voltage. Should be AVDD analog

AVDD P CODEC Analog 3.3V Supply. Should be connected to a filtered supply.

AVSS G CODEC Analog Ground. Should be connected to ground. The user

Signal I/O Description

VDD P 3.3V Digital Supply.

www.nuvoton.com 10 Revision 1.1

Table 2. NPCA110B Power Planes

Power Plane Power Plane

2.1.2 Power States

Illegal Power States

2.1.3 Power Connection and Layout Guidelines

Revision 1.1 11 www.nuvoton.com

2.0 Power, Clocks and Reset (Continued)