uA9637A Dual Differential Line Receiver: 1 Features 3 Description

UA9637A
SLLS111C – SEPTEMBER 1980 – REVISED JANUARY 2024
uA9637A Dual Differential Line Receiver
1 Features 3 Description
• Meets or exceeds the requirements of ANSI The uA9637A is a dual differential line receiver
standards EIA/TIA-422-B and EIA/TIA-423-B and designed to meet ANSI Standards EIA/TIA-422-B
ITU recommendations V.10 and V.11 and EIA/TIA-423-B and ITU Recommendations V.10
• Operates From Single 5V power supply and V.11. The line receiver uses Schottky circuitry,
• Wide common-mode voltage range and has TTL-compatible outputs. The inputs are
• High input impedance compatible with either a single-ended or a differential-
• TTl-compatible outputs line system. This device operates from a single 5V
• High-speed schottky circuitry power supply and is supplied in an 8-pin dual-in-line
• 8-Pin dual-in-line and small-outline packages package or small-outline package.
• Designed to be interchangeable with national
The uA9637A is characterized for operation from 0°C
DS9637A
to 70°C.
2 Applications Package Information
• Factory automation PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
• AC and servo motor drives SOIC (D, 8) 4.9mm × 6mm
uA9637A
PDIP (P, 8) 9.81mm × 9.43mm
(1) For more information, see Section 11.

(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
Logic Symbol† Logic Diagram
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UA9637A
SLLS111C – SEPTEMBER 1980 – REVISED JANUARY 2024 www.ti.com
Table of Contents
1 Features............................................................................1 7 Detailed Description........................................................8
2 Applications..................................................................... 1 7.1 Device Functional Modes............................................8
3 Description.......................................................................1 8 Application and Implementation.................................. 10
4 Pin Configuration and Functions...................................3 8.1 Typical Application.................................................... 10
5 Specifications.................................................................. 4 9 Device and Documentation Support............................11
5.1 Absolute Maximum Ratings........................................ 4 9.1 Support Resources................................................... 11
5.2 Dissipation Rating Table............................................. 4 9.2 Trademarks............................................................... 11
5.3 Recommended Operating Conditions.........................4 9.3 Electrostatic Discharge Caution................................ 11
5.4 Thermal Resistance Characteristics........................... 4 9.4 Glossary.................................................................... 11
5.5 Electrical Characteristics.............................................5 10 Revision History.......................................................... 11
5.6 Switching Characteristics............................................5 11 Mechanical, Packaging, and Orderable
5.7 Typical Characteristics................................................ 6 Information.................................................................... 11
6 Parameter Measurement Information............................ 7
2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: UA9637A

UA9637A
www.ti.com SLLS111C – SEPTEMBER 1980 – REVISED JANUARY 2024
4 Pin Configuration and Functions
Figure 4-1. D (SOIC) or P (PDIP) Package

(Top View)
Table 4-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME NO.
VCC 1 POW 5V (+/-5%) Positive Supply Connection Pin
1OUT 2 O Single Ended Output for Channel 1 Differential Receiver
2OUT 3 O Single Ended Output for Channel 2 Differential Receiver
GND 4 GND Device Ground
2IN- 5 I Inverting Differential Input for Channel 2's Differential Receiver
2IN+ 6 I Non-Inverting Differential Input for Channel 2's Differential Receiver
1IN- 7 I Inverting Differential Input for Channel 1's Differential Receiver

1IN+ 8 I Non-Inverting Differential Input for Channel 1's Differential Receiver
(1) Signal Types: I = Input, O = Output, I/O = Input or Output, POW = Power, GND = Ground.
Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

UA9637A
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range (see Note 1) –0.5 7 V
VI Input voltage ±15 V
VID Differential input voltage (see (3)) ±15 V
VO Output voltage range (see (2)) –0.5 5.5 V
IOL Low-level output current 50 mA
Continuous total dissipation See Dissipation Rating Table
TA Operating free-air temperature range 0 70 °C
Tstg Storage temperature range –65 150 °C
Lead temperature 1,6mm (1/16 inch) from case for 10
260 °C
seconds
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential input voltage, are with respect to the network ground terminal.
(3) Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
5.2 Dissipation Rating Table

OPERATING FACTOR ABOVE
PACKAGE TA ≤ 25°C POWER RATING TA = 70°C POWER RATING
TA = 25°C
D 725mW 5.8mW/°C 464mW
P 1000mW 8.0mW/°C 640mW
5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Common-mode input voltage, VIC ±7 V
Operating free-air temperature, TA 0 70 °C
5.4 Thermal Resistance Characteristics

D (SOIC) P (PDIP)
THERMAL METRIC(1) UNIT
8 Pins 8 Pins
R θJA Junction-to-ambient thermal resistance 116.7 65.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 56.3 54.7 °C/W
R θJB Junction-to-board thermal resistance 63.4 42.1 °C/W
ψ JT Junction-to-top characterization parameter 8.8 23 °C/W
ψ JB Junction-to-board characterization parameter 62.6 41.7 °C/W
R θJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

UA9637A
5.5 Electrical Characteristics

over recommended ranges of supply voltage, common-mode input voltage, and operating free-air temperature (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
0.2
VIT + Positive-going input threshold voltage See (4) V
0.4
-0.2
VIT- Negative-going input threshold voltage See (4) V
-0.4(2)
Vhys Hysteresis voltage (VIT+-VIT-) 70 mV
VOH High-level output voltage VID = 0.2V, IO = -1mA 2.5 1.5 V
VOL Low-level output voltage VID = -0.2V, IO = 20mA 0.35 0.5 V
VCC = 0 to 5.5V, VI = 10V 1.1 1.25
II Input current mA
See (5) VI = -10V -1.6 -1.25
IOS Short-circuit output current(3) VO = 0, VID = 0.2V -40 -75 -100 mA
ICC Supply current VID = -0.5V, No load 35 50 mA
(1) All typical values are at VCC = 5 V, TA = 25°C.

(2) The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for
threshold levels only.
(3) Only one output should be shorted at a time, and duration of the short circuit should not exceed one second.
(4) The expanded threshold parameter is tested with a 500-Ω resistor in series with each input.
(5) The input not under test is grounded.
5.6 Switching Characteristics

VCC = 5V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output 15 25 ns
CL = 30pF, See Figure 6-1
tPHL Propagation delay time, high- to low-level output 13 25 ns

UA9637A
5.7 Typical Characteristics
Figure 5-1. Output Voltage vs Differential Input Voltage Figure 5-2. Output Voltage vs Differential Input Voltage
Figure 5-3. High-level Output Voltage vs High-level Output Figure 5-4. Low-level Output Voltage vs Low-level Output
Current Current
Figure 5-5. Supply Current vs Supply Voltage

UA9637A
6 Parameter Measurement Information
A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: tr ≤ 5 ns, tf ≤ 5 ns, PRR ≤ 5 MHz, duty cycle = 50%.
Figure 6-1. Test Circuit and Voltage Waveform

UA9637A
7 Detailed Description
7.1 Device Functional Modes
Table 7-1. Functional Table (Each Receiver)
ENABLES(1)
DIFFERENTIAL INPUTS A – B (VID) OUTPUT Y
G G
H X
VID ≤ −0.2 V L
X L
H X
−0.2 V < VID < −0.01 V ?
X L
H X
−0.01 V ≤ VID H
X L
L H
X Z
OPEN OPEN
H X
Short circuit H
X L
Open circuit H X H
(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
Figure 7-1. Equivalent Input and Output Schematic Diagrams

UA9637A
7.1.1 Schematics of Inputs and Outputs

UA9637A
8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Typical Application
Figure 8-1. EIA/TIA-422-B System Applications

UA9637A
9 Device and Documentation Support

9.1 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.2 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.4 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 1995) to Revision C (January 2024) Page
• Changed the numbering format for tables, figures, and cross-references throughout the document................ 1
11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
UA9637ACD OBSOLETE SOIC D 8 TBD Call TI Call TI 0 to 70 9637AC

UA9637ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 9637AC Samples
UA9637ACDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 9637AC Samples
UA9637ACDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 9637AC Samples
UA9637ACP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UA9637ACP Samples
UA9637ACPS ACTIVE SO PS 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM UA9637A Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2024
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2024
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UA9637ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UA9637ACDR SOIC D 8 2500 353.0 353.0 32.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
UA9637ACP P PDIP 8 50 506 13.97 11230 4.32
UA9637ACPS PS SOP 8 80 530 10.5 4000 4.1
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
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such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated

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UA9637A

SLLS111C – SEPTEMBER 1980 – REVISED JANUARY 2024

uA9637A Dual Differential Line Receiver

(1) For more information, see Section 11.

Logic Symbol† Logic Diagram

2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UA9637A

4 Pin Configuration and Functions

Figure 4-1. D (SOIC) or P (PDIP) Package

Table 4-1. Pin Functions

1IN- 7 I Inverting Differential Input for Channel 1's Differential Receiver

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

5.2 Dissipation Rating Table

5.3 Recommended Operating Conditions

5.4 Thermal Resistance Characteristics

4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UA9637A

5.5 Electrical Characteristics

(1) All typical values are at VCC = 5 V, TA = 25°C.

5.6 Switching Characteristics

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5

5.7 Typical Characteristics

Figure 5-5. Supply Current vs Supply Voltage

6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UA9637A

6 Parameter Measurement Information

A. CL includes probe and jig capacitance.

Figure 6-1. Test Circuit and Voltage Waveform

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7

Figure 7-1. Equivalent Input and Output Schematic Diagrams

8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UA9637A

7.1.1 Schematics of Inputs and Outputs

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9

8 Application and Implementation

8.1 Typical Application

Figure 8-1. EIA/TIA-422-B System Applications

10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UA9637A

9 Device and Documentation Support

11 Mechanical, Packaging, and Orderable Information

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11

UA9637ACD OBSOLETE SOIC D 8 TBD Call TI Call TI 0 to 70 9637AC

UA9637ACPS ACTIVE SO PS 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM UA9637A Samples

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

Reel Width (W1)

Q3 Q4 Q3 Q4 User Direction of Feed

*All dimensions are nominal

TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

B - Alignment groove width

*All dimensions are nominal

LAND PATTERN EXAMPLE

SOLDER MASK SOLDER MASK

NON SOLDER MASK SOLDER MASK

SOLDER MASK DETAILS

6. Publication IPC-7351 may have alternate designs.

SOLDER PASTE EXAMPLE