CS5102: FOUNDATIONS OF COMPUTER SYSTEMS

LECTURE 5: PROGRAMMING - PART I

DR. ARIJIT ROY
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
INDIAN INSTITUTE OF TECHNOLOGY PATNA

These slides are based on the book: David A. Patterson, John L. Hennessy, Computer Organization and Design
TOPICS
➢ Introduction
➢ Assembly Language
➢ Machine Language
➢ Programming
➢ Addressing Modes
PROGRAMMING
➢ High-level languages:
➢ e.g., C, Java, Python
➢ Written at more abstract level
➢ Common high-level software constructs:
➢ if/else statements
➢ for loops
➢ while loops
➢ array accesses
➢ procedure calls
➢ Other useful instructions:
➢ Arithmetic/logical instructions
➢ Branching
LOGICAL INSTRUCTIONS
• and, or, xor, nor

• and: useful for masking bits

• Masking all but the least significant byte of a value: 0xF234012F AND 0x000000FF = 0x0000002F
• or: useful for combining bit fields
• Combine 0xF2340000 with 0x000012BC: 0xF2340000 OR 0x000012BC = 0xF23412BC
• nor: useful for inverting bits: A NOR $0 = NOT A
• andi, ori, xori
– 16-bit immediate is zero-extended (not sign-extended)
– nori not needed
LOGICAL INSTRUCTION EXAMPLES

Source Registers
$s1 1111 1111 1111 1111 0000 0000 0000 0000

$s2 0100 0110 1010 0001 1111 0000 1011 0111

Assembly Code Result

and $s3, $s1, $s2 $s3
or $s4, $s1, $s2 $s4
xor $s5, $s1, $s2 $s5
nor $s6, $s1, $s2 $s6
LOGICAL INSTRUCTION EXAMPLES

Source Registers
$s1 1111 1111 1111 1111 0000 0000 0000 0000

$s2 0100 0110 1010 0001 1111 0000 1011 0111

Assembly Code Result

and $s3, $s1, $s2 $s3 0100 0110 1010 0001 0000 0000 0000 0000
or $s4, $s1, $s2 $s4 1111 1111 1111 1111 1111 0000 1011 0111
xor $s5, $s1, $s2 $s5 1011 1001 0101 1110 1111 0000 1011 0111
nor $s6, $s1, $s2 $s6 0000 0000 0000 0000 0000 1111 0100 1000
LOGICAL INSTRUCTION EXAMPLES

Source Values
$s1 0000 0000 0000 0000 0000 0000 1111 1111

imm 0000 0000 0000 0000 1111 1010 0011 0100

zero-extended
Assembly Code Result
andi $s2, $s1, 0xFA34 $s2
ori $s3, $s1, 0xFA34 $s3
xori $s4, $s1, 0xFA34 $s4
LOGICAL INSTRUCTION EXAMPLES

Source Values
$s1 0000 0000 0000 0000 0000 0000 1111 1111

imm 0000 0000 0000 0000 1111 1010 0011 0100

zero-extended
Assembly Code Result
andi $s2, $s1, 0xFA34 $s2 0000 0000 0000 0000 0000 0000 0011 0100
ori $s3, $s1, 0xFA34 $s3 0000 0000 0000 0000 1111 1010 1111 1111
xori $s4, $s1, 0xFA34 $s4 0000 0000 0000 0000 1111 1010 1100 1011
SHIFT INSTRUCTIONS
• sll: shift left logical
– Example: sll $t0, $t1, 5 #$t0 <=$t1 << 5
• srl: shift right logical
– Example: srl $t0, $t1, 5 #$t0 <=$t1 >> 5

• sra: shift right arithmetic

– Example: sra $t0, $t1, 5 #$t0 <=$t1 >>> 5
SHIFT INSTRUCTIONS
Assembly Code Field Values
op rs rt rd shamt funct
sll $t0, $s1, 2 0 0 17 8 2 0
srl $s2, $s1, 2 0 0 17 18 2 2
sra $s3, $s1, 2 0 0 17 19 2 3
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Machine Code
op rs rt rd shamt funct

000000 00000 10001 01000 00010 000000 (0x00114080)

000000 00000 10001 10010 00010 000010 (0x00119082)

000000 00000 10001 10011 00010 000011 (0x00119883)

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
GENERATING CONSTANTS
• 16-bit constants using addi:
High-level code MIPS assembly code
// int is a 32-bit signed word # $s0 = a
int a = 0x4f3c; addi $s0, $0, 0x4f3c
• 32-bit constants using load upper immediate (lui) and ori:
(lui loads the 16-bit immediate into the upper half of the register and sets the lower half to 0.)
lui $s0, 10101010 10101010 11110000 11110000

s0 = 10101010 10101010 00000000 00000000

ori $s0, 11110000 11110000

s0 = 10101010 10101010 11110000 11110000

MIPS assembly code
High-level code # $s0 = a
int a = 0xFEDC8765; lui $s0, 0xFEDC
ori $s0, $s0, 0x8765
MULTIPLICATION, DIVISION
• Special registers: lo, hi
• 32 × 32 multiplication, 64 bit result
– mult $s0, $s1
– Result in {hi, lo}
• 32-bit division, 32-bit quotient, 32-bit remainder
– div $s0, $s1
– Quotient in lo
– Remainder in hi
• Moves from lo/hi special registers
– mflo $s2
– mfhi $s3
BRANCHING
• Allows a program to execute instructions out of sequence.
• Types of branches:
– Conditional branches
• branch if equal (beq) beq R1, R2 (2000)
• branch if not equal (bne)
– Unconditional branches
• jump (j)
• jump register (jr)
• jump and link (jal)
REVIEW: THE STORED PROGRAM
Assembly Code Machine Code
lw $t2, 32($0) 0x8C0A0020
add $s0, $s1, $s2 0x02328020
addi $t0, $s3, -12 0x2268FFF4
sub $t0, $t3, $t5 0x016D4022

Stored Program

Address Instructions

0040000C 01 6 D 4 0 22
00400008 22 6 8 F F F4
00400004 02 3 2 8 0 20
00400000 8C 0 A 0 0 20 PC

Main Memory
WORD-ADDRESSABLE MEMORY
• Each 32-bit data word has a unique address

Word Address Data

• Data space in a cell: Word length of CPU
• Word: A unit of data that can be stored or operated
• A cell is uniquely identified by a binary number
00000003 40 F 3 0 7 8 8 Word 3
00000002 01 E E 2 8 4 2 Word 2
00000001 F2 F 1 A C 0 7 Word 1
00000000 AB C D E F 7 8 Word 0
READING WORD-ADDRESSABLE MEMORY
➢ Memory reads are called loads
➢ Mnemonic: load word (lw)
➢ Example: read a word of data at memory address 1 into $s3
➢ Memory address calculation:
➢ add the base address ($0) to the offset (1)
➢ address = ($0 + 1) = 1
➢ Any register may be used to store the base address.
➢ $s3 holds the value 0xF2F1AC07 after the instruction completes.
Assembly code
lw $s3, 1($0) # read memory word 1 into $s3
Word Address Data

00000003 40 F 3 0 7 8 8 Word 3
00000002 01 E E 2 8 4 2 Word 2
00000001 F2 F 1A C 0 7 Word 1
00000000 AB C D E F 7 8 Word 0
WRITING WORD-ADDRESSABLE MEMORY
➢ Memory writes are called stores
➢ Mnemonic: store word (sw)
➢ Example: Write (store) the value held in $t4 into memory address 7
➢ Offset can be written in decimal (default) or hexadecimal
➢ Memory address calculation:
➢ – add the base address ($0) to the offset (0x7)
➢ – address: ($0 + 0x7) = 7
➢ Any register may be used to store the base address
Word Address Data
Assembly code .
. .
sw $t4, 0x7($0) # write the value in $t4 .
# to memory word 7 .
.
00000003 40 F 3 0 7 8 8 Word 3
00000002 01 E E 2 8 4 2 Word 2
00000001 F2 F 1A C 0 7 Word 1
00000000 AB C D E F 7 8 Word 0
BYTE-ADDRESSABLE MEMORY
➢ Each data byte has a unique address
➢ Load/store words or single bytes: load byte (lb) and store byte (sb)
➢ Each 32-bit words has 4 bytes, so the word address increments by 4

Word Address Data

• Data space in a cell: 8bits = 1byte
• A cell is uniquely identified by a binary number
0000000C 4 0 F 3 0 7 8 8 Word 3
00000008 0 1 E E 2 8 4 2 Word 2
00000004 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

width = 4 bytes
READING BYTE-ADDRESSABLE MEMORY
➢ The address of a memory word must now be multiplied by 4. For example,
➢ the address of memory word 2 is 2 × 4 = 8
➢ the address of memory word 10 is 10 × 4 = 40 (0x28)
➢ Load a word of data at memory address 4 into $s3.
➢ $s3 holds the value 0xF2F1AC07 after the instruction completes.
➢ MIPS is byte-addressed, not word-addressed
MIPS assembly code
lw $s3, 4($0) # read word at address 4 into $s3

Word Address Data

0000000C 4 0 F 3 0 7 8 8 Word 3
00000008 0 1 E E 2 8 4 2 Word 2
00000004 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

width = 4 bytes
WRITING BYTE-ADDRESSABLE MEMORY
• Example: stores the value held in $t7 into memory address 0x2C (44)

MIPS assembly code

sw $t7, 44($0) # write $t7 into address 44

Word Address Data

0000000C 4 0 F 3 0 7 8 8 Word 3
00000008 0 1 E E 2 8 4 2 Word 2
00000004 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

width = 4 bytes
BIG-ENDIAN AND LITTLE-ENDIAN MEMORY
➢ How to number bytes within a word?
➢ Word address is the same for big- or little-endian
➢ Little-endian: byte numbers start at the little (least significant) end
➢ Big-endian: byte numbers start at the big (most significant) end

Big-Endian Little-Endian
Byte Address Word Byte Address
Address

C D E F C F E D C
8 9 A B 8 B A 9 8
4 5 6 7 4 7 6 5 4
0 1 2 3 0 3 2 1 0
MSB LSB MSB LSB
BIG-ENDIAN AND LITTLE-ENDIAN MEMORY
➢ From Jonathan Swift’s Gulliver’s Travels where the Little-Endians broke
their eggs on the little end of the egg and the Big-Endians broke their eggs
on the big end.
➢ As indicated by the farcical name, it doesn’t really matter which addressing
type is used – except when the two systems need to share data!

Big-Endian Little-Endian
Byte Address Word Byte Address
Address

C D E F C F E D C
8 9 A B 8 B A 9 8
4 5 6 7 4 7 6 5 4
0 1 2 3 0 3 2 1 0
MSB LSB MSB LSB
BIG- AND LITTLE-ENDIAN EXAMPLE
➢ Suppose $t0 initially contains 0x23456789. After the following program is run
on a big-endian system, what value does $s0 contain? In a little-endian system?

sw $t0, 0($0)
lb $s0, 1($0)
BIG- AND LITTLE-ENDIAN EXAMPLE
➢ Suppose $t0 initially contains 0x23456789. After the following program is run
on a big-endian system, what value does $s0 contain? In a little-endian system?

sw $t0, 0($0)
lb $s0, 1($0)

• Big-endian: 0x00000045
• Little-endian: 0x00000067
Big-Endian Little-Endian
Word
Byte Address 0 1 2 3 Address 3 2 1 0 Byte Address
Data Value 23 45 67 89 0 23 45 67 89 Data Value
MSB LSB MSB LSB
THE POWER OF THE STORED PROGRAM
➢ 32-bit instructions and data stored in memory
➢ Sequence of instructions: only difference between two applications (for example,
a text editor and a video game)
➢ To run a new program:
➢ No rewiring required
➢ Simply store new program in memory
➢ The processor hardware executes the program:
➢ fetches (reads) the instructions from memory in sequence
➢ performs the specified operation
➢ The program counter (PC) keeps track of the current instruction
➢ In MIPS, programs typically start at memory address 0x00400000
THE STORED PROGRAM
Assembly Code Machine Code
lw $t2, 32($0) 0x8C0A0020
add $s0, $s1, $s2 0x02328020
addi $t0, $s3, -12 0x2268FFF4
sub $t0, $t3, $t5 0x016D4022

Stored Program

Address Instructions

0040000C 01 6 D 4 0 22
00400008 22 6 8 F F F4
00400004 02 3 2 8 0 20
00400000 8C 0 A 0 0 20 PC

Main Memory
CONDITIONAL BRANCHING (BEQ)
# MIPS assembly
addi $s0, $0, 4 # $s0 = 0 + 4 = 4
addi $s1, $0, 1 # $s1 = 0 + 1 = 1
sll $s1, $s1, 2 # $s1 = 1 << 2 = 4
beq $s0, $s1, target # branch is taken
addi $s1, $s1, 1 # not executed
sub $s1, $s1, $s0 # not executed

target: # label
add $s1, $s1, $s0 # $s1 = 4 + 4 = 8

Labels indicate instruction locations in a program. They cannot use reserved

words and must be followed by a colon (:).
THE BRANCH NOT TAKEN (BNE)
# MIPS assembly
addi $s0, $0, 4 # $s0 = 0 + 4 = 4
addi $s1, $0, 1 # $s1 = 0 + 1 = 1
sll $s1, $s1, 2 # $s1 = 1 << 2 = 4
bne $s0, $s1, target # branch not taken
addi $s1, $s1, 1 # $s1 = 4 + 1 = 5
sub $s1, $s1, $s0 # $s1 = 5 – 4 = 1

target:
add $s1, $s1, $s0 #$s1 = 1 + 4 = 5
UNCONDITIONAL BRANCHING / JUMPING (J)
# MIPS assembly
addi $s0, $0, 4 # $s0 = 4
addi $s1, $0, 1 # $s1 = 1
j target # jump to target
sra $s1, $s1, 2 # not executed
addi $s1, $s1, 1 # not executed
sub $s1, $s1, $s0 # not executed

target:
add $s1, $s1, $s0 #$s1 = 1 + 4 = 5
UNCONDITIONAL BRANCHING (JR)
# MIPS assembly
0x00002000 addi $s0, $0, 0x2010
0x00002004 jr $s0
0x00002008 addi $s1, $0, 1
0x0000200C sra $s1, $s1, 2
0x00002010 lw $s3, 44($s1)
THANK YOU!

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