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20a04504a Computer Architecture and Organization

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156 views1 page

20a04504a Computer Architecture and Organization

Uploaded by

Shaik Althaf
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Code: 20A04504a R20

B.Tech III Year I Semester (R20) Supplementary Examinations July 2024


COMPUTER ARCHITECTURE AND ORGANIZATION
(Electronics & Communication Engineering)
Time: 3 hours Max. Marks: 70
PART – A
(Compulsory Question)
*****
1 Answer the following: (10 X 02 = 20 Marks)
(a) Define computer organisation and computer architecture. 2M
(b) List the Phases of instruction cycle. 2M
(c) Draw the block diagram of Micro-Programmed control organisation. 2M
(d) Write short notes on Implied mode and register mode of Addressing modes? 2M
(e) Convert (101.11011)2 into Decima and Octal. 2M
(f) Draw the flowchart of Hardware Divide Algorithm. 2M
(g) What is the impact of cache on overall performance of the computer? 2M
(h) Write short notes on isolated I/O. 2M
(i) Write the advantage of RISC over CISC. 2M
(j) Distinguish between tightly coupled and loosely coupled microprocessors. 2M

PART – B
(Answer all the questions: 05 X 10 = 50 Marks)

2 Explain different functional units of a digital computer with neat sketch. 10M
OR
3 What is Register transfer language? Explain the basic symbols used in register transfer. 10M

4 What is Micro operation? Briefly explain the arithmetic micro-operations. 10M


OR
5 Briefly explain the conditional branch instructions. 10M

6 Multiply 7 and 3 using booth algorithm. 10M


OR
7 Perform division of 1000 and 0011 using restoring division algorithm. 10M

8 With a neat diagram, describe DMA transfer in a computer system. 10M


OR
9 Explain the strobe control method of Asynchronous data transfer. What are the disadvantages of 10M
this method?

10 What is Pipelining? Name the two pipeline organizations. Explain about the arithmetic pipeline 10M
with the help of an example.
OR
11 Describe the need for Inter-Processor communication. Elaborate the synchronization concept 10M
used in inter processor communication.

*****

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