▪ Digital systems are designed with flip‐flops and gates.

▪ Since the combinational PLD consists of only gates, it is necessary to include external flip‐flops when they are
used in the design.

▪ Sequential programmable devices include both gates and flip‐flops.

▪ In this way, the device can be programmed to perform a variety of sequential‐circuit functions.

▪ There are several types of sequential programmable devices available commercially, but the internal logic of
these devices is too complex to be shown here.

▪ Therefore, we will describe three major types without going into their detailed construction:

1. Sequential (or simple) programmable logic device (SPLD)

2. Complex programmable logic device (CPLD)
3. Field‐programmable gate array (FPGA)
Sequential (or simple) programmable logic device (SPLD)

▪ The sequential PLD is sometimes referred to as a simple PLD to differentiate it from the complex PLD.

▪ The SPLD includes flip‐flops, in addition to the AND–OR array, within the integrated circuit chip.

▪ The result is a sequential circuit as shown below.

▪ A PAL or PLA is modified by including a number of flip‐flops connected to form a register.

▪ The circuit outputs can be taken from the OR gates or from the outputs of the flip‐flops (D or the JK type).
Additional programmable connections are available to include the flip‐flop outputs in the product terms formed
with the AND array.
Sequential (or simple) programmable logic device (SPLD)
▪ The configuration mostly used in an SPLD is the combinational PAL together with D flip‐flops.

▪ A PAL that includes flip‐flops is referred to as a registered PAL, to signify that the device contains
flip‐flops in addition to the AND–OR array.

▪ Each section of an SPLD is called a macrocell, which is a circuit that contains a sum‐of‐products
combinational logic function and an optional flip‐flop.

▪ We will assume an AND–OR sum‐of‐products function, but in practice, it can be any one of the
two‐level implementations presented in Section 3.7.
Sequential (or simple) programmable logic device (SPLD)
▪ The configuration mostly used in an SPLD is the combinational PAL together with D flip‐flops.

▪ A PAL that includes flip‐flops is referred to as a registered PAL, to signify that the device contains
flip‐flops in addition to the AND–OR array.

▪ Each section of an SPLD is called a macrocell, which is a circuit that contains a sum‐of‐products
combinational logic function and an optional flip‐flop.

▪ We will assume an AND–OR sum‐of‐products function, but in practice, it can be any one of the
two‐level implementations presented in Section 3.7.

SELF-STUDY ASSIGNMENT
▪ The behavior of many digital systems depends on the history of their inputs, and the conditions that determine their
future actions depend on the results of previous actions. Such systems are said to have “memory.”

▪ A digital system is a sequential logic system constructed with flip‐flops and gates.

▪ Sequential circuits can be specified by means of state tables as shown in Chapter 5 .

▪ To specify a large digital system with a state table is very difficult, because the number of states would be enormous.

▪ To overcome this difficulty, digital systems are designed via a modular approach.

▪ The system is partitioned into subsystems, each of which performs some function.

▪ The modules are constructed from digital devices such as registers, decoders, multiplexers, arithmetic elements, and
control logic.

▪ The various modules are interconnected with datapaths and control signals to form a digital system.

▪ In this chapter, we will introduce a design methodology for describing and designing large, complex digital systems.
▪ The modules of a digital system are best defined by a set of registers and the operations that are performed on the
binary information stored in them. Examples of register operations are shift, count, clear, and load .

▪ Registers are assumed to be the basic components of the digital system.

▪ A register is a connected group of flip‐flops that stores binary information and has the capability of performing one or
more elementary operations.

▪ The information flow and processing performed on the data stored in the registers are referred to as register transfer
operations.

A digital system is represented at the register transfer level (RTL) when it is specified by the following three
components:

1. The set of registers in the system.

2. The operations that are performed on the data stored in the registers.
3. The control that supervises the sequence of operations in the system.
Register Transfer Level Notations
Information transfer from one register to another is designated in symbolic
form by means of a replacement operator.

Normally, we want a register transfer operation to occur, not with every

clock cycle, but only under a predetermined condition.

A conditional statement governing a register transfer operation is

symbolized with an if–then statement such as
Register Transfer Level Notations
A comma may be used to separate two or more operations that are executed
at the same time (concurrently). Consider the statement

Other examples of register transfers are

 Register Transfer Level
In hardware,

• addition is done with a binary parallel adder,

• incrementing is done with a counter, and
• shift operation is implemented with a shift register.

The type of operations most often encountered in digital systems can be classified into four categories:

1. Transfer operations, which transfer (i.e., copy) data from one register to another.
2. Arithmetic operations, which perform arithmetic (e.g., multiplication) on data in registers.
3. Logic operations, which perform bit manipulation (e.g., logical OR) of non-numeric data in registers.
4. Shift operations, which shift data between registers.
 Register Transfer Level Notations
A = 1010 and B = 0000,
Self Study
Binary information in Digital Systems:

Data
Control

Data processing tasks

Addition, decoding, counting etc

Control information provides command signals for

monitoring data processing tasks.

Various modules are interconnected to form digital system

Logic Design

Design of Data processing circuits

Design of control circuits

Control sequence and data processing tasks are specified by
means of Hardware Algorithm.

A Special Flowchart developed to design Digital hardware

algorithms is called Algorithmic State Machine ( ASM) chart
A conventional flowchart describes sequence of
procedural steps without concern for their time relationship

An ASM chart describes the sequence of events as well as the

timing relationship between states of sequential controller
ASM CHART
Composed of three basic elements

The State box

The decision box

The conditional box

A state is indicated by the state box within which

register operations are written

Or

the output signal names that the control

generates while being in the state

The state is given a symbolic name, binary code

assigned to state
Start name may indicate an output signal that
Starts an operation
✓ Decision box indicates the effect of an input on the control
subsystem

✓ Input condition to be tested is written inside the box

✓ One exit path is taken if the condition is true and another if false
✓ The conditional box in unique to ASM chart

✓ Input path to conditional box comes from one of exit paths

of a decision box

✓ The register operations or outputs listed inside a conditional

box are generated during a given state provided the input
condition is satisfied.
ASM Block

➢ A structure consisting of one state box and all the

decision and conditional boxes connected to its exit path.

➢ An ASM block has one entrance and any number of exit

paths represented by the structure of the decision boxes
✓ Each block in the ASM chart describes the state of the system
during one clock pulse interval

✓ The operations within the state and conditional boxes are executed
with a common clock pulse while the system is in state T1.

✓ The same clock pulse also transfers the system controller to one of
the next states.

✓ ASM chart is very similar to state diagram.

✓Major difference between a conventional flowchart and an ASM
chart is interpreting the timing relations.

✓Conventional flowchart the listed operations follow one after the

other in time sequence.

✓ASM chart consider the entire block as one unit.

✓All operations within a block must occur in synchronism during

clock edge.
During transition
A is incremented, If E = 1 , R is cleared
Depending on values of EF control transferred to T2 or T3 or T4
Design Example

Design a Digital system with two FFs E and F, one

4-bit binary counter A (A4A3A2A1). A start signal S
initiates the system operation by clearing counter A
and flip-flop F. Counter incremented by one starting
from next clock pulse, continues to increment until
operations stop.
If A3 = 0, E is cleared to 0 and count continues
If A3 = 1, E set to 1; then if A4=0, count continues,
but if A4 = 1, F set to 1 on next clock pulse and system
stops counting. If S = 0 system remains in initial state,
but if S = 1 operation cycle repeats.
Design a Digital system with two FFs
E and F, one 4-bit binary counter A
(A4A3A2A1). A start signal S initiates
the system operation by clearing
counter A and flip-flop F.
Counter incremented by one starting
from next clock pulse, continues to
increment until operations stop.

If A3 = 0, E is cleared to 0 and count

continues
If A3 = 1, E set to 1; then if A4 = 0,
count continues,
but if A4 = 1, F set to 1 on next clock
pulse and system stops counting. If S
= 0 system remains in initial state,
but if S = 1 operation cycle repeats.
When no operations the system in initial state T0
waiting for S

When input S = 1, counter A and flip-flop F

cleared
Counter goes to state T1

Block with T1 has two decision and two

conditional boxes

Counter incremented with every clock pulse, at

the same time
One of three operations occur during clock
transition

Either E cleared and control stays in T1 ( A3 = 0);

or
E is set and control stays in T1 ( A3A4 = 10); or
E is set and control goes to T2 ( A3A4 = 11).

When in T2 F is set and circuit goes to T0.

✓Every block in the ASM chart specifies the operations
performed during one common clock pulse.

✓Operations specified within the state and conditional

boxes in the block are performed in the datapath section.

✓The change from one state to next is performed in the

control section.
A4 A3 A2 A1

A3 = 0, A4 = 0
T1

A3 = 1, A4 = 0

A3 = 0, A4 = 1

A3 = 1, A4 = 1
T2
T0
✓ The requirements of design of the datapath are
specified inside the state and conditional boxes

✓ Control logic is determined by the decision boxes

and required state transitions.
Data path consists of
-4 bit binary counter
-Two flip-flops
-Gates

Counter is incremented with every clock cycle

when control is in state T1.
Cleared when control is in state T0 and S is equal
to 1. - uses an AND gate

The other two conditional operations use two

other AND gates for setting or clearing E.
F is set unconditionally during T2.
State Table:

Present-State Present Inputs Next Outputs

State State
Symbol G1 G0 S A3 A4 G1 G0 T0 T1 T2

T0 0 0 0 X X 0 0 1 0 0
T0 0 0 1 X X 0 1 1 0 0
T1 0 1 X 0 X 0 1 0 1 0
T1 0 1 X 1 0 0 1 0 1 0
T1 0 1 X 1 1 1 1 0 1 0
T2 1 1 X X X 0 0 0 0 1
State Table:

Present-State Present Inputs Next Outputs

State State
Symbol G1 G0 S A3 A4 G1 G0 T0 T1 T2

T0 0 0 0 X X 0 0 1 0 0
T0 0 0 1 X X 0 1 1 0 0
T1 0 1 X 0 X 0 1 0 1 0
T1 0 1 X 1 0 0 1 0 1 0
T1 0 1 X 1 1 1 1 0 1 0 Design Using D FFs.
T2 1 1 X X X 0 0 0 0 1
Flip-flop Inputs
DG1 = T1A3A4

DG0 = T0S +T1

Output Functions

T0 = G0’
T1 = G1’G0
T2 = G1
Flip-flop Inputs
DG1 = T1A3A4
DG0 = T0S +T1

Output Functions
T0 = G0’
T1 = G1’G0
T2 = G1
▪ This section introduces a second design example.

▪ It presents a hardware algorithm for binary multiplication, proposes

the register configuration for its implementation, and

▪ then shows how to use an ASMD chart to design its datapath and its
controller.

▪ The system we will examine multiplies two unsigned binary

numbers.

▪ The hardware developed in Section 4.7 to execute multiplication

resulted in a combinational circuit multiplier with many adders
and AND gates, and requires large area of silicon as an integrated
circuit.
▪ The multiplication of two binary numbers is done with paper ▪ The process consists of successively adding and shifting
and pencil by successive (i.e., sequential) additions and copies of the multiplicand.
shifting.
▪ Successive bits of the multiplier are examined, least
▪ The process is best illustrated with a numerical example. significant bit first.

▪ Let us multiply the two binary numbers 10111 and 10011: ▪ If the multiplier bit is 1, the multiplicand is copied
down; otherwise, 0’s are copied down.

▪ The numbers copied in successive lines are shifted one

position to the left from the previous number.

d ▪ Finally, the numbers are added and their sum forms the
product.

▪ The product obtained from the multiplication of two

binary numbers of n bits each can have up to 2 n bits.

▪ It is apparent that the operations of addition and shifting

are executed by the algorithm.
▪ When the multiplication process is implemented with digital hardware, it is convenient to change the process slightly.

▪ First, we note that, in the context of synthesizing a sequential machine, the add‐and‐shift algorithm for binary
multiplication can be executed in a single clock cycle or over multiple clock cycles.

▪ A choice to form the product in the time span of a single clock cycle will synthesize the circuit of a parallel multiplier
like the one discussed in Section 4.7.

▪ On the other hand, an RTL model of the algorithm adds shifted copies of the multiplicand to an accumulated partial
product.

▪ The values of the multiplier, multiplicand, and partial product are stored in registers, and the operations of shifting and
adding their contents are executed under the control of a state machine.

▪ Among the many possibilities for distributing the effort of multiplication over multiple clock cycles, we will consider
that in which only one partial product is formed and accumulated in a single cycle of the clock. (
▪ Instead of providing digital circuits to store and add simultaneously as many binary numbers as there are 1’s in
the multiplier, it is less expensive to provide only the hardware needed to sum two binary numbers and
accumulate the partial products in a register.

▪ Second, instead of shifting the multiplicand to the left, the partial product being formed is shifted to the right.
This leaves the partial product and the multiplicand in the required relative positions.

▪ Third, when the corresponding bit of the multiplier is 0, there is no need to add all 0’s to the partial product, since
doing so will not alter its resulting value.
▪ A block diagram for the sequential binary multiplier is
shown in Fig. 8.14 (a), and the register configuration of the
datapath is shown in Fig. 8.14 (b).

▪ The multiplicand is stored in register B, the multiplier is

stored in register Q, and the partial product is formed in
register A and stored in A and Q .

▪ A parallel adder adds the contents of register B to register A .

▪ The C flip‐flop stores the carry after the addition. The

counter P is initially set to hold a binary number equal to the
number of bits in the multiplier.

▪ This counter is decremented after the formation of each

partial product.

▪ When the content of the counter reaches zero, the product is

formed in the double register A and Q, and the process stops.
▪ The control logic stays in an initial state until Start becomes
1.

▪ The system then performs the multiplication. The sum of A

and B forms the n most significant bits of the partial product,
which is transferred to A .

▪ The output carry from the addition, whether 0 or 1, is

transferred to C .

▪ Both the partial product in A and the multiplier in Q are

shifted to the right. The least significant bit of A is shifted
into the most significant position of Q, the carry from C is
shifted into the most significant position of A, and 0 is
shifted into C .

▪ After the shift‐right operation, one bit of the partial product

is transferred into Q while the multiplier bits in Q are shifted
one position to the right.

▪ In this manner, the least significant bit of register Q,

designated by Q[0], holds the bit of the multiplier that must
be inspected next.
▪ The control logic determines whether to add or not on the basis of
this input bit.

▪ The control logic also receives a signal, Zero, from a circuit that
checks counter P for zero.

▪ Q[0] and Zero are status inputs for the control unit.

▪ The input signal Start is an external control input.

▪ The outputs of the control logic launch the required operations in

the registers of the datapath unit.

▪ The interface between the controller and the datapath consists of

the status signals and the output signals of the controller.

▪ The control signals govern the synchronous register operations of

the datapath.

▪ Signal Load_regs loads the internal registers of the datapath,

Shift_regs causes the shift register to shift, Add_regs forms the
sum of the multiplicand and register A, and Decr_P decrements
the counter.
▪ The controller also forms output Ready to signal to the host
environment that the machine is ready to multiply.

▪ The contents of the register holding the product vary during

execution, so it is useful to have a signal indicating that its
contents are valid.

▪ Note, again, that the state of the control is not an interface signal
between the control unit and the datapath.

▪ Only the signals needed to control the datapath are included in the
interface.

▪ Putting the state in the interface would require a decoder in the

datapath, and would require a wider and more active bus than the
control signals alone. Not good.
▪ The ASMD chart for the binary multiplier is shown
in Fig. 8.15 .

▪ The intermediate form in Fig. 8.15 (a) annotates the

ASM chart of the controller with the register
operations, and

▪ the completed chart in Fig. 8.15 (b) identifies the

Moore and Mealy outputs of the controller.

▪ Initially, the multiplicand is in B and the multiplier

in Q .

▪ As long as the circuit is in the initial state and Start

= 0, no action occurs and the system remains in
state S_idle with Ready asserted.

▪ The multiplication process is launched when Start =

1.
▪ The multiplication process is launched when Start = 1.

▪ Then, (1) control goes to state S_add, (2) register A and carry flip‐flop C are cleared
to 0, (3) registers B and Q are loaded with the multiplicand and the multiplier,
respectively, and (4) the sequence counter P is set to a binary number n, equal to the
number of bits in the multiplier.

▪ In state S_add, the multiplier bit in Q[0] is checked, and if it is equal to 1, the
multiplicand in B is added to the partial product in A . The carry from the addition is
transferred to C . The partial product in A and C is left unchanged if Q[0] = 0.

▪ The counter P is decremented by 1 regardless of the value of Q[0], so Decr_P is

formed in state S_add as a Moore output of the controller. In both cases, the next
state is S_shift .

▪ Registers C, A, and Q are combined into one composite register CAQ, denoted by the
concatenation { C, A, Q }, and its contents are shifted once to the right to obtain a
new partial product.

▪ This shift operation is symbolized in the flowchart with the Verilog logical right‐shift
operator, >>. It is equivalent to the following statement in register transfer notation:
▪ In terms of individual register symbols, the shift operation can be described by the
following register operations:

▪ Both registers A and Q are shifted right. The leftmost bit of A, designated by An-1 ,
receives the carry from C . The leftmost bit of Q, Qn-1 , receives the bit from the
rightmost position of A in A0 , and C is reset to 0.

▪ In essence, this is a long shift of the composite register CAQ with 0 inserted into
the serial input, which is at C .

▪ The value in counter P is checked after the formation of each partial product. If the
contents of P are different from zero, status bit Zero is set equal to 0 and the
process is repeated to form a new partial product.

▪ The process stops when the counter reaches 0 and the controller’s status input Zero
is equal to 1.

▪ Note that the partial product formed in A is shifted into Q one bit at a time and
eventually replaces the multiplier.

▪ The final product is available in A and Q, with A holding the most significant bits
and Q the least significant bits of the product.
Table 8.5 to clarifies the multiplication process. The procedure follows the steps
outlined in the ASMD chart.
▪ The type of registers needed for the data processor subsystem can be derived
from the register operations listed in the ASMD chart.

▪ Register A is a shift register with parallel load to accept the sum from the
adder and must have a synchronous clear capability to reset the register to 0.

▪ Register Q is a shift register.

▪ The counter P is a binary down counter with a facility to parallel load a

binary constant.

▪ The C flip‐flop must be designed to accept the input carry and have a
synchronous clear.

▪ Registers B and Q need a parallel load capability in order to receive the

multiplicand and multiplier prior to the start of the multiplication process.
▪ The design of a digital system can be divided into two parts: (1) the design of the
register transfers in the datapath unit and (2) the design of the control logic of the
control unit.

▪ The control logic is a finite state machine; its Mealy‐ and Moore‐type outputs
control the operations of the datapath.

▪ The inputs to the control unit are the primary (external) inputs and the internal
status signals fed back from the datapath to the controller.

▪ The design of the system can be synthesized from an RTL description derived from
the ASMD chart.

▪ Alternatively, a manual design must derive the logic governing the inputs to the
flip‐flops holding the state of the controller.

▪ The information needed to form the state diagram of the controller is already
contained in the ASMD chart, since the rectangular blocks that designate state
boxes are the states of the sequential circuit.

▪ The diamond‐shaped blocks that designate decision boxes determine the logical
conditions for the next state transition in the state diagram and assertions of the
conditional outputs.
✓ The register transfer operations for each of the three states are listed in Fig. 8.16 (b)
and are taken from the corresponding state and conditional boxes in the ASMD chart.

✓ Establishing the state transitions is the initial focus, so the outputs of the controller
are not shown.
▪ We must execute two steps when implementing the control logic: (1) establish the
required sequence of states, and (2) provide signals to control the register
operations.

▪ The sequence of states is specified in the ASMD chart or the state diagram.

▪ The signals for controlling the operations in the registers are specified in the
register transfer statements annotated on the ASMD chart or listed in tabular
format.

▪ For the multiplier, these signals are Load_regs (for parallel loading the registers in
the datapath unit), Decr_P (for decrementing the counter), Add_regs (for adding the
multiplicand and the partial product), and Shift_regs (for shifting register CAQ ).

▪ The block diagram of the control unit is shown in Fig. 8.14 (a).

▪ The inputs to the controller are Start, Q[0], and Zero, and the outputs are Ready,
Load_regs, Decr_P, Add_regs, and Shift_regs, as specified in the ASMD chart.

▪ We note that Q[0] affects only the output of the controller, not its state transitions.
The machine transitions from S_add to S_shift unconditionally.
▪ An important step in the design is the assignment of coded binary values to the
states

▪ Indeed, one‐hot encoding uses more flip‐flops than other types of coding, but it
usually leads to simpler decoding logic for the next state and the output of the
machine.

▪ Because the decoding logic does not become more complex as states are added to
the machine, the speed at which the machine can operate is not limited by the time
required to decode the state.
▪ Since the controller is a sequential circuit, it can be designed manually by the sequential logic procedure outlined in
Chapter 5 .

▪ However, in most cases this method is difficult to carry out manually because of the large number of states and
inputs that a typical control circuit may have.

▪ As a consequence, it is necessary to use specialized methods for control logic design that may be considered as
variations of the classical sequential logic method.

▪ We will now present two such design procedures.

✓ One uses a sequence register and decoder, and
✓ the other uses one flip‐flop per state.

▪ The method will be presented for a small circuit, but it applies to larger circuits as well.

▪ Of course, the need for these methods is eliminated if one has software that automatically synthesizes the circuit
from an HDL description.
Thank You