Static MOS Gate Circuits

CHAPTER 5
Kyeong-Sik Min, Kookmin University
Outline
 Introduction
 CMOS gate
 Complex gate
 XOR and XNOR
 Multiplexer
 FFs and latches
 Power dissipation
 P
Power andd delay
d l tradeoffs
d ff
 Summary
Introduction
 In chapter 4, we learned about MOS inverters.
 Here in chapter
p 5,, we will expand
p our studyy from
the inverter to all logic gates of combinational and
sequential
q circuits.
 What is difference between the combinational and
sequential?
 Power-delay tradeoffs are the most important
metric
i in
i di
digital
i l VLSI design
d i
CMOS NOR and NAND gates
 How do they work?
 What is fan-in?
 Need to notice that all the channel lengths are the
same.
same
CMOS Gate sizing
 PMOS size is twice larger than NMOS.
 Why y is PMOS larger
g than NMOS?
 At first, we decide inverter sizing and than expand
to more complex gates.
gates
Cont.
Sizing for pseudo
pseudo-NMOS
NMOS gates
 Ratioed logic
Layout and equivalent size of 3x

Weq  W1 || W2 || W3 (for series, all devices on)

Weq  W1  W2  W3 (for parallel,
parallel all devices on)
Fanin and fanout
 Fanin is 8
 Resistance of 8 stacks is
very large
 Not to use fanin number
larger than 4
 F i b
Fanin beyondd 4 will
ill be
b
very slow
 Self-capacitance
DeMorgan’ss law
DeMorgan

a  b   a  b
a  b   a  b
Pseudo NMOS gate with 8 fanin
 Compare to CMOS 8-
fanin gate, this area is
greatly reduced
 tPHL is fast
 tPLH is very slow
 St ti currentt di
Static dissipation
i ti
in holding its output low
Multi-level
Multi level logic implementation
 In terms off delay, this is
much better than 8-fanin
CMOS and d pseudo-NMOS
d NMOS
gates
 Th area is
The i larger
l than
h
pseudo-NMOS logic
 A
Area, power, andd delay
d l
are things to be
considered
id d in i digital
di it l circuit
i it
design
Fanout
 Fanout is the number of
identical logic gates
driven by it
 Delayy of logic
g gate
g is
usually given by a
function of fanout
VTC of CMOS gates
Complex gate
 /(A+B)C
ab  a  b
(a  b)c  ab  c
F  ( a  b)  c  ( a  b)  c  a  b  c
Generalized complex gate
 P-complex and n-complex have relationship of
duality
Cont.
XOR and XNOR

f XOR  a b  a b
f XNOR  a b  ab
MUX
 Many different ways of
implementing MUX
 Transmission gate can
also be used in
implementing MUX
Latches and flip
flip-flops
flops
 Latch and FF are storages for data in digital VLSI
 Latch and FF are p parts of sequential
q logic
g
 Latch is level-triggered
 FF is
i edge-triggered
d ti d
 In terms of timing margin, FF is more stable and
marginal than latch
Basic bi
bi-stable
stable circuit
 We can see three bias points of A, B, and C
 Bi-stable circuit can not be stable at the C in real
situation (C is only seen at the simulation)
SR latch with NOR
 Bi-stable with set and reset inputs
 When S=1 and R=1,, Q and //Q
are the same
 We need to avoid this case
because Q is not /Q in this case
Cont.
SR latch with NAND
 Very similar with SR latch
with NOR
JK flip
flip-flop
flop
 JK ff avoids the case
of both set and reset
being activated in the
SR latch
 When J=1 and K=1
and clock is high, Q
becomes /Q and then
Q again. This is called
oscillation.
JK master
master-slave
slave flip
flip-flop
flop
 There is no oscillation even though clock is kept high
 Master ppart is driven byy clock and slave part
p is
driven by /clock
 Falling-edge driven
JK edge
edge-triggered
triggered ff
D latch and ff
 (a) truth table
 ((b)) transparent
p D latch
 (c) edge-triggered D flip-
flop
D Latch operation
 Transparent
 opaque
p q
FF operation
 Edge-triggered or sampled
Flip-flop
Flip flop timing parameters
Latch timing parameters
Gate level realization of D latch
Power dissipation
 Dynamic (switching and short-circuit)
 Static ((leakage,
g , bias,, etc))
 Dynamic power at pull
pull-up
up
35

VDD
on

IN
ESUPPLY=C*VDD2
ESTORE=0
0.5 C VDD2
5*C*V
C
EDISSIPATED=0.5*C*VDD
off 2

VSS

• Energy is dissipated only at PMOS switch.

 Dynamic power at pull
pull-down
down
36

VDD
off ESUPPLY=0
ESTORED=0
EDISSIPATED=0.5*C*VDD2
IN
C
on
VSS

• Energy is dissipated only at NMOS switch.

 Further thinking
37

 When ‘On’ resistance of ideal transistor becomes

zero, can energy be consumed at zero resistance?
 Gate capacitance
38

- Components of Cg:
Cg=Cchannel + 2 Coverlap
=(Leff+2*Loverlap)*ox/Tox
- How to optimize Cgate:
- Observation:
1) Cchannel determines the drain current.
-> We cannot arbitrarily decrease Cchannel.
2) Coverlap do
d not contribute
ib to the
h ddrain
i current.

- Methods:
1) Reduce the overlap length by using very shallow and
abrupt S/D extension or thick side wall spacer.
 Junction capacitance
39

Cdj  C jb AD  C jsw PD
Vdd
1 C jb 0
C jb 
Vdd   Vj 
mj
dV j
1  V 
0

 b
V
1 dd C jsw0
C jsw  
Vdd 0  V j  mjsw
dV j
1  V 
 b
 Miller capacitance
40

Miller capacitance
Cout
Cov,d: overlap at drain
Cov,s: overlap at source
Cg: gate-oxide
gate oxide
Cj,d: junction at drain
Cj,s: junction at source
Cin

Cout=Cj,d+2*Cov,d
Cin=Cg+Cov,s+2*Cov,d
 Interconnect capacitance
41

 W  W 
0.25
  
T
0 .5

C wl      0 . 77  1 . 06   1.06  
 H  H  H  
Dynamic power dissipation
Cont.
 Alpha: activity factor

dV C L Vswing
I D ,avg  C   C LVDD f avg
dt t
Pswitchingg  I D ,avggVDD  C LVDD f avgg
2

Pswitching   0  1C LVDD f avg

2
Short-circuit
Short circuit power
Cont.

t sc  t scr  t scf
Psc  I scVDD
t sc
I sc  I sc ,avg
T
t sc
Psc  I sc ,avggVDD  t sc I sc ,avggVDD f clk
T
if we set t sc I sc ,avg  CscVDD
Psc  CscVDD f clk
2

if switching activity factor for short - circuit current is  sc

Psc   sc CscVDD f clk
2
Glitch at NOR
 10% of dynamic
power is glitch power
 How can we reduce
glitch power?
g p
Leakage vs. switching power
Cont.
 Various leakage current mechanisms of deep
submicron transistors
Gate
I7, I8
Source Drain

n+ n+
I2, I3, I6
I5 I1 p well
p-well

I4
Well
Cont.
 I1: p-n junction reverse bias current
 I2: weak inversion
 I3: DIBL (drain-induced barrier lowering)
 I4 GIDL (G
I4: (Gate-induced
t i d dd drain
i leakage)
l k )
 I5: punch-through
 I6: narrow width effect
 I7: gate oxide tunneling
 I8: hot-carrier injection
Power-delay
Power delay product

PDP  Pavg t P
Pavg  C VDD f
2

1
tP 
2f
2
1 C VDD
PDP  C VDD f 
2

2f 2
  VDD
dv (t )
EC   ic (t )vout (t )dt   C out vout (t )dt   cv out (t )dvout
0 0
dt 0
2
C VDD

2
Energy-delay
Energy delay product

EDP  PDP  t p
dV
I C
dt
CV
t 
I
CV CVDD
tp  
I sat K (VDD  VT )
3
C 2VDD
EDP 
2 K (VDD  VT )
Cont.
 Energy-delay product vs. supply voltage

EDP
0
VDD
3
 VT
*
VDD
2