A Complete Datapath for -R Type Instructions What Else is Needed in Data Path

• Lw, Sw, Add, Sub, And, Or, Slt can be performed • Support for j and jr
• For j (jump) we need an additional multiplexor
– For both of them PC value need to come from somewhere else
PCSrc
– For J, PC is created by 4 bits (31:28) from old PC, 26 bits from IR
1
Add M
u
(27:2) and 2 bits are zero (1:0)
x
ALU
4 Add result 0
– For JR, PC value comes from a register
RegWrite Shift
left 2
• Support for JAL
Instruction [25–21] Read
PC Read register 1 Read
data 1
MemWrite – Address is same as for J inst
address Instruction [20–16] Read MemtoReg
ALUSrc
register 2 Zero
Instruction
[31–0] 1 Read
1 ALU ALU
– OLD PC needs to be saved in register 31
Write data 2 result Address Read 1
M register M data
u
Instruction
memory
Instruction [15–11] x Write u
x
M
u • And what about immediate operand instructions
0 data Registers 0
x
Write Data 0
– Second operand from instruction, but without shifting
RegDst data memory
Instruction [15–0] 16 Sign 32
extend ALU MemRead • Support for other instructions like lw and immediate inst write
control
Instruction [5–0]

ALUOp

1 2

Control Adding Control to DataPath

0
M
u
x

• For each instruction Add ALU

result
1
Add Shift

– Select the registers to be read (always read two) 4

RegDst
Branch
left 2

MemRead

– Select the 2nd ALU input Instruction [31– 26]

Control
MemtoReg
ALUOp
MemWrite
– Select the operation to be performed by ALU ALUSrc
RegWrite

– Select if data memory is to be read or written PC

Read
Instruction [25– 21] Read
register 1 Read
address
Instruction [20– 16] Read data 1
– Select what is written and where in the register file Instruction
[31– 0]
0
register 2
Registers Read
0
ALU
Zero
ALU
M Write data 2 result Address Read 1
Instruction u register M data
– Select what goes in PC memory
Instruction [15– 11]
1
x
Write
u
x Data
M
u
x
data 1 memory 0
Write
• Information comes from the 32 bits of the instruction data
16 32
Instruction [15– 0] Sign

• Example: extend ALU

control

add $8, $17, $18 Instruction Format: Instruction [5– 0]

000000 10001 10010 01000 00000 100000

Memto- Reg Mem Mem
Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0
op rs rt rd shamt funct R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 0 1 0 1
3 4

Our Simple Control Structure ALU Control

• All of the logic is combinational • ALU's operation based on instruction type and function code
– e.g., what should the ALU do with any instruction
• We wait for everything to settle down, and the right thing to be done • Example: lw $1, 100($2)
– ALU might not produce “right answer” right away
•
– we use write signals along with clock to determine when to write 35 2 1 100
• Cycle time determined by length of the longest path
op rs rt 16 bit offset

State State
• ALU control input
element Combinational logic element
1 2
000 AND
001 OR
010 add
Clock cycle
110 subtract
111 set-on-less-than

• Why is the code for subtract 110 and not 011?

We are ignoring some details like setup and hold times

5 6
Other Control Information Implementation of Control

• Must describe hardware to compute 3-bit ALU conrol input • Simple combinational logic to realize the truth tables
– given instruction type Inputs
00 = lw, sw ALUOp Op5
01 = beq, computed from instruction type Op4
ALUOp Op3
10 = arithmetic Op2
ALUcontrol block
11 = Jump ALUOp0
Op1
Op0
– function code for arithmetic ALUOp1
• Control can be described using a truth table: Outputs

Operation2 R-format Iw sw beq

RegDst
F3
ALUOp Funct field Operation ALUSrc
Operation
ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0 F2 Operation1 MemtoReg
F (5–0)
0 0 X X X X X X 010 RegWrite
F1
X 1 X X X X X X 110 Operation0 MemRead
MemWrite
1 X X X 0 0 0 0 010 F0
Branch
1 X X X 0 0 1 0 110 ALUOp1
1 X X X 0 1 0 0 000 ALUOpO
1 X X X 0 1 0 1 001
1 X X X 1 0 1 0 111
7 8

A Complete Datapath with Control Datapath with Control and Jump Instruction

9 10

Timing: Single Cycle Implementation Where we are headed

• Calculate cycle time assuming negligible delays except: • Single Cycle Problems:
– memory (2ns), ALU and adders (2ns), register file access (1ns) – what if we had a more complicated instruction like floating point?
PCSrc – wasteful of area
1
M
• One Solution:
Add u
4 ALU
x
0
– use a “smaller” cycle time
Add result
RegWrite Shift – have different instructions take different numbers of cycles
left 2

Instruction [25– 21]

– a “multicycle” datapath:
Read
Read register 1 Read MemWrite
PC data 1
address Instruction [20– 16] Read MemtoReg
ALUSrc
Instruction register 2 Zero
1 Read ALU ALU
[31– 0] Write data 2 1 Read Instruction
M result Address 1
u register M data register
Instruction Instruction [15– 11] x u M Data
memory Write x u PC Address
0 data Registers x A
0
Write Data 0 Register #
RegDst data memory Memory
Instruction
Registers ALU ALUOut
Instruction [15– 0] 16 Sign 32 or data
extend Memory Register #
ALU MemRead
control data B
Data register Register #
Instruction [5– 0]

ALUOp

11 12
Instruction Format Operation for Each Instruction

LW: SW: R-Type: BR-Type: JMP-Type:

31 26 25 21 20 16 15 11 10 6 5 0

LW REG 1 REG 2 LOAD ADDRESS OFFSET 1. READ INST 1. READ INST 1. READ INST 1. READ INST 1. READ

31 26 25 21 20 16 15 11 10 6 5 0 INST
SW REG 1 REG 2 STORE ADDRESS OFFSET 2. READ REG 1 2. READ REG 1 2. READ REG 1 2. READ REG 1 2.

31 26 25 21 20 16 15 11 10 6 5 0 READ REG 2 READ REG 2 READ REG 2 READ REG 2

R-TYPE REG 1 REG 2 DST SHIFT AMOUNT ADD/AND/OR/SLT 3. ADD REG 1 + 3. ADD REG 1 + 3. OPERATE on 3. SUB REG 2 3.
OFFSET OFFSET REG 1 / REG 2 from REG 1
31 26 25 21 20 16 15 11 10 6 5 0
4. READ MEM 4. WRITE MEM 4. 4.
BRANCH ADDRESS OFFSET
4.
BEQ/BNE REG 1 REG 2

31 26 25 21 20 16 15 11 10 6 5 0
5. WRITE REG2 5. 5. WRITE DST 5.
JUMP
5.
JUMP ADDRESS

13 14

Multicycle Approach Review: finite state machines

• We will be reusing functional units • Finite state machines:

– Break up the instruction execution in smaller steps – a set of states and
– Each functional unit is used for a specific purpose in one cycle – next state function (determined by current state and the input)
– output function (determined by current state and possibly input)
– Balance the work load
– ALU used to compute address and to increment PC
– Memory used for instruction and data Next
state
• At the end of cycle, store results to be used again Current state
Next-state
function

– Need additional registers Inputs

Clock

• Our control signals will not be determined solely by instruction

Output
– e.g., what should the ALU do for a “subtract” instruction? function
Outputs

• We’ll use a finite state machine for control – We’ll use a Moore machine (output based only on current state)

15 16

Multi- Cycle DataPath Operation Five Execution Steps

• Instruction Fetch
M
U
25-00 X
• Instruction Decode and Register Fetch
PC 25-21 M
M RA1 A
RD1 U
R
U I 20-16
RA2 REG X • Execution, Memory Address Computation, or Branch Completion
X R A
FILE ALU
L
M B M U
U WA WD
RD2
R 4
U
• Memory Access or R-type instruction completion
Add X
X
15-11 BR
MEM Data
D COND • Write-back step
Out 15-00 Sign Shift
R Ext Left 2 ALU BNE
Data In M
CON BEQ
U 05-00
X INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!
ALUOP JUMP

31-26
CONTROL

17 18
Step 1: Instruction Fetch Step 2: Instruction Decode and Register Fetch

• Use PC to get instruction and put it in the Instruction Register. • Read registers rs and rt in case we need them
• Increment the PC by 4 and put the result back in the PC. • Compute the branch address in case the instruction is a branch
• Can be described succinctly using RTL "Register-Transfer Language" • RTL:

IR = Memory[PC]; A = Reg[IR[25-21]];
PC = PC + 4; B = Reg[IR[20-16]];
ALUOut = PC + (sign-extend(IR[15-0]) << 2);
Can we figure out the values of the control signals?
• We aren't setting any control lines based on the instruction type
What is the advantage of updating the PC now? (we are busy "decoding" it in our control logic)

19 20

Step 3 (instruction dependent) Step 4 (R

- type or memory
- access)

• ALU is performing one of three functions, based on instruction type • Loads and stores access memory

• Memory Reference: MDR = Memory[ALUOut];

or
ALUOut = A + sign-extend(IR[15-0]); Memory[ALUOut] = B;

• R-type:
• R-type instructions finish
ALUOut = A op B;
Reg[IR[15-11]] = ALUOut;
• Branch:

if (A==B) PC = ALUOut; The write actually takes place at the end of the cycle on the edge

21 22

Write
- back step Summary:

• Reg[IR[20-16]]= MDR;
Action for R-type Action for memory-reference Action for Action for
What about all the other instructions? Step name instructions instructions branches jumps
Instruction fetch IR = Memory[PC]
PC = PC + 4
Instruction A = Reg [IR[25-21]]
decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)
Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] II
computation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)
jump completion
Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]
completion ALUOut or
Store: Memory [ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] = MDR

23 24