Decoder

• Discrete quantities of information are represented in digital

systems with binary codes.
• A binary code of n bits is capable of representing up to 2n
distinct elements of the coded information.
• A decoder is a combinational circuit that converts binary
information from n input lines to a maximum of 2n unique
output lines.
• If the n-bit decoded information has unused or don’t-care
combinations, the decoder output will have less than 2n outputs.
• The decoders presented here are called n-to-m line decoders
where m ≤ 2n Their purpose is to generate the 2n (or less)
minterms of n input variables.
• A decoder get a set of binary inputs and activates only the output that a
complement to that input number. A demultiplexer is a circuit that gets data
on a single line and sends this data on one of several output lines. It can be
used for decoding the encoded input terminal.
 Decoder
consider the 3-to-8 line decoder circuit of Fig. 5-8. The
Ex.
three inputs are decoded into eight outputs, each
output representing one of the minterms of the 3-input
variables.
• The three inverters provide the complement of the
inputs, and each one of the eight AND gates generates
one of the minterms. A particular application of this
decoder would be a binary-to octal conversion.
• The input variables may represent a binary number,
and the outputs will then represent the eight digits in
the octal number system.
• However, a 3-to-8 line decoder can be used for
decoding any 3-bit code to provide eight outputs, one
for each element of the code.
 Decoder
• Observe -output variables are mutually exclusive because only
one output can be equal to 1 at any one time.
• The output line whose value is equal to 1 represents the
minterm equivalent of the binary number presently available
in the input lines.
Decoder
 Decoder
EXAMPLE 5-2: Design a BCD-to-decimal decoder.
• The elements of information in this case are the ten decimal digits
represented by the BCD code. The code itself has four bits.
Therefore, the decoder should have four inputs to accept the
coded digit and ten outputs, one for each decimal digit. This will
give a 4-line to 10-line BCD-to-decimal decoder.
• Since the circuit has ten outputs, it would be necessary to draw
ten maps to simplify each one of the output functions.
• There are six don’t-care conditions here, and they must be taken
into consideration when we simplify each of the output functions.
Instead of drawing ten maps, we will draw only one map and
write each of the output variables, D0 to D9, inside its
corresponding minterm square as shown in Fig. 5-9. Six input
combinations will never occur, so we mark their corresponding
minterm squares with X’s.
 Decoder
EXAMPLE 5-2: Design a BCD-to-decimal decoder.
• But An analysis of the circuit of Fig. 5-10 shows that the six invalid
input combinations will produce outputs as listed in Table 5-3.
The reader can look at the table and decide whether this is a good
or bad design.
 Decoder
EXAMPLE 5-2: Design a BCD-to-decimal decoder.
• Using the don’t-care terms for the other outputs, we obtain the circuit shown
in Fig. 5-10. Thus the don’t-care terms cause a reduction in the number of
inputs in most of the AND gates.
 Decoder
EXAMPLE 5-2: Design a BCD-to-decimal decoder.
• It is the designer’s responsibility to decide on how to treat the
don’t-care conditions. Assume that it is decided to use them in
such a way as to simplify the functions to the minimum combined
with the don’t care minterm m10 to give:
D2 = x’yz’
• The square with D9 can be combined with three other don’t-care
squares to give:
D9 = wz
Using the don’t-care terms for the other outputs, we obtain the
circuit shown in Fig. 5-10. Thus the don’t-care terms cause a
reduction in the number of inputs in most of the AND gates.
 Decoder
• EXAMPLE 5-2: Design a BCD-to-decimal decoder.

LSB

MSB
 Decoder
EXAMPLE 5-2: Design a BCD-to-decimal decoder.
• But An analysis of the circuit of Fig. 5-10 shows that the six invalid
input combinations will produce outputs as listed in Table 5-3.
The reader can look at the table and decide whether this is a
good or bad design.
 Decoder
EXAMPLE 5-3: Implement a full-adder circuit with a decoder and two OR gates.
• From the truth table of the full-adder (Section 4-3), we obtain
the functions for this combinational circuit in sum of
minterms:
S(x, y, z) = Σ(1, 2, 4, 7)
C(x, y, z,) = Σ(3, 5, 6, 7)
• Since there are three inputs and a total of eight minterms, we
need a 3-to-8 line decoder. The implementation is shown in Fig.
5-11. The decoder generates the eight minterms for x, y, z.
• The OR gate for output S forms the sum of minterms 1, 2, 4, and 7.
The OR gate for output C forms the sum of minterms 3, 5, 6, and 7.
• A function with a long list of minterms requires an OR gate with a
large number of inputs.
• A function F having a list of k minterms can be expressed in its
complemented form F′ with 2n - k minterms. If the number of
minterms in a function is greater than 2n /2, then F′ can be
expressed with fewer minterms than required for F. In such a
case, it is advantageous to use a NOR gate to sum the minterms of
F′. The output of the NOR gate will generate the normal output F.
 Decoder
EXAMPLE 5-3: Implement a full-adder circuit with a decoder and two OR gates.

Truth Table of Full adder

 Demultiplexers
• Some IC decoders are constructed with NAND gates. Since a NAND
gate produces the AND operation with an inverted output, it
becomes more economical to generate the decoder minterms in
their complemented form. Most, if not all, IC decoders include one
or more enable inputs to control the circuit operation.
• A 2-to-4 line decoder with an enable input constructed with
NAND gates is shown in Fig, 5-12. All outputs are equal to 1 if
enable input E is 1, regardless of the values of inputs A and B.
• When the enable input is 0, the circuit operates as a decoder with
complemented outputs. The truth table lists these conditions. The
X’s under A and B are don’t care conditions.
• Normal decoder operation occurs only with E = 0, and the outputs
are selected when they are in the 0 state.
Demultiplexers

More economical ,when o/

p is complemented
 Demultiplexers
• A decoder with an enable input can function as a demultiplexer.
A demultiplexer is a circuit that receives information on a
single line and transmits this information on one of 2 n
possible output lines.
• The selection of a specific output line is controlled by the bit
values of n selection lines. The decoder of Fig. 5-12 can function as
a demultiplexer if the E line is taken as a data input line and lines
A and B are taken as the selection lines. This is shown in Fig.
5-13(b).
• The single input variable E has a path to all four outputs, but the
input information is directed to only one of the output lines, as
specified by the binary value of the two selection lines A an
• The single input variable E has a path to all four outputs, but the
input information is directed to only one of the output lines, as
specified by the binary value of the two selection lines A and B.
• This can be verified from the truth table of this circuit, shown in
Fig. 5-12(b). For example, if the selection lines AB = 10, output D2
will be the same as the input value E, while all other outputs are
maintained at 1.
• Because decoder and demultiplexer operations are obtained from
Demultiplexers
 Demultiplexers
• Decoder/demultiplexer circuits can be connected together to form
a larger decoder circuit. Figure 5-14 shows two 3×8 decoders with
enable inputs connected to form a 4 × 16 decoder.
• When w = 0, the top decoder is enabled and the other is disabled.
The bottom decoder outputs are all 0’s, and the top eight outputs
generate minterms 0000 to 0111. When w = 1, the enable
conditions are reversed; the bottom decoder outputs generate
minterms 1000 to 1111, while the outputs of the top decoder are
all 0’s.
• This example demonstrates the usefulness of enable inputs in ICs.
In general, enable lines are a convenient feature for connecting
two or more IC packages
• for the purpose of expanding the digital function into a similar
function with more inputs and outputs.
Demultiplexers
 Encoders
• An encoder is a digital function that produces a reverse operation from that
of a decoder. An encoder has 2n (or less) input lines and n output lines. The
output lines generate the binary code for the 2n input variables.
• An example of an encoder is shown in Fig. 5-15. The octal-to-binary en coder
consists of eight inputs, one for each of the eight digits, and three outputs
that generate the corresponding binary number.
 Encoders
• DO input is not linked to any O R gate; the binary output must be all zeroes in
such case

MS
B

LSB
 Encoders
• It is constructed with OR gates whose inputs can be determined
from the truth table given in Table 5-4.
• The low-order output bit z is 1 if the input octal digit is odd.
Output y is 1 for octal digits 2, 3, 6, or 7. Output x is a 1 for octal
digits 4, 5, 6, or 7.
• Note that D0 is not connected to any OR gate; the binary output
must be all 0’s in this case.
 Encoders
• Note: Encoders of this type (Fig. 5-15) are not available in IC
packages, since they can be easily constructed with OR gates. The
type of encoder available in IC (IC type 74148. )form is called a
priority encoder These encoders establish an input priority to
ensure that only the highest-priority input line is encoded.
• Thus, in Table 5-4, if priority is given to an input with a higher
subscript number over one with a lower subscript number, then
if both D2 and D5 are logic-1 simultaneously, the output will be 101
because D5 has a higher priority over D2. Of course, the truth table
of a priority encoder is different from the one in Table 5-4
 Multiplexers
• Multiplexing means transmitting a large number of information
units over a smaller number of channels or lines.
• A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs
it to a single output line. The selection of a particular input
line is controlled by a set of selection lines. Normally, there
are 2 n input lines and n selection lines whose bit
combinations determine which input is selected.
 Multiplexers
• A 4-line to 1-line multiplexer is shown in Fig. 5-16. Each of the
four input lines, I0 to I3, is applied to one input of an AND gate.
Selection lines s1 and s0 are decoded to select a particular AND
gate.
• The function table in the figure lists the input-to-output path for
each possible bit combination of the selection lines. When this
MSI function is used in the design of a digital system, it is
represented in block diagram form as shown in Fig. 5-16(c).
• To demonstrate the circuit operation, consider the case when s1s0
= 10. The AND gate associated with input I2 has two of its inputs
equal to 1 and the third input connected to I2.
• The other three AND gates have at least one input equal to 0,
which makes their output equal to 0. The OR-gale output is now
equal to the value of I2, thus providing a path from the selected
input to the output. A multiplexer is also called a data selector,
since it selects one of many inputs and steers the binary
information to the output line.
Multiplexers
 Multiplexers
• As in decoders, multiplexer ICs may have an enable input to control the
operation of the unit. As in decoders, multiplexer ICs may have an enable
input to control the operation of the unit.
• When the enable input is in a given binary state, the outputs are disabled,
and when it is in the other state (the enable state), the circuit functions as a
normal multiplexer.
• The enable input (sometimes called strobe) can be used to expand two or
more multiplexer ICs to a digital multiplexer with a larger number of inputs.