24ec102 Unit - II

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24EC102 DIGITAL PRINCIPLES AND
SYSTEM DESIGN
(Lab Integrated)
Department: Science and Humanities
Batch/Year: 2024-2028 / I
Created by:
Dr.V.Tamil Selvi
Dr.N.Padmavathi
Dr U.Nagabalan
Ms.S.Jayanthi
Mr.V.S.Prabhu
Ms.P.Santhoshini
Ms.R.M.Senthil Priya
Date: 21st September, 2024

Table of Contents
Sl. No. Contents Page No.
1 Contents 5
2 Course Objectives 6
3 Pre Requisites (Course Name with Code) 7
4 Syllabus (With Subject Code, Name, LTPC details) 8
5 Course Outcomes 10
6 CO-PO/PSO Mapping 11
Lecture Plan (S.No., Topic, No. of Periods, Proposed
7 date, Actual Lecture Date, pertaining CO, Taxonomy 12
level, Mode of Delivery)
8 Activity based learning 13
Lecture Notes ( with Links to Videos, e-book reference
9 27
and PPTs)
10 Assignments 111
11 Part A Q & A (with K level and CO) 113
12 Part B Qs (with K level and CO) 122

Supportive online Certification courses (NPTEL,
13 125
Swayam, Coursera, Udemy, etc.,)
Real time Applications in day to day life and to
14 127
Industry
Contents beyond the Syllabus ( COE related Value
15 140
added courses)
16 Assessment Schedule ( Proposed Date & Actual Date) 160
17 Prescribed Text Books & Reference Books 161
18 Mini Project 162

2.COURSE OBJECTIVES
The Course will enable learners to:

To acquire the knowledge in Digital fundamentals and its
simplification methods.
To familiarize the design of various combinational digital circuits using

logic gates.
To realize various sequential circuits using flip flops.
To interpret various clocked sequential circuits.
To elucidate various semiconductor memories and related technology.
To build various logic functions using Programming Logic Devices.
3.PRE REQUISITES
SUBJECT NAME : HSC Physics
4.Syllabus
24EC102 DIGITAL PRINCIPLES AND SYSTEM DESIGN L T P C
(LAB INTEGRATED) 3 0 2 4
UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 9
Review of number systems-representation-conversions, Review of Boolean algebra- theorems,

sum of product and product of sum simplification, canonical forms, min term and max term,
Simplification of Boolean expressions-Karnaugh map, Implementation of Boolean expressions
using logic gates and universal gates.
List of Exercise/Experiments:
1. Implementation of Boolean expression using logic gates.
UNIT II COMBINATIONAL LOGIC CIRCUITS 9
Design of combinational circuits - Half and Full Adders, Half and Full Subtractors, Binary
Parallel Adder – Carry look ahead Adder, Magnitude Comparator, Decoder, Encoder, Priority
Encoder, Mux/De-mux, Parity Generator/Checker
2. Design of adders
3. Design of subtractors.
4. Design of binary adder using IC7483
5. Design of Multiplexers & Demultiplexers.
6. Design of Encoders and Decoders.
7. Implementation of a boolean function using a multiplexer
UNIT III SEQUENTIAL CIRCUITS 9
Flip flops – SR, JK, T, D, Master/Slave FF – operation and excitation tables, Asynchronous
and Synchronous Counters Design - Shift registers, Universal Shift Register
8. Design and implementation of 3 bit ripple counters.
9. Design and implementation of 3 bit synchronous counter
10. Design and implementation of shift registers
4.Syllabus
24EC102 DIGITAL PRINCIPLES AND SYSTEM DESIGN L T P C
3 0 2 4
(LAB INTEGRATED)
UNIT IV SYNCHRONOUS SEQUENTIAL CIRCUITS DESIGN 9
Design of clocked sequential circuits - Moore/Mealy models, state minimization, state

assignment, circuit implementation
UNIT V MEMORY AND PROGRAMMABLE LOGIC DEVICES 9
Basic memory structure ROM: PROM – EPROM – EEPROM –RAM – Static and dynamic
RAM – Programmable Logic Devices: Programmable Logic Array (PLA) – Programmable
Array Logic (PAL) – Implementation of combinational logic circuits using PLA, PAL.
TOTAL: 45 PERIODS (THEORY) + 30 PERIODS (LAB) = 75 PERIODS

5. Course
Outcomes
Course Description Knowledge
Outcomes Level
Apply Boolean algebra to simplify and implement digital
CO1 K3
circuits.
Design combinational circuits to meet specific functional
CO2 K3
requirements using logic gates
Demonstrate the operation of counters and shift registers
CO3 K3
using flip-flops in sequential circuits.
CO4 Analyze synchronous sequential circuits to determine their K3

behavior and performance characteristics
Evaluate various types of memory devices, discussing their
CO5 K2
roles and functionalities in digital systems.
Construct combinational circuits using Programmable Logic
CO6 Devices (PLDs) to solve complex digital design problems. K3
Knowledge Level Description
K6 Create
K5 Evaluate
K4 Analyze
K3 Apply
K2 Understand
K1 Remember
6. CO – PO /PSO Mapping
Matrix
CO PO PO PO PO PO PO PO PO PO PO PO PO PS PS PS
1 2 3 4 5 6 7 8 9 10 11 12 O1 O2 03
1 3 2 1 1 - - - - - - - - 3 - -
2 3 3 2 2 - - - - - - - - 3 - -
3 3 3 2 2 - - - - - - - - 3 - -
4 3 3 2 2 - - - - - - - - 3 - -
5 3 3 2 2 - - - - - - - - 3 - -
6 3 2 1 1 - - - - - - - - 3
7. Lecture Plan – Unit 2 – COMBINATIONAL
LOGIC CIRCUITS
Number Taxo
Sl. Proposed Mode of
Topic of CO nomy
No. Date Delivery
Periods Level
Design of combinational 25.09.2024
Experiment
1 circuits – Half Adder 2 & CO2 K2
al Learning
and Full Adders 26.09.2024
Half and Full Experiment
2 1 27.09.2024 CO2 K2
Subtractors al Learning
Chalk &
3 Binary parallel Adder 1 28.09.2024 CO2 K2
Board/ PPT
Carry look ahead Adder, 30.09.2024 Chalk &
4 1 CO2 K2
Magnitude comparator Board/ PPT
Decoder, Encoder, 01.10.2024
Chalk &
5 Priority Encoder 2 & CO2 K2
Board/ PPT
03.10.2024
PPT &
Mux/De-Mux
6 1 04.10.2024 CO2 K2 Learning by
doing
Chalk &
Parity CO2
7 1 05.10.2024 K2 Board/ PPT
Generator/Checker
Design of Half Adder, 07.10.2024

Full Adder, Half & Learning by
8 2 CO2 K2
Subtractor, Full 08.10.2024 doing
Subtractor
Design of Binary Parallel 09.10.2024
Learning by
9 Adder, Encoder and 2 & CO2 K2
doing
Decoder 10.10.2024
MUX, DEMUX and 15.10.2024
implementation of & Learning by
10 2 CO2 K2
Boolean function with 16.10.2024 doing
MUX
8. ACTIVITY BASED LEARNING
1. Circuit simulator for magnitude comparator &full adder
13
ACTIVITY BASED LEARNING
• Simulate a 4 bit parallel adder circuit using multisim.
• Online Logic Circuit Simulator

https://logic.ly/
14
ACTIVITY-PUZZLE WORKSHEET
• The simple switch-and-diode circuit shown here is an example of a
digital encoder. Explain what this circuit does, as the switch is moved
from position to position:
This encoder generates a three-bit binary code corresponding to the switch position
(one out of eight positions).
Follow-up question: trace the path of electron flow through the circuit with the switch
in position #3.
Challenge question: are there other codes (besides binary) that could possibly be
generated with a circuit of this general design?
15
• Identify which diode is failed in this circuit, given the
following truth table (showing the actual operation of the
encoder circuit, not what it should do):
Switch Output
position code
0 000
1 001
2 010
3 011
4 100
5 001
6 110
7 111
16
QUIZ
1. If A and B are the inputs of a half adder, the sum is given by __________
a)A AND B
b)A OR B
c)A XOR B
d) A EX-NOR B
Answer: c
2. A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: a
3. If A, B and C are the inputs of a full adder then the sum is given by
__________
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C
Answer: c
4. If A, B and C are the inputs of a full adder then the carry is given by
__________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
Answer: a
5. How many AND, OR and EXOR gates are required for the configuration of full
adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
Answer: b
17
6. The full subtractor can be implemented using ___________
a) Two XOR and an OR gates
b) Two half subtractors and an OR gate
c) Two multiplexers and an AND gate
d) Two comparators and an AND gate
Answer: b
7. Let A and B is the input of a subtractor then the output will be ___________
a) A XOR B
b) A AND B
c) A OR B
d) A EXNOR B
Answer: a
8. Which combinational circuit is renowned for selecting a single input from

multiple inputs & directing the binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
Answer: a
9. What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) It is a type of encoder which decodes several inputs and gives one output
Answer: b
10. If the number of n selected input lines is equal to 2^m then it requires
_____ select lines.
a) 2
b) m
c) n
d) 2n
Answer: b
18
11. How many select lines would be required for an 8-line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3
Answer: d
12. The discrepancy of 0 output due to all inputs being 0 or D0, being 0 is
resolved by using additional input known as ___________
a) Enable
b) Disable
c) Strobe
d) Clock
Answer: a
13. Can an encoder be called as multiplexer?

a) No
b) Yes
c) Sometimes
d) Never
Answer: b
14. One that is not the outcome of magnitude comparator is ____________

a) a > b
b) a – b
c) a < b
d) a = b
Answer: b
15. A circuit that compares two numbers and determine their magnitude is called
____________
a) Height comparator
b) Size comparator
c) Comparator
d) Magnitude comparator
Answer: d
19
16. What type of logic circuit is represented by the figure shown below?
a) XOR
b) XNOR
c) AND
d) XAND
Answer: b
17. Which of the following logic expressions represents the logic diagram shown?
a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB
Answer: d
18. The Boolean expression Y = (AB)’ is logically equivalent to what single gate?
a) NAND
b) NOR
c) AND
d) OR
Answer: a
19. The observation that a bubbled input OR gate is interchangeable with a

bubbled output AND gate is referred to as:
a) A Karnaugh map
b) DeMorgan’s second theorem
c) The commutative law of addition
d) The associative law of multiplication
Answer: b
20. The carry look ahead adder is based on the principle of looking at the lower
order bits of ________ and ________ if a high order carry is generated.
a) Addend, minuend
b) Minuend, subtrahend
c) Addend, minuend
d) Augend, addend
Answer: d
20
21. The inverter can be produced with how many NAND gates?
a) 2
b) 1
c) 3
d) 4
Answer: b
22. The word demultiplex means ___________

a) One into many
b) Many into one
c) Distributor
d) One into many as well as Distributor
Answer: d
23. In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be

___________
a) Y0
b) Y1
c) Y2
d) Y3
Answer: b
24. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
Answer: b
25. The binary subtraction of 0 – 0 = ?

a) Difference = 0, borrow = 0
b) Difference = 1, borrow = 0
c) Difference = 1, borrow = 1
d) Difference = 0, borrow = 1
Answer: a
21
Activity-Multiple Choice Quiz
1. What does Parity mean?

a) Parity checking is a used to check whether data has been changed or corrupted
following transmission from one device to another device.
b) Parity is whether or not data is odd or even.
c) Parity checking is used to check whether binary has been changed or corrupted
following transmission from 2 devices to another device.
d) Parity is when a smartphone uses data to check if its transmitted to one device
to another.
2. In an even parity scheme, what would be the correct parity bit for the
binary string: 1101 0001
a) 1 1101 0001
b) 0 1101 0001
c) 1 101 0001
d) 1101 0001 1
3) In an odd parity scheme, what would be the correct parity bit for the
a) 1 1101 0001
b) 0 1101 0001
c) 0101 0001
d) 1101 0001 0
a) 0 1111 0111
b) 1 1111 0111
c) 0 1011 0111
d) 1111 0111 1
22
5) In an even parity scheme, what would be the correct parity bit for the
a) 1 1000 0111
b) 0 1000 0111
c) 0 1100 0111
d) 1000 0111 0
a) 0 1000 0111
b) 1 1000 0110
c) 1000 0111 1
d) 0 1100 0111
a) 1 1000 0000
b) 0 1000 0000
c) 1 1100 0000
d) 1000 0000 1
a) 1 1010 1010
b) 0 1010 1010
c) 1 1110 1010
d) 1010 1010 1
a) 1 1010 1111
b) 0 1010 1111
c) 1010 1111 1
a) 1 1010 0011
b) 0 1000 0111
c) 1 1100 0111
d) 1010 0111 1
23
8. ACTIVITY BASED LEARNING
PUZZLE
Across
[3] Timing signal is called as ___.
[4] One input many output is called as_____.
[7] A binary no. obtained by complementing every bit of a
no.
[10] AND, OR, and NOT are ____ gates
[12] (A+B)+C= A+(B+C) is expression for ____ law.
[14] Base of decimal number system
[15] A+BC= (A+B) . (A+C) is expression for ____ law.
[16] Circuit whose value depends on present input and
previous output
[18] Parity counter is application of ____ logic gate
12
ACTIVITY BASED LEARNING
DOWN
[1] A combinational circuit performs addition of two
numbers
[2] Theorem used to change AND logic to OR and vice
versa
[5] Memory information is easily read and altered in ____
memory.
[6] Memory is not required in _____ circuits.
[8] 7432 is IC no of ___ logic gate
[9] FlipFlops are ___ triggered circuit
[11] Universal Gate
[13] Basic building block of sequential circuit
[16] Format of following Boolean expression is Y=A
?B+AB ?
[17] If any one of input is 1 output is zero. This is ___
Gate
[18] Number of distinct value in octal number systems
25
Puzzle -Solution
9.Lecture Notes
Unit 2
UNIT II COMBINATIONAL LOGIC
CIRCUITS
Sl. No. Contents
1 Design of combinational circuits
2 Half Adder
3 Full Adder
4 Half Subtractor
5 Full Subtractor
6 Binary Parallel Adder
7 Carry Look ahead Adder
8 Magnitude Comparator
9 Decoder
10 Encoder
11 Priority Encoder
12 Multiplexer
13 De-multiplexer
14 Parity Generator/Checker
Introduction to Combinational
Circuits
The digital system consists of two types of circuits, namely
(i) Combinational circuits

(ii) Sequential circuits
Combinational circuit consists of logic gates whose output at any time is

determined from the present combination of inputs.
The logic gate is the most basic building block of combinational logic. The logical
function performed by a combinational circuit is fully defined by a set of Boolean
expressions.
A combinational circuit consists of input variables, logic gates, and output variables.
The logic gates accept signals from inputs and output signals are generated
according to the logic circuits employed in it.
Binary information from the given data transforms to desired output data in this
process. Both input and output are obviously the binary signals, i.e., both the input
and output signals are of two possible states, logic 1 and logic 0.
Combinational
. m outputs
n inputs . circuits
. .
Block diagram of a combinational logic circuit
For n number of input variables, to a 2𝑛 possible combinational circuit,

Combinational logic output can be combinations of binary input states are
possible. For each possible combination, there is one and only one possible output
combination. A circuit can be described by m Boolean functions and each
expressed in terms of n input variables.
Circuits
Sequential logic circuit comprises both logic gates and the state of storage
elements such as flip-flops. As a consequence, the output of a sequential circuit
depends not only on present value of inputs but also on the past state of inputs.
Block diagram of a sequential logic circuit

Sequential logic circuits, it consists of combinational circuits to which storage
elements are connected to form a feedback path. The storage elements are
devices capable of storing binary information either 1 or 0.
The information stored in the memory elements at any given time defines the
present state of the sequential circuit. The present state and the external circuit
determine the output and the next state of sequential circuits.
Classification of Logic
Circuits
Circuits
The sequential circuits can be classified depending on the timing of their signals:
• Synchronous sequential circuits
• Asynchronous sequential circuits.
In synchronous sequential circuits, signals can affect the memory elements only
at discrete instants of time.
In asynchronous sequential circuits change in input signals can affect memory

element at any instant of time.
The memory elements used in both circuits are Flip-Flops, which are capable of
storing 1- bit information.
Difference Between Combinational and Sequential Circuits
S.No Combinational logic Sequential logic

The output variable, at all times The output variable depends not only
1
depends on the combination of on the present input but also depend
input variables. upon the past history of inputs.
2 Memory unit is required to store the
Memory unit is not required
past history of input variables.
3 Faster in speed Slower than combinational circuits.
4
Easy to design Comparatively harder to design.
5 Eg. Parallel adder Eg. Serial adder
1. Design of Combinational
Circuits
Design of Combinational Circuits (Procedure)
Any combinational circuit can be designed by the following steps of

design procedure.
• The problem is stated.
• Identify the input and output variables.
• The input and output variables are assigned letter symbols.
• Construction of a truth table to meet input -output requirements.
• Writing Boolean expressions for various output variables in terms

of input variables.
• The simplified Boolean expression is obtained by any method of

minimization— algebraic method, Karnaugh map method, or
tabulation method.
• A logic diagram is realized from the simplified Boolean expression

using logic gates.
• There should be a minimum number of interconnections.
• Limitation on the driving capability of the gates should not be

ignored.
• The implementation should have the minimum number of gates,

with the gates used having the minimum number of inputs.
2. HALF ADDER
Half Adder
Half Adder is a combinational circuit that can be used to add two binary bits. It
has two inputs that represent the two bits to be added and two outputs, with one
producing the SUM output and the other producing the CARRY.
Block Diagram of Half Adder
The truth table of a half-adder, showing all possible input combinations and the
corresponding outputs are shown below.
Inputs Outputs
A B Carry (C) Sum (S)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
K-map simplification for carry and sum

The Boolean expressions for the SUM and CARRY outputs are
given by the equations,
Sum, S= A’B+ AB’= AÅB
Carry, C = A . B
The first one representing the SUM output is that of an EX-OR gate, the second
one representing the CARRY output is that of an AND gate.
The logic diagram of the half adder is,

3. FULL ADDER
Full Adder
A full adder is a combinational circuit that forms the arithmetic sum of three input
bits. It consists of 3 inputs and 2 outputs.
Two of the input variables, represent the significant bits to be added. The third
input represents the carry from previous lower significant position. The block
diagram of full adder is given by,
Full Adder:
The full adder circuit overcomes the limitation of the half-adder, which can be
used to add two bits only. As there are three input variables, eight different input
combinations are possible. The truth table is shown below,
Inputs Outputs
A B Cin Sum Carry
(S) (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
The Boolean expressions for the SUM and CARRY outputs are given by the
equations,
Sum, S = A’B’Cin+ A’BC’in + AB’C’in + ABCin

Carry, Cout = AB+ ACin + BCin
The logic diagram for the above functions is shown as,
Implementation of Full Adder Using Two Half Adders

The logic diagram of the full adder can also be implemented with two half- adders
and one OR gate. The S output from the second half adder is the exclusive-OR of
Cin and the output of the first half-adder, giving
Sum = Cin ⊕ (A ⊕ B) [x ⊕ y = x‘y+ xy‘]

= Cin ⊕ (A‘B+AB‘)
= C‘in (A‘B+AB‘) + Cin (A‘B+AB‘)‘ [(x‘y+xy‘)‘= (xy+x‘y‘)]
= C‘in (A‘B+AB‘) + Cin (AB+A‘B‘)
= A‘BC‘in + AB‘C‘in + ABCin + A‘B‘Cin
and the carry output is,
Carry, Cout = AB+ Cin (A’B+AB’)
= AB+ A‘BCin+ AB‘Cin
= AB (Cin+1) + A‘BCin+ AB‘Cin [Cin+1= 1]
= ABCin+ AB+ A‘BCin+ AB‘Cin
= AB+ ACin (B+B‘) + A‘BCin
= AB+ ACin+ A‘BCin
= AB (Cin+1) + ACin+ A‘BCin [Cin+1= 1]
= ABCin+ AB+ ACin+ A‘BCin
= AB+ ACin+ BCin (A +A‘)
= AB+ ACin+ BCin
Implementation of Full Adder Using Two Half Adders
The logic diagram of the full adder can also be implemented with two half-
adders and one OR gate is as follows,
4. HALF SUBTRACTOR
Binary Subtractor
Half Subtractor
• Half Subtractor is a combinational circuit that performs the subtraction of

two bits.
• It has two inputs and two outputs as shown in the block diagram.
• Two inputs A and B form the minuend and the subtrahend.
• Two outputs B and B form the Difference and borrow output.
Block Diagram
• The truth table for the half subtractor is listed in the table. The Borrow output is
1 when A is 0 and B is 1. The difference output is 1 when both the inputs are
different.
Truth Table
• The simplified Boolean function for the two outputs can be obtained directly
from the truth table.
• The logic diagram of the half subtractor implemented in sum of products is
shown in the figure.
K map for Borrow K map for Difference
Borrow = X’Y Difference= X’Y+XY’
= X Y
Logic Diagram
Limitations:
Multidigit subtraction along with borrow of the previous digit
subtraction is not possible with half subtractor.
5. FULL SUBTRACTOR
Full Subtractor
•A full subtractor is a combinational circuit that performs a subtraction between two

bits, taking into account borrow of the lower significant stage.
•The circuit has three inputs X,Y and Z, and two outputs Difference and
Borrow as shown in the block diagram.
•Three Inputs (X,Y, Z is borrow)
•Two outputs (D-Difference, B-Borrow)
Block Diagram
• The truth table for the full subtractor is listed in the table.
• The simplified Boolean function for the two outputs can be obtained directly
from the truth table.
• The logic diagram of the full subtractor implemented in sum of products is
shown in the figure.
Truth Table K Map for Difference
K map for Borrow
Logic Diagram
Implementation of Full Subtractor using two Half-Subtractors
• A full subtractor is formed by two half subtractors,
• It involves three inputs such as minuend, subtrahend and borrow.
• Borrow bit among the inputs is obtained from subtraction of two binary digits
and is subtracted from next higher order pair of bits, outputs as difference and
borrow.
Difference =X’Y’Z+ X’YZ’+ XY’Z’ + XYZ

=X Y Z
Borrow = X’Y+ X’Z+ YZ = X’Y + Z(X’+Y)
= X’Y+ X’YZ + X’Y’Z + XYZ + X’YZ
= X’Y+ X’YZ + X’YZ + X’Y’Z + XYZ
= X’Y (1+ Z + Z) + (X’Y’ + XY) Z
= X’Y + (X’ Y)’ Z
Logic Diagram:
Logic
Diagram
6. Binary Parallel Adder
Binary Adder (Parallel Adder)
The 4-bit binary adder using full adder circuits is capable of adding two 4-bit
numbers resulting in a 4-bit sum and a carry output as shown in figure below.
• Since all the bits of augend and addend are fed into the adder circuits
simultaneously and the additions in each position are taking place at the same
time, this circuit is known as parallel adder.
• Let the 4-bit words to be added be represented by, A3A2A1A0= 1111 and
B3B2B1B0= 0011.
44
• The bits are added with full adders, starting from the least significant position, to
form the sum it and carry bit. The input carry C0 in the least significant position
must be
• The carry output of the lower order stage is connected to the carry input of the
next higher order stage. Hence this type of adder is called ripple-carry adder.
• In the least significant stage, A0, B0 and C0 (which is 0) are added resulting in
sum S0 and carry C1. This carry C1 becomes the carry input to the second stage.
• Similarly in the second stage, A1, B1 and C1 are added resulting in sum S1 and
carry C2, in the third stage, A2, B2 and C2 are added resulting in sum S2 and
carry C3, in the third stage, A3, B3 and C3 are added resulting in sum S3 and C4,
which is the output carry. Thus the circuit results in a sum (S3S2S1S0) and a
carry output (Cout).
45
7. Carry Look ahead Adder
In Parallel adder, all the bits of the augend and the addend are available for
computation at the same time.
The carry output of each full-adder stage is connected to the carry input of the
next high-order stage. Since each bit of the sum output depends on the value
of the input carry, time delay occurs in the addition process. This time delay is
called as carry propagation delay.
For example, addition of two numbers (0011+ 0101) gives the result as 1000.
Addition of the LSB position produces a carry into the second position. This
carry when added to the bits of the second position, produces a carry into the
third position.
This carry when added to bits of the third position, produces a carry into the
last position. The sum bit generated in the last position (MSB) depends on the
carry that was generated by the addition in the previous position. i.e., the
adder will not produce correct result until LSB carry has propagated through
the intermediate full-adders.
This represents a time delay that depends on the propagation delay produced
in an each full-adder. For example, if each full adder is considered to have a
propagation delay of 30nsec, then S3 will not react its correct value until 90nsec
after LSB is generated. Therefore total time required to perform addition is
90+ 30 = 120nsec.
The method of speeding up this process by eliminating inter stage carry delay
is called look ahead-carry addition. This method utilizes logic gates to look
at the lower order bits of the augend and addend to see if a higher-order
carry is to be generated. It uses two functions: carry generate and carry
propagate.
Carry Look ahead Adder
Consider the circuit of the full-adder shown above. Here we define two functions:
carry generate (Gi) and carry propagate (Pi) as,
Carry generate, Gi = Ai Bi
Carry propagate, Pi = Ai ⊕ Bi
the output sum and carry can be expressed as,
Si = Pi ⊕ Ci
Ci+1 = Gi + Pi Ci
Gi (carry generate), it produces a carry 1 when both Ai and Bi are 1, regardless of

the input carry Ci.
Pi (carry propagate) because it is the term associated with the propagation of the
carry from Ci to Ci+1.
The Boolean functions for the carry outputs of each stage and substitute for each
Ci
its value from the previous equation:
C0= input carry

C1= G0 + P0C0
C2= G1 + P1C1 = G1 + P1 (G0 + P0C0)
= G1 + P1G0 + P1P0C0
C3= G2 + P2C2 = G2 + P2 (G1 + P1G0 + P1P0C0)
= G2 + P2G1 + P2P1G0 + P2P1P0C0

Since the Boolean function for each output carry is expressed in sum of products,
each function can be implemented with one level of AND gates followed by an OR
gate. The three Boolean functions for C1, C2 and C3 are implemented in the carry
look-ahead generator as shown below. Note that C3 does not have to wait for C2 and
C1 to propagate; in fact C3 is propagated at the same time as C1 and C2.
Using a Look-ahead Generator we can easily construct a 4-bit parallel adder with a
Look-ahead carry scheme. Each sum output requires two exclusive-OR gates.
The output of the first exclusive-OR gate generates the Pi variable, and the AND gate
generates the Gi variable. The carries are propagated through the carry look- ahead
generator and applied as inputs to the second exclusive-OR gate.
All output carries are generated after a delay through two levels of gates. Thus,
outputs S1 through S3 have equal propagation delay times.
• The advantages of carry look ahead adder are-
• It generates the carry-in for each full adder simultaneously.

• It reduces the propagation delay.
• The disadvantages of carry look ahead adder are-
• It involves complex hardware.

• It is costlier since it involves complex hardware.
• It gets more complicated as the number of bits increases.
8. MAGNITUDE COMPARATOR
A magnitude comparator is a combinational circuit that compares two numbers A
and B and determines their relative magnitudes.
The comparison of two numbers is an operation that determines whether one

number is greater than, less than, or equal to the other number.
The outcome of the comparison is specified by three binary variables that indicate
whether A < B, A = B, or A > B.
1-BIT MAGNITUDE COMPARATOR

A comparator used to compare two bits is called a single-bit comparator. It
consists of two inputs each for two single-bit numbers and three outputs to
generate less than, equal to, and greater than between two binary numbers.
The truth table for a 1-bit comparator is given below:
From the above truth table logical expressions for each output can be expressed as
follows:
A>B : AB’
A<B : A’B
A=B : A’B’ + AB
2-BIT MAGNITUDE COMPARATOR
The circuit for comparing two n -bit numbers has 2 X 2n entries in the truth table.
So, for comparing two 2-bit numbers, the truth table has 2 2x2=16 entries
Consider two numbers, A and B , with two digits each
A = A1 A0
B = B1 B0
Truth table for comparison of two 2-bit numbers
The outputs A=B, A>B and A<B are expressed as follows:

F(A<B) = ∑m (1,2,3,6,7,11)
F(A>B) = ∑m (4,8,9,12,13,14)
F(A=B) = ∑m (0,5,10,15)
K-map for F(A<B)
The comparison A<B can be logically expressed by the following Boolean function
F(A<B) = A1’B1 + A1’A0’B0 + A0’B1B0
K-map
for F(A>B)
The comparison A>B can be logically expressed by the following Boolean function
F(A>B) = A1B1’ + A1A0B0’ + A0B1’B0’
K-map for F(A=B)
F(A=B) = A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’
= A1’B1’ (A0’B0’ +A0B0) + A1B1(A0B0 + A0’B0’)
= A1’B1’( A0 ⊙ B0) + A1B1 (A0 ⊙ B0)
= ( A0 ⊙ B0) (A1’B1’ + A1B1)
=( A0 ⊙ B0)(A1⊙ B1)
The comparison A=B can be logically expressed by the following Boolean function
F(A=B) =( A0 ⊙ B0)(A1⊙ B1)
Logic diagram for 2-bit Magnitude Comparator
4- BIT MAGNITUDE COMPARATOR
The circuit for comparing two n -bit numbers has 22n entries in the truth
table and becomes complicated, even with n = 3.
The algorithm here, is a direct application of the procedure we use to

compare the relative magnitudes of two numbers.
Consider two numbers, A and B , with four digits each

A = A 3 A2 A1 A0
B = B3 B2 B1 B0
To find if A=B
The two 4-bit numbers A and B are said to be
equal if A3=B3 & A2=B2 & A1=B1 & A0=B0
This can be written as

E3 = A3 ⊙ B3 (The ⊙ XNOR operation returns 1 if two bits are
equal)
E2 = A2 ⊙ B2
E1 = A1 ⊙ B2
E0 = A0 ⊙ B0
The comparison A=B can be logically expressed by the following Boolean

function
F(A = B) = E3.E2.E1.E0
The binary variable A = B is equal to 1 only if all pairs of digits of the
two numbers are equal.
Logic Diagram for 4-bit Magnitude Comparator
E
3
E
2
E1
E0
9. DECODER
• A decoder is similar to Demultiplexer but without any data input. Most digital
systems requires decoding of data. Decoding is necessary in applications such as
data demultiplexing, digital display, digital to analog converters and memory
addressing. A decoder is a combinational circuit that converts binary information
of n input lines to a maximum of 2n unique output lines. Such that one of each
output line will be activated for only one of the possible combinations of inputs. The
general structure of decoder circuit is given below:
Binary Decoder (2 to 4 decoder)

• A binary decoder has ‗n‘ bit binary input and a one activated output out of 2n
outputs. A binary decoder is used when it is necessary to activate exactly one of
2n outputs based on an n-bit input value.
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2-to-4 Line decoder
• Here the 2 inputs are decoded into 4 outputs, each output representing one of the
minterms of the two input variables
• As shown in the truth table, if enable input is 1 (EN= 1) only one of the outputs (Y0 –
Y3), is active for a given input.
• The output Y0 is active, i.e.., Y0= 1 when inputs A= B= 0,
• Y1 is active when inputs, A= 0 and B= 1,
• Y2 is active, when input A= 1 and B= 0,
• Y3 is active, when inputs A= B= 1.
3- to-8 Line Decoder
• 3-to-8 line decoder has three inputs (A, B, C) and eight outputs (Y0- Y7). Based on
the 3 inputs one of the eight outputs is selected.
• The three inputs are decoded into eight outputs, each output representing one of the
minterms of the 3-input variables. This decoder is used for binary-to-octal conversion.
The input variables may represent a binary number and the outputs will represent the
eight digits in the octal number system. The output variables are mutually exclusive
because only one output can be equal to 1 at any one time. The output line whose
value is equal to 1 represents the minterm equivalent of the binary number presently
available in the input lines.
59
3-to-8 line decoder
Now, let us implement the following two higher-order decoders using lower-order
decoders.
Required No of Decoder =m1/m2
m1 is the number of outputs of lower order decoder.
m2 is the number of outputs of higher order decoder.
Here, m1 = 4 and m2 = 8.
Required number of 2 to 4 decoders=8/4
Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder.
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Implementation of one 3 to 8 decoder using
two 2 to 4 decoder
4 to 16 Decoder using 3 to 8 decoders:

To implement 4 to 16 decoder using 3 to 8 decoders. We know that 3 to 8 Decoder has
three inputs A2, A1 & A0 and eight outputs, Y7 to Y0. Whereas, 4 to 16 Decoder has
four inputs A3, A2, A1 & A0 and sixteen outputs, Y15 to Y0 .The formula for finding the
number of lower order decoders required.
Required number of lower order decoders= m2/m1
=16/8
=2
Here fore, we require two 3 to 8 decoders for implementing one 4 to 16 decoder.
The block diagram of 4 to 16 decoder using 3 to 8 decoders
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Truth table for 4 - to -16
decoder
Inputs Outputs
A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 0 1 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0
0 1 0 0 0 0 0 0 1 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0
0 0 1 1 0 0 0 0 0 0 1 0
0 1 1 1 0 0 0 0 0 0 0 1
Inputs Outputs
A3 A2 A1 A0 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15
1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1
4- to 16 Decoder using 2 to 4
decoders.:
4- to 16 Decoder using 2 to 4 decoders.:
Required number of lower order decoders= m2/m1=16/4=4
Therefore, we require two 2 to 4 decoders for implementing one 4 to 16 decoder.
Combinational Logic Implementation using
Decoder
Since any boolean function can be expressed as a sum of minterms, a decoder that
can generate these minterms along with external OR gates that form their
logical
sums, can be used to form a circuit of any boolean function.
Implement full adder with a decoder

To implement the logic of a full adder, we need a 3:8 decoder and OR gates. The
input to the full adder, first and second bits and carry bit, are used as input to the
decoder. Let x, y and z represent these three bits. Sum and Carry outputs of a full
X
adder have the followingYtruth tables-E
Z S C
0 0 0 0 0
0 0 1 1 0
S=∑m (1, 2, 4, 7)
0 1 0 1 0 C=∑m (3,5,6,7)
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Implement, with a decoder and external OR gates, the combinational
circuit specified by the following three Boolean functions:
f1(A, B, C) = Σm(0,5,7)
f2(A, B, C) = Σm(2,3,4)
f3(A, B, C) =Σm(1,6,7)
A combinational circuit is specified by the following three Boolean

functions:
F1 (A, B, C) = Σ(2, 4,7)

F2 (A, B, C) = Σ(0, 3)
F3 (A, B, C) = Σ(0, 2, 3, 4, 7) Implement the circuit with a decoder constructed with
NAND gates connected to the decoder outputs.
BCD to 7-Segment Display Decoder
• A seven-segment display is normally used for displaying any one of the decimal
digits, 0 through 9. A BCD-to-seven segment decoder accepts a decimal digit in
BCD and generates the corresponding seven-segment code
Each segment is made up of a material that emits light when current is passed
through it. The segments activated during each digit display are tabulated as—
66
Truth table
67
68
BCD to 7-segment display decoder
Applications of decoders
• Decoders are used in counter system.
• They are used in analog to digital converter.
• Decoder outputs can be used to drive a display system.
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10. ENCODERS
• An encoder is a digital circuit that performs the inverse operation of a decoder.
Hence, the opposite of the decoding process is called encoding. An encoder is a
combinational circuit that converts binary information from 2n input lines to a
maximum of ‗n‘ unique output lines.
• The general structure of encoder circuit is –
• It has 2n input lines, only one which 1 is active at any time and ‗n‘ output lines.
It encodes one of the active inputs to a coded binary output with ‗n‘ bits. In an
encoder, the number of outputs is less than the number of inputs.
Octal-to-Binary Encoder
• It has eight inputs (one for each of the octal digits) and the three outputs that
generate the corresponding binary number. It is assumed that only one input has
a value of 1 at any given time.
70
• The encoder can be implemented with OR gates whose inputs are determined
directly from the truth table. Output z is equal to 1, when the input octal digit is 1 or
3 or 5 or 7. Output y is 1 for octal digits 2, 3, 6, or 7 and the output is 1 for digits 4,
5, 6 or
• These conditions can be expressed by the following output Boolean functions:
• z= D1+ D3+ D5+ D7
• y= D2+ D3+ D6+ D7
• x= D4+ D5+ D6+ D7
• The encoder can be implemented with three OR gates. The encoder defined in the
below table, has the limitation that only one input can be active at any given time. If
two inputs are active simultaneously, the output produces an undefined
combination.
• For e.g., if D3 and D6 are 1 simultaneously, the output of the encoder may be 111.
This does not represent either D6 or D3. To resolve this problem, encoder circuits
must establish an input priority to ensure that only one input is encoded. If we
establish a higher priority for inputs with higher subscript numbers and if D3 and D6
are 1 at the same time, the output will be 110 because D6 has higher priority than
D3.
Octal-to-Binary Encoder
• Another problem in the octal-to-binary encoder is that an output with all 0‘s is
generated when all the inputs are 0; this output is same as when D0 is equal to 1.
The discrepancy can be resolved by providing one more output to indicate that at
least one input is equal to 1.
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11. PRIORITY ENCODER
A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if two or more inputs are equal to 1 at the same time, the input having the
highest priority will take precedence.
• In addition to the two outputs x and y, the circuit has a third output, V (valid bit
indicator). It is set to 1 when one or more inputs are equal to 1. If all inputs are
0, there is no valid input and V is equal to 0.
• The higher the subscript number, higher the priority of the input. Input D3, has
the highest priority. So, regardless of the values of the other inputs, when D3 is
1, the output for xy is 11.
• D2 has the next priority level. The output is 10, if D2= 1 provided D3= 0. The
output for D1 is generated only if higher priority inputs are 0, and so on down the
priority levels.
Truth table
• Although the above table has only five rows, when each don‘t care condition is
replaced first by 0 and then by 1, we obtain all 16 possible input combinations.
For example, the third row in the table with X100 represents minterms 0100 and
1100.
• The don‘t care condition is replaced by 0 and 1 as shown in the table below.
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K-map Simplification:
• The priority encoder is implemented according to the above Boolean

functions. The logic diagram is as follows
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12. MULTIPLEXER
• A multiplexer or MUX, is a combinational circuit with more than one input line,
one output line and more than one selection line. A multiplexer selects binary
information present from one of many input lines, depending upon the logic status
of the selection inputs, and routes it to the output line. Normally, there are 2n input
lines and n selection lines whose bit combinations determine which input is
selected. The multiplexer is often labelled as MUX in block diagrams.
• A multiplexer is also called a data selector, since it selects one of many inputs
and steers the binary information to the output line.
Block diagram of Multiplexer

2-to-1- line Multiplexer
• The circuit has two data input lines, one output line and one selection line, S.
• When S= 0, the upper AND gate is enabled and I0 has a path to the output.
• When S=1, the lower AND gate is enabled and I1 has a path to the output.
Logic diagram
The multiplexer acts like an electronic switch that selects one of the two sources.
4-to-1-line Multiplexer
• 4-to-1-line multiplexer has four (2n) input lines, two (n) select lines and one
output line. It is the multiplexer consisting of four input channels and information
of one of the channels can be selected and transmitted to an output line
according to the select inputs combinations. Selection of one of the four input
channel is possible by two selection inputs.
• Each of the four inputs I0 through I3, is applied to one input of AND gate.
Selection lines S1 and S0 are decoded to select a particular AND gate. The
outputs of the AND gate are applied to a single OR gate that provides the 1-line
output.
Function table:
• To demonstrate the circuit operation, consider the case when S1S0= 10. The AND
gate associated with input I2 has two of its inputs equal to 1 and the third input
connected to I2.
• The other three AND gates have at least one input equal to 0, which makes their
outputs equal to 0. The OR output is now equal to the value of I2, providing a
path from the selected input to the output.
• The data output is equal to I0 only if S1= 0 and S0= 0; Y= I0S1‘S0‘.

• The data output is equal to I1 only if S1= 0 and S0= 1; Y= I1S1‘S0.
• The data output is equal to I2 only if S1= 1 and S0= 0; Y= I2S1S0‘.
• The data output is equal to I3 only if S1= 1 and S0= 1; Y= I3S1S0.
When these terms are ORed, the total expression for the data output is,
Y= I0S1’S0’+ I1S1’S0 +I2S1S0’+ I3S1S0.
As in decoder, multiplexers may have an enable input to control the operation of the
Unit. When the enable input is in the inactive state, the outputs are disabled, and
when it is in the active state, the circuit functions as a normal multiplexer.
As in decoder, multiplexers may have an enable input to control the operation of the
Unit. When the enable input is in the inactive state, the outputs are disabled, and
when it is in the active state, the circuit functions as a normal multiplexer.
Application:
• The multiplexer is a very useful MSI function and has various ranges of
applications in data communication. Signal routing and data communication are
the important applications of a multiplexer. It is used for connecting two or more
sources to guide to a single destination among computer Units and it is useful for
constructing a common bus system. One of the general properties of a
multiplexer is that Boolean functions can be implemented by this device.
Quadruple 2-to-1 Line Multiplexer:

• This circuit has four multiplexers, each capable of selecting one of two input lines.
Output Y0 can be selected to come from either A0 or B0. Similarly, output Y1 may
have the value of A1 or B1, and so on. Input selection line, S selects one of the
lines in each of the four multiplexers. The enable input E must be active for
normal operation.
• Although the circuit contains four 2-to-1-Line multiplexers, it is viewed as a circuit
that selects one of two 4-bit sets of data lines. The Unit is enabled when E= 0.
Then if S= 0, the four A inputs have a path to the four outputs. On the other
hand, if S=1, the four B inputs are applied to the outputs. The outputs have all
0‘s when E= 1, regardless of the value of S.
Quadruple 2-to-1 Line Multiplexer:
Implementation of Boolean Function using MUX
• Any Boolean or logical expression can be easily implemented using a multiplexer.

If a Boolean expression has (n+1) variables, then n‘ of these variables can be
connected to the select lines of the multiplexer. The remaining single variable
along with constants 1 and 0 is used as the input of the multiplexer. For example,
if C is the single variable, then the inputs of the multiplexers are C, C‘, 1 and 0.
By this method any logical expression can be implemented.
• In general, a Boolean expression of (n+1) variables can be implemented using a
multiplexer with 2n inputs.
1.Implement the following Boolean function using 4: 1 multiplexer,
F (A, B, C) = ∑m (1, 3, 5, 6).
Solution:
Variables, n= 3 (A, B, C)
Select lines= n-1 = 2 (S1, S0)
2-1 to MUX i.e., 22 to 1 = 4 to 1 MUX
Input lines= 2n-1 = 22 = 4 (D0, D1, D2, D3)
Implementation table:
• Apply variables A and B to the select lines. The procedures for implementing the
function are:
• List the input of the multiplexer
• List under them all the minterms in two rows as shown below.
• The first half of the minterms is associated with A‘ and the second half with A.
The given function is implemented by circling the minterms of the function and
applying the following rules to find the values for the inputs of the multiplexer.
• If both the minterms in the column are not circled, apply 0 to the corresponding
input.
• If both the minterms in the column are circled, apply 1 to the corresponding
input.
• If the bottom minterm is circled and the top is not circled, apply C to the input.
• If the top minterm is circled and the bottom is not circled, apply C‘ to the input.
Multiplexer Implementation
2. F (x, y, z) = ∑m (1, 2, 6, 7)
Solution:
Implementation table:
3. F ( A, B, C) = ∑m (1, 2, 4, 5)
Solution:
• Variables, n= 3 (A, B, C) Select lines= n-1 = 2 (S1, S0)
• 2n-1 to MUX i.e., 22 to 1 = 4 to 1 MUX Input lines= 2n-1 = 22 = 4 (D0, D1, D2,
D3)
Implementation table
4. F( P, Q, R, S)= ∑m (0, 1, 3, 4, 8, 9, 15)
Solution:
•Variables, n= 4 (P, Q, R, S)
•Select lines= n-1 = 3 (S2, S1, S0)
•2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
•Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
5. Implement the Boolean function using 8: 1 and also using 4:1 multiplexer
F (A, B, C, D) = ∑m (0, 1, 2, 4, 6, 9, 12, 14)
Solution:
• Variables, n= 4 (A, B, C, D)
• 2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Multiplexer Implementation (Using 8: 1 MUX)

Using 4: 1 MUX
6.Implement the Boolean function using 8: 1 multiplexer.

F (A, B, C, D) = A’BD’ + ACD + B’CD + A’C’D.
Solution:
Convert into standard SOP form,
= A‘BD‘ (C‘+C) + ACD (B‘+B) + B‘CD (A‘+A) + A‘C‘D (B‘+B)
=‘BC‘D‘ + A‘BCD‘+ AB‘CD + ABCD +A‘B‘CD + AB‘CD +A‘B‘C‘D+ A‘BC‘D
=A‘BC‘D‘ + A‘BCD‘+ AB‘CD + ABCD +A‘B‘CD +A‘B‘C‘D+ A‘BC‘D
= m4+ m6+ m11+ m15+ m3+ m1+ m5
=∑m (1, 3, 4, 5, 6, 11, 15)
7. Implement the Boolean function using 8: 1 multiplexer.

F (A, B, C, D) = AB’D + A’C’D + B’CD’ + AC’D.
Solution:
Convert into standard SOP form,
= AB‘D (C‘+C) + A‘C‘D (B‘+B) + B‘CD‘ (A‘+A) + AC‘D (B‘+B)
= AB‘C‘D + AB‘CD+ A‘B‘C‘D + A‘BC‘D +A‘B‘CD‘ + AB‘CD‘ +AB‘C‘D+ ABC‘D
= AB‘C‘D + AB‘CD+ A‘B‘C‘D + A‘BC‘D +A‘B‘CD‘ + AB‘CD‘+ ABC‘D
= m9+ m11+ m1+ m5+ m2+ m10+ m13

= ∑m (1, 2, 5, 9, 10, 11, 13).
Implementation Table
8. Implement the Boolean function using 8: 1 multiplexer

F (A, B, C, D) = ∏m (0, 3, 5, 8, 9, 10, 12, 14)
Solution
•Variables, n= 4 (A, B, C, D)
•2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
• Multiplexer Implementation:
9. Implement the Boolean function using 8: 1 multiplexer

F (A, B, C, D) = ∑m (0, 2, 6, 10, 11, 12, 13) + d (3, 8, 14)
Solution
• Variables, n= 4 (A, B, C, D)
• Select lines= n-1 = 3 (S2, S1, S0)
• 2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
• Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
Implementation Table:
Multiplexer Implementation:
10. An 8×1 multiplexer has inputs A, B and C connected to the selection inputs S2,
S1, and S0 respectively. The data inputs I0 to I7 are as follows I1=I2=I7= 0;
I3=I5= 1; I0=I4= D and I6= D'.
Determine the Boolean function that the multiplexer implements.
F (A, B, C, D) = ∑m (3, 5, 6, 8, 11, 12, 13).
13. DEMULTIPLEXER
• Demultiplex means one into many. Demultiplexing is the process of taking
information from one input and transmitting the same over one of several
outputs.
• A demultiplexer is a combinational logic circuit that receives information on a
single input and transmits the same information over one of several (2n) output
lines.
Block diagram of demultiplexer
• The block diagram of a demultiplexer which is opposite to a multiplexer in its

operation is shown above. The circuit has one input signal, ‗n‘ select signals and
2n output signals. The select inputs determine to which output the data input will
be connected. As the serial data is changed to parallel data, i.e., the input caused
to appear on one of the n output lines, the demultiplexer is also called a ―data
distributer‖ or a ―serial-to-parallel converter‖ .
1-to-4 Demultiplexer
• 1-to-4 demultiplexer has a single input, Din, four outputs (Y0 to Y3) and two
select inputs (S1 and S0).
• The input variable Din has a path to all four outputs, but the input information is
directed to only one of the output lines. The truth table of the 1-to-4
demultiplexer is shown below.
Truth table of 1-to-4 demultiplexer
• From the truth table, it is clear that the data input, Din is connected to the output
Y0, when S1= 0 and S0= 0 and the data input is connected to output Y1 when
S1= 0 and S0= 1. Similarly, the data input is connected to output Y2 and Y3
when S1= 1 and S0= 0 and when S1= 1 and S0= 1, respectively. Also, from the
truth table, the expression for outputs can be written as follows,
Y0= S1’S0’Din
Y1= S1’S0Din
Y2= S1S0’Din
Y3= S1S0Din
Logic diagram of 1-to-4 demultiplexer
• Now, using the above expressions, a 1-to-4 demultiplexer can be implemented

using four 3-input AND gates and two NOT gates. Here, the input data line Din, is
connected to all the AND gates. The two select lines S1, S0 enable only one gate
at a time and the data that appears on the input line passes through the selected
gate to the associated output line.
1-to-8 Demultiplexer
1-to-8 demultiplexer has a single input, Din, eight outputs (Y0 to Y7) and three
select inputs (S2, S1 and S0). It distributes one input line to eight output lines
based on the select inputs. The truth table of 1-to-8 demultiplexer is shown below
• From the truth table, it is clear that the data input is connected with one of the
eight outputs based on the select inputs. Now from this truth table, the
expression for eight outputs can be written as follows:
• Now using the above expressions, the logic diagram of a 1-to-8 demultiplexer can
be drawn as shown below. Here, the single data line, Din is connected to all the
eight AND gates, but only one of the eight AND gates will be enabled by the
select input lines. For example, if S2S1S0= 000, then only AND gate-0 will be
enabled and thereby the data input, Din will appear at Y0. Similarly, the different
combinations of the select inputs, the input Din will appear at the respective
output.
Logic diagram of 1-to-8 demultiplexer
1. Design 1:8 demultiplexer using two 1:4 DEMUX.
2. Implement full subtractor using demultiplexer

14. PARITY GENERATOR/CHECKER
• When sender transmits data to the receiver, the data might get scrambled by noise or
data might get corrupted during the transmission.
Check bits:
• Check bits are bits of data used in serial communications to check for errors in data
before it is accepted.
Error Detection Codes :
• The binary information is transferred from one location to another location through some
communication medium. The external noise can change bits from 1 to 0 or 0 to 1.This
changes in values are called errors. For efficient data transfer, there should be an error
detection and correction codes. An error detection code is a binary code that detects
digital errors during transmission. A famous error detection code is a Parity Bit method.
• A Parity Generator is a combinational logic circuit that generates the parity bit in the
transmitter. On the other hand, a circuit that checks the parity in the receiver is called
Parity Checker. A combined circuit or device of parity generators and parity checkers are
commonly used in digital systems to detect the single bit errors in the transmitted data.
Parity Bit:
• A parity bit, also known as a check bit, is a single bit that can be appended to a binary
string. It is set to either 1 or 0 to make the total number of 1-bits either even ("even
parity") or odd ("odd parity").
• The purpose of a parity bit is to provide a simple way to check for errors later. When
data is stored or transferred electronically, it's not uncommon for bits to "flip" — change
from a ‘1’ to a ‘0’, or vice versa. Parity checks can detect these errors.
• For example, to check a binary sequence with even parity, the total number of ones can
be counted. If the number of ones is not even, an error is likely to have occurred.
• The inherent weakness in this type of error checking is that it can only detect an odd
number of errors in the sequence. If an even number of bits are flipped, a parity check
will not catch it.
Parity checking process: Example
• The data 10101 is given the even parity bit of 1, resulting in the bit sequence 101011.
• This data is transferred to another computer. In transit, the data is corrupted, and the
computer receives the incorrect data 100011.
• The receiving computer computes the parity: 1+0+0+0+1+1 = 3. It then performs 3
modulo 2 (the remainder of 3 divided by 2), expecting the result 0 which would indicate
that the number is even.
• Instead, it receives the result 3 modulo 2 = 1, indicating that the number is odd. Because
it is looking for numbers with even parity, it asks the original computer to send the data
again.
• This time, the data comes through with no errors: 101011. The receiving computer
calculates 1+0+1+0+1+1 = 4.
• 4 modulo 2 = 0, indicating even parity. The parity bit is stripped from the end of the
sequence, and the data 10101 is accepted.
94
Single Parity Check
• In this technique,
• One extra bit called as parity bit is sent along with the original data bits.
• Parity bit helps to check if any error occurred in the data during the transmission.
Steps Involved-
• Error detection using single parity check involves the following steps-
Step-01:
• At sender side,
• Total number of 1’s in the data unit to be transmitted is counted.
• The total number of 1’s in the data unit is made even in case of even parity.
• The total number of 1’s in the data unit is made odd in case of odd parity.
• This is done by adding an extra bit called as parity bit.
Step-02:
• The newly formed code word (Original data + parity bit) is transmitted to the
receiver.
Step-03:
• At receiver side,
• Receiver receives the transmitted code word.
• The total number of 1’s in the received code word is counted.
• Then, following cases are possible-
• If total number of 1’s is even and even parity is used, then receiver assumes that
no error occurred.
• If total number of 1’s is even and odd parity is used, then receiver assumes that
error occurred.
• If total number of 1’s is odd and odd parity is used, then receiver assumes that no
error occurred.
• If total number of 1’s is odd and even parity is used, then receiver assumes that
error occurred.
• Parity Check Example-
• Consider the data unit to be transmitted is 1001001 and even parity is used.
• At Sender Side-
• Total number of 1’s in the data unit is counted.
• Total number of 1’s in the data unit = 3.
• Clearly, even parity is used and total number of 1’s is odd.
• So, parity bit = 1 is added to the data unit to make total number of 1’s even.
• Then, the code word 10010011 is transmitted to the receiver.
• At Receiver Side-
• After receiving the code word, total number of 1’s in the code word is counted.
• Consider receiver receives the correct code word = 10010011.
• Even parity is used and total number of 1’s is even.
• So, receiver assumes that no error occurred in the data during the transmission.
• Advantages:
1. This technique is guaranteed to detect an odd number of bit errors (one, three,
five and so on).
2. If odd number of bits flip during transmission, then receiver can detect by
counting the number of 1’s.
• Limitations:
1. This technique can not detect an even number of bit errors (two, four, six and so
on).
2. If even number of bits flip during transmission, then receiver can not catch the
error.
KINDS OF PARITY BITS
• There are two kinds of parity bits:

1. Even Parity bit
2. Odd Parity Bit
• In even parity, the number of bits with a value of one are counted. If that
number is odd, the parity bit value is set to one to make the total number of ones
in the set (including the parity bit) an even number. If the number of bits with a
value of one is even, the parity bit value is set to zero, so that the total number of
ones in the set (including the parity bit) remains an even number.
• In odd parity, if the number of bits with a value of one is an even number, the
parity bit value is set to one to make the total number of ones in the set
(including the parity bit) an odd number. If the number of bits with a value of one
is odd, the parity bit value is set to zero, so that the total number of ones in the
set (including the parity bit) remains an odd number.
Table. 1. How to Adjust Parity bits for Even or Odd Parity
• At the receiving end, each group of incoming bits is checked to see if the group
totals to an even or odd number. If a transmission error occurs, the transmission
is retried or the system halts and an error message is sent to the user.
PARITY CHECKER CIRCUIT
• It is a logic circuit that checks for possible errors in the transmission.

• This circuit can be an even parity checker or odd parity checker depending on the
type of parity generated at the transmission end.
• When this circuit is used as even parity checker, the number of input bits must
always be even. When a parity error occurs, the ‘sum even’ output goes low and
‘sum odd’ output goes high.
• If this logic circuit is used as an odd parity checker, the number of input bits
should be odd, but if an error occurs the ‘sum odd’ output goes low and ‘sum
even’ output goes high.
a) EVEN PARITY CHECKER

• Consider that three input message along with even parity bit is generated at the
transmitting end. These 4 bits are applied as input to the parity checker circuit
which checks the possibility of error on the data.
• Since the data is transmitted with even parity, four bits received at circuit must
have an even number of 1s.
• If any error occurs, the received message consists of odd number of 1s.
• The output of the parity checker is denoted by PEC (parity error check).
• The below table shows the truth table for the even parity checker in which
• PEC = 1 if the error occurs, i.e., the four bits received have odd number of 1s and
PEC = 0 if no error occurs, i.e., if the 4-bit message has even number of 1s
98
• The above truth table can be simplified using K-map as shown below.
• The above logic expression for the even parity checker can be implemented by
using three Ex-OR gates as shown in figure. If the received message consists of
five bits, then one more Ex-OR gate is required for the even parity checking.
b) Odd Parity Checker
• Consider that a three bit message along with odd parity bit is transmitted at the
transmitting end.
• Odd parity checker circuit receives these 4 bits and checks whether any error are
present in the data.
• If the total number of 1s in the data is odd, then it indicates no error, whereas if
the total number of 1s is even then it indicates the error since the data is
transmitted with odd parity at transmitting end.
• The below figure shows the truth table for odd parity checker.
Truth Table for Odd Parity Checker
• The truth table of the odd parity generator can be simplified by using K-map as
• If the four-bit received message consists of an odd number of 1 means, no error
has occurred. If it contains an even number of 1 means, an error has occurred.
• Odd parity checker for three input message signal and odd parity bit can be
implemented with three EX-NOR Gates.
• E = (A Ex-NOR B) Ex-NOR (C Ex-NOR D)
• the outputs of an EXNOR gate are the inverse to that of the EXOR gate.
• The output parity bit expression for this generator circuit is obtained as
P = (A ⊕ B ⊕C)’
• The logic circuit for odd parity generator is shown below
Figure 3 Bit Odd Parity Checker circuit

PARITY GENERATOR
Parity Generator
• It is combinational circuit that accepts an n-1 bit data and generates the
additional bit that is to be transmitted with the bit stream. This additional or extra
bit is called as a Parity Bit.
• In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in
the data stream and the parity bit is ‘1’ if there are odd number of 1s in the data
stream.
• In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the
data stream and the parity bit is ‘0’ if there are odd number of 1s in the data
stream. Let us discuss both even and odd parity generators.
a) EVEN PARITY GENERATOR

• Let us assume that a 3-bit message is to be transmitted with an even parity bit.
Let the three inputs A, B and C are applied to the circuit and output bit is the
parity bit P. The total number of 1s must be even, to generate the even parity bit
P.
• The table below shows the truth table of even parity generator in which 1 is
placed as parity bit in order to make all 1s as even when the number of 1s in the
truth table is odd.
• The K-map simplification for 3-bit message even parity generator is

• From the above truth table, the simplified expression of the parity bit can be
written as
a) ODD PARITY GENERATOR

The Parity Generator
It is a combinational circuit that takes n-bit of information (data) and generates
an additional bit to be transmitted along with the n-bit data.
In the Odd Parity scheme, if the number of 1’s is even in the data stream then ‘1’
is the parity bit but when the number of 1’s is odd then ‘0’ is used as the parity
bit.
a) Odd Parity Generator

Let us consider a 2-bit message to be transmitted with an even parity bit. Let the
2 inputs A & B are applied to the circuit and Y is the output bit parity. Now to
generate the even parity bit Y, the total number of 1’s must be odd.
The below-shown is the truth table of Even Parity generator where the output
(parity bit generator) becomes 1 when the number of inputs is odd else output
remains 0.
Truth Table for Odd Parity Generator
• The K-map simplification for the 2-bit message even parity generator is
From the above table, the simplified expression of parity bit can be given as:
Y= A’ B + A B’
Y= A ⊕ B
The above expression could be implemented using an Ex-OR gate. The logic
diagram is as shown below. The 2-bit message along with the parity bit is
transmitted to the receiving end where the checker circuit checks for the
error.
104
3-bit Odd Parity Generator
• Suppose at the transmitting end now we have a 3-bit message signal, and we
wish to transmit it using odd parity.
• Then, the parity bit generated, P, would be as a result of odd parity generation.
• The total number of 1s in the input bits must be odd for the odd parity bit. If the
total number of 1s in input bits is odd, then P gets the value 0, and if it is even
then, P is assigned the value 1.
3-bit Odd Parity Generator truth table
Parity Generator/ Checker
• A Parity is a very useful tool in information processing in digital computers to
indicate any presence of error in bit information. External noise and loss of signal
strength causes loss of data bit information while transporting data from one
device to other device, located inside the computer or externally. To indicate any
occurrence of error, an extra bit is included with the message according to the
total number of 1s in a set of data, which is called parity.
• If the extra bit is considered 0 if the total number of 1s is even and 1 for odd
quantities of 1s in a set of data, then it is called even parity. On the other hand,
if the extra bit is 1 for even quantities of 1s and 0 for an odd number of 1s, then
it is called odd parity.
• The message including the parity is transmitted and then checked at the
receiving end for errors. An error is detected if the checked parity does not
correspond with the one transmitted. The circuit that generates the parity bit in
the transmitter is called a parity generator and the circuit that checks the parity in
the receiver is called a parity checker.
Parity Generator:
• A parity generator is a combination logic system to generate the parity bit at the
transmitting side. A table illustrates even parity as well as odd parity for a
message consisting of three bits.
• If the message bit combination is designated as A, B, C and Pe, Po are the even
and odd parity respectively, then it is obvious from table that the Boolean applied
to a parity checker circuit expressions of even parity and odd parity are
Truth table
106
• If the message bit combination is designated as A, B, C and Pe, Po are the even and
odd parity respectively, then it is obvious from table that the Boolean expressions of
even parity and odd parity are applied to a parity checker circuit. The circuit that
checks the parity at the receiver side is called the parity checker. The parity checker
circuit produces a check bit and is very similar to the parity generator circuit. If the
check bit is 1, then it is assumed that the received data is incorrect. The check bit will
be 0 if the received data is correct. The table shows the truth table for the even parity
checker.
k-map Simplification
P= A’B’C+ A’BC’+ A’B’C’+ ABC

=A’ (B’C+ BC’) + A (B’C’+ BC)
=A’ (BÅC) + A (BÅC)’
=AÅ(BÅC)
Logic Diagram
The circuit that checks the parity at the receiver side is called the parity checker. The
parity checker circuit produces a check bit and is very similar to the parity generator
circuit. If the check bit is 1, then it is assumed that the received data is incorrect. The
check bit will be 0 if the received data is correct. The table shows the truth table for the
even parity checker.
107
Logic Diagram
108
Video Links
Sl. Topic Video Link
No.
1 Combination Circuit Design https://www.youtube.com/w
atch?v=uv_RJ1
Pv71s
2 Arithmetic Circuits https://www.youtube.com/w
atch?v=NAqR-
OGjgoQ
3 Carry Look Ahead Adders https://www.youtube.co
m/watch?v=36hCiz
Ok4PA
4 Magnitude Comparator https://spocathon.page/vi
deo/lecture-
26-magnitude-comparator
5 Encoders and Decoders https://www.youtube.co
m/watch?v=RZQTTf
U9TNA
6 Multiplexers https://www.youtube.com
and /watch?v=kxHRk7
DeMultiplexers Yczac
7. Decoder, https://drive.google.com/driv
Multiplexer, e/folders/17Xdb8c6FPDczKrk
Demultiplexer KK7woEQhrTDfxZfWy?usp=sh
aring
E-BOOKS
E-Books
1. Digital Fundamentals_ Global Ed – Thomas L Floyd
2. Digital Principles And Application - Leach &Malvino

3. Digital Design - M. Morris Mano and Michael D. Ciletti
4. Fundamentals of Digital Logic with Verilog Design-Stephen Brown and
Zonko Vranesic
ONLINE LEARNING MATERIALS:

1:http://nptel.iitm.ac.in/ video.php? subject Id=117106086
2:http://nptel.iitm.ac.in/courses/117101001
3: https://youtu.be/C-oAyXibnJU
4 https://youtu.be/oYRMYSIVj1o
5: https://www.youtube.com/watch?v=XZmGGAbHqa0
6: https://www.youtube.com/watch?v=KymIDyQiXZI
eBooK Links:
https://www.ebooknetworking.net/ebooks/dpsd-godse-book.html
https://www.vidyarthiplus.com
ASSIGNMENTS
Assignment 1: Home Security System Logic Design
A home security system is being designed with the following features:
•An alarm should be triggered if motion is detected and it's nighttime.
•The alarm should also go off if there's a breach in the door contact sensor.
a)Formulate the Boolean function for the security system's alarm trigger.
Express the function in terms of motion detection (M), nighttime (N), and
door contact breach (D). Provide the minterms, maxterms, Sum of Product
(SOP), and Product of Sum (POS) forms.
b)Derive the truth table for the Boolean function.
c)Design a logic circuit using appropriate logic gates to implement the security
system's alarm trigger.
Assignment 2: Elevator Control Logic
An elevator control system is to be designed with the following conditions:
•The elevator should only move between floors if a valid floor request button
is pressed and the doors are closed.
•If the emergency stop button is pressed, the elevator should halt its
operation immediately.
a)Define the Boolean function for controlling the elevator's movement based
on the conditions: valid floor request (F), doors closed (D), and emergency
stop (E). Present the minterms, maxterms, SOP, and POS forms.
b)Construct the truth table representing the Boolean function.
c)Create a logic circuit diagram using suitable logic gates to implement the
elevator control system.

ASSIGNMENTS
Assignment 3: Temperature Regulation System Logic
A temperature regulation system is being developed with the following
specifications:
•The heating element should turn on if the room temperature falls below a
certain threshold and it's daytime.
•The cooling system should engage if the room temperature exceeds a certain
threshold and it's nighttime.
a)Develop the Boolean function representing the temperature regulation
system's operation, considering room temperature (T), daytime (D), and
nighttime (N). Provide the minterms, maxterms, SOP, and POS expressions.
b)Construct the truth table corresponding to the Boolean function.
c)Design a logic circuit using suitable logic gate components to implement the
temperature regulation system.

Part A - Questions & Answers
1. Define combinational circuit [CO2,K2]
A combinational circuit consists of logic gates whose outputs at any time are
determined directly from the present combination of inputs, without regard to
previous inputs.
2. Differentiate combinational and sequential circuits

[CO2,K2]
3. Mention the classification of logic circuits

[CO2,K2]
4. List the procedure for designing combinational logic circuits [CO2, K2]
Any combinational circuit can be designed by the following steps of design
procedure.
• The problem is stated.
• Identify the input and output variables.
• The input and output variables are assigned letter symbols.
• Construction of a truth table to meet input -output requirements.
• Writing Boolean expressions for various output variables in terms of input

variables.
• The simplified Boolean expression is obtained by any method of minimization—

algebraic method, Karnaugh map method, or tabulation method.
• A logic diagram is realized from the simplified boolean expression using logic
gates.
5. Define half adder [CO2, K2]

A half-adder is a combinational circuit that can be used to add two binary bits. It has
two inputs that represent the two bits to be added and two outputs, with one
producing the SUM output and the other producing the CARRY.
6. Give the truth table for half adder [CO2, K2]
7. Draw the logic diagram for half adder [CO2, K2]
8. Define full adder [CO2, K2]
A full adder is a combinational circuit that forms the arithmetic sum of three input
bits. It consists of 3 inputs and 2 outputs
9. Give the truth table for full adder [CO2, K2]
10. Draw the logic diagram for full adder [CO2, K2]
11. Draw the logic diagram for full adder using two half adders [CO2, K2]
12. What is carry propagation delay? [CO2, K2]
In Parallel adder, all the bits of the augend and the addend are available for
computation at the same time. The carry output of each full-adder stage is connected
to the carry input of the next high-order stage. Since each bit of the sum output
depends on the value of the input carry, time delay occurs in the addition process. This
time delay is called as carry propagation delay.
13. What is binary parallel adder? [CO2, K2]

A binary parallel adder is a digital function that produces the arithmetic sum of two
binary numbers in parallel. It consists of full adders connected in cascade, with
output carry from one full adder connected to the input carry of the next full adder.
14. What is the propagation time for an n-bit parallel adder? [CO2, K2]
For an n-bit parallel adder, there are 2n gate levels for the carry to propagate
through.
15. What are the disadvantages of parallel adder? [CO2, K2]

a) The carry propagation time is the limiting factor on the speed with which two
numbers are added in parallel.
b)The outputs will not be correct unless the signals are given enough time to
propagate through the gates connected from the inputs to the outputs.
c)Since, all the arithmetic operations are implemented by successive additions, the
time consumed during the addition process is very critical.
16. Mention the two ways for reducing the carry propagation time [CO2, K2]
a) Employ faster gates with reduced delays
a) Employ the principle of Carry look-a-head
17. What is carry look-a-head adder? [CO2, K2]

A carry look-a-head adder is a combinational circuit which generates and propagates the
carry to all levels of the gates immediately when the input is applied to the parallel
adder.
18. What is carry generate and carry propagate? [CO2, K2]

Carry generate given by Gi = AiBi, produces an output carry when both Ai and Bi are ‘1’,
regardless of the input carry. Carry propagate given by Pi = Ai ⊕ Bi, is associated with
the propagation of carry from Ci to Ci+1
19. What is encoder? (CO2, k1)

An encoder is a digital circuit that performs the inverse operation of a decoder. An
encoder has 2n input lines and n output lines. The block diagram of encoder is shown
below.
20. What is priority encoder? (CO2, k1)

A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if two or more inputs are equal to 1 at the same time, the input having the
highest priority will take precedence.
Part A -Questions &
Answers
21) Define multiplexer. (CO2, k1)
A multiplexer or MUX is a combinational circuit that accepts maximum of 2 n data

inputs, ‘n’ selection lines and produces single output line.
22) List out the uses of MUX (CO2, k1)
• They can be used as data selector.
• They can be used to implement combinational digital circuits.

• Using a single transmission line, various types of data (video, audio,..) are
transmitted at the same instant.
22) Draw the circuit for 2 X 1 line multiplexer. (CO2,K3)

The digital circuit for 2X1 MUX accepts two inputs, one selection line and has
single output line. The circuit for 2X1 line multiplexer is as follows.
Part A -Questions & Answers
24) Define a half subtractor and a full subtractor. Develop the truth tables
and logic equations for both circuits. (CO2, k1)
• A half subtractor calculates the difference (D) and borrow-out (B_out) for 1-bit
inputs A and B.
• A full subtractor extends the half subtractor by including a borrow-in (B_in) input.
It produces a difference and borrow-out.
Truth Table:
A B D B_out
0 0 0 0
0 1 1 1
1 0 0 0
1 1 0 0
Logic Expressions:
• Half Subtractor: D = A XOR B, B_out = A' AND B
• Full Subtractor: D = A XOR B XOR B_in, B_out = (A AND B') OR (B_in AND (A XOR
B'))
25) Describe the concept of a carry look-ahead adder. Outline the

advantage of using this type of adder compared to a ripple carry adder.
(CO2, k1).
A carry look-ahead adder reduces propagation delay by calculating carry signals in

advance. It uses precomputed formulas for carry generation.
Advantage: Unlike ripple carry, the carry look-ahead adder minimizes the
dependency on previous carry bits, resulting in faster addition operations.
Carry and Sum Expressions:
Carry for bit i: G_i = A_i AND B_i, P_i = A_i XOR B_i
Carry-out for bit i: C_i = G_i OR (P_i AND C_(i-1))
Sum for bit i: S_i = P_i XOR C_(i-1)
Part A -Questions & Answers
26) Elaborate on the purpose of a magnitude comparator in digital
systems. (CO2, k1)
A magnitude comparator determines the relationship between two binary numbers,

identifying whether one is greater, equal, or less than the other.
27) Describe the operation of a binary parallel adder. (CO2, k1)

A binary parallel adder is a combinational circuit that adds two binary numbers in
parallel by considering each bit position simultaneously and generating the sum and
carry outputs for each bit position.
28) What is the significance of the carry input and carry output in a full
adder? (CO2, k1)
The carry input (C_in) represents the carry generated from the previous bit's
addition, while the carry output (C_out) indicates whether there is a carry generated
in the current bit position.
29) What is the advantage of using a carry look-ahead adder compared to

a ripple carry adder? (CO2, k1)
A carry look-ahead adder significantly reduces the propagation delay in adding binary
numbers by calculating carry signals in advance. This results in faster addition
operations compared to the ripple carry adder.
30) Briefly explain the concept of carry propagation and carry generation.
(CO2, k1)
A carry look-ahead adder significantly reduces the propagation delay in adding binary
numbers by calculating carry signals in advance. This results in faster addition
operations compared to the ripple carry adder.
Part B Questions
Q. Questions K CO
No. Level Mapping
1 What are the design procedures for combinational K1 CO2
circuit?
2 Design a combinational logic circuit whose outputs K3 CO2

are
F1 = a’bc + ab’c and
F2 = a’ + b’c + bc’
3 Design a half-adder and Full-adder circuit. K3 CO2
4 Draw the four bit binary parallel adder circuit. K3 CO2

Examine the carry propagation from one stage
to next stage and describe the operation.
5 Derive the Boolean expression for Carry Generate K2 CO2

and Carry Propagate for implementing carry look-a-
head adder. Describe the operation of carry look-a-
head adder using the logic diagrams.
6 Design a half-subtractor and Full-subtractor. K3 CO2
7 Design a 4-bit adder-subtractor using full adders. K2 CO2
8 Design a combinational circuit for BCD adder. K3 CO2
9 Design a 2-bit by 2-bit binary multiplier. K2 CO2
10 Design a 4-bit by 3-bit binary multiplier. K2 CO2
11 Design a magnitude comparator to compare two 4- K3 CO2

bit binary numbers.
12 Design a magnitude comparator to compare two 2- K3 CO2
bit binary numbers.
13 Design a 3-to-8 line decoder using combinational K3 CO2
circuits.
14 Construct a larger decoder using smaller decoders: K3 CO2
(a)4 x 16 line Decoder using 3 x 8 line
Decoders
(b)5 x 32 line Decoder using 3 x 8 line
Decoders and 2 x 4 line Decoder
15 Implement a Full Adder and Full Subtractor using a 3 x K3 CO2
8 line Decoder.
Part B Questions
Q. Questions K CO
No. Level Mapping
16 Implement a full subtactor with a decoder. K3 CO2
17 Design an Octal-to-Binary Encoder. K3 CO2
18 Design a 4-input priority encoder. K3 CO2
19 Design a 2-to-1-line and a 4-to-1-line Multiplexer. K3 CO2
20 Design a Quadruple 2-to-1-line Multiplexer. K3 CO2
21 Implement a full adder & full subtractor with a 4-to- k3 CO2

1-line MUX.
22 Implement the following Boolean function using 4 x 1 K3 CO2
multiplexer.
F(X,Y,Z) = ∑ m (1, 2, 6, 7)
23 Implement F(A, B, C) = ∑ m (1, 2, 4, 5) with a K3 CO2
multiplexer.
24 Implement F(A, B, C) = ∑ m (1, 3, 5, 6) with a 4:1 K3 CO2

multiplexer.
25 Implement the following Boolean function using a K3 CO2

8:1 multiplexer.
F(W,X,Y,Z) = ∑ m (0, 1, 3, 4, 8, 9, 15)
26 Implement the following Boolean function using 4:1 K3 CO2
multiplexer.
F(W,X,Y,Z) = ∑ m (1, 2, 3, 6, 7, 8, 11, 12, 14)
27 Implement the switching function F= ∑ m (0, 1, 3, 4, K3 CO2
12, 14, 15) using an 8 input multiplexer.
28 Implement F(A, B, C, D) = ∑ m (1, 3, 4, 11, 12, 13, K3 CO2
14, 15) using 8 x 1 multiplexer.
29 Implement the following Boolean function with 16 x 1 K3 CO2
multiplexer:
F(A, B, C, D) = ∑ m (0, 1, 3, 4, 8, 9, 15)
Use block diagram for representation.
30 Implement a full adder with two 4 x 1 multiplexers. K3 CO2
31 Design a combinational logic using a K3 CO2

suitable multiplexer to realize the following
Boolean expressions:
Y = AD’ + B’C + BC’D’
Part B Questions
Q. Questions K CO
No. Level Mapping
32 Implement the following Boolean function using 8:1 K3 CO2
MUX.
F(A,B,C,D) = ABD + ACD + BCD +ACD’
33 Explain with necessary diagram design a BCD to 7 K3 CO2

segment display decoder.
34 Implement the following Boolean function with a 4 X 1 K3 CO2
multiplexer and external gates. Connect inputs A and B
to the selection lines. The input requirements for the
four data lines will be a function of variables C and D.
these values are obtained by expressing F as a function
of C and D for each of the four cases when AB=00, 01,
10 and 11. These functions may have to be
implemented with external gates.
F(A,B,C,D)= ∑ m (1,3, 4, 11, 12, 13, 14, 15)
35 Construct a 16 X 1 multiplexer with two 8 X 1 and K3 CO2
one 2 X 1 multiplexers.
Supportive online
Certification
courses (NPTEL,
Swayam, Coursera,
Udemy, etc.,)
Supportive Online Certification Courses
Swayam:
• Digital Circuits By Prof. Santanu Chattopadhyay IIT
Kharagpur
• https://swayam.gov.in/nd1_noc19_ee51/preview
Coursera:
• Digital Systems: From Logic Gates to Processors
offered by Universitat Autònoma de Barcelona
• https://www.coursera.org/learn/digital-systems
Classcentral.com:
• Online Course - Digital Electronic Circuits by
Indian Institute of
Technology, Kharagpur and NPTEL via Swayam
• https://www.classcentral.com/course/swayam-
digital-electronic-circuits- 12953
Udemy:
• Master The Digital Electronics- Minimisation And
Basic Gates – [Learn about the digital gates, boolean
algebra, k-map| Update your digital from base to pro]
• https://www.udemy.com/course/professional-digital-
electronics/
Real Time Applications
1. Error Detection in Computer Networks-
• When sender transmits data to the receiver, the data might get scrambled by noise or
data might get corrupted during the transmission.
2. Parity checking in a real-time digital communications system
• In a digital communication system for voice signals, a system and method for
improving the quality of a received signal.
• The invention comprises a system for arranging the data and parity bits in a data
frame and a corresponding method for analyzing and using the received frames.
• In the present invention, the data are conveyed in short independent segments, such
as one or a few ADPCM nibbles. The length of each segment is chosen to be short
enough that the loss of one segment of data from the received signal does not
significantly degrade the quality of the output analog signal.
• The transmitter generates a parity bit for each of these segments and composes
transmit frames by alternating data segments with their corresponding parity bits.
The receiver then receives each data segment along with its corresponding parity bit.
• This arrangement allows the receiver to identify specific received segments that
contain errors, and minimizes the receiver's delay between receiving the segment and
determining if contains an error.
• The invention also comprises a system and method for detecting such an erroneous
segment and blanking it. If a received frame contains more than a threshold number
of erroneous segments, then the remaining segments of the frame can be muted.
Subsequent frames can then also be muted until one of the subsequent frames
contains fewer than a second threshold number of errors.
127
Real time Applications
APPLICATION OF MULTIPLEXER
APPLICATION OF DEMULTIPLEXER
Real time Applications
APPLICATION OF ENCODER & DECODER
TRANSMISSION OF DATA IN A SECURED FORM.

Real time Applications in day to
day life and to Industry
FPGA APPLICATION IN EMBEDDED SYSTEMS
The fast growing embedded market is one of most diverse in terms of end
application. Embedded includes traditional general purpose ‘embedded CPU’
platforms such as Medical, Robotics, Industrial Control, and Data Acquisition,
but can also include Video Surveillance, Automotive, Point-of-Sale, and other
more specialized applications. Pericom offers a wide variety of support
products for all of these sub segment platforms, ranging from specialized
Timing products like processor specific XO and clocks, to Bridge that can
connect the latest PCIe based embedded processor families to legacy
protocols such as PCI-X, PCI, USB, UART, and more. In fact, Pericom
Timing, Switching, and Signal Conditioning products are already used in
most embedded platform applications with the most popular embedded
processors. Embedded processors can include CPU chipsets from major CPU
vendors, SOC, and FPGA from major vendors which are used across all
embedded segments. As an example, the FPGA-Pericom block diagram
illustrates the many I/O, power management, and timing functions that
Pericom can provide.
Real Time examples
Types of Encoders: Rotary, Linear, Position,
and Optical Encoder Types
• Linear Encoders
Linear encoders deal with the movement of objects along a path or
line, such as in the cut-to-length application mentioned earlier. This
type of encoder makes use of a transducer to measure the
movement or distance between two points, sometimes employing a
cable (longer distances) or a small rod (shorter distances). In these
cases, a cable is run between the encoder transducer and the moving
object. As the object moves, the transducer gathers data from the
cable and produces an analog or digital output signal that is used to
establish the object’s movement or position.
• Rotary Encoders
Rotary encoders are used to provide feedback about the movement
of a rotating object or device, such as the shaft of a motor. The
rotary encoder converts the angular position of the moving shaft into
an analog or digital output signal that will then enable a control
system to establish the shaft’s position or speed.
131
• Rotary encoders may contain shafts or can be of a design that is
known as thru-bore encoders, meaning that they are capable of
being directly mounted on top of a rotating shaft such as that of a
motor. Thru-bore encoders are available with a wide variety of
sizes and feature clamp or set screw mounting options making
them suitable for attachment in machine design applications.
Flanges are used to position the encoder and to keep it from
rotating with the moving shaft.
• Angle encoders are similar to rotary encoders in that they monitor
and provide feedback on rotational movement, but they are
different in that angle encoders tend to offer higher accuracy.
• Both linear and rotary encoders are available as either absolute or
incremental encoders, which describes the desired signal output
for the encoder. With an absolute encoder, the output signal
generated by the device results in a unique set of digital bits that
correspond to a specific position of the object being measured.
Even if power is lost, the absolute encoder by its design can
determine the position of the object since there is a specific digital
signal associated with every position.
• Rotary absolute encoders are available in both single-turn and
multi-turn designs. Single-turn encoders are capable of providing
information within any one shaft rotation. Multi-turn encoders are
capable of providing information about the position over many
rotations of shaft position, even large numbers of rotations.
• Absolute encoders are used in applications where knowing the
exact position of an object is important. They are also used in
situations where the machine or process is inactive for a large
percentage of time or moves at a very slow rate.
• Incremental encoders use a simpler method of counting
movement and rely on establishing the position of the object by
counting the number of pulses and then using that count to
compute the position. Because they rely on pulse counting, there is
no unique digital signature that can be used to determine an
absolute position.
132
• Hence in the event of a power loss, incremental encoders must be
referenced to a home position or reference point so that the
counter can be reset and then used to compute relative
movement. One way to think about the difference is that
incremental encoders measure the relative movement against
some point of reference, whereas absolute encoders measure the
position directly using a unique signal code that directly reflects
the position.
Encoder Sensing Technologies

There are several different sensing technologies that may be used
within an encoder to detect motion or position. The most common
sensing technologies that are used in encoder designs include:
• Optical
• Magnetic
• Capacitive
• Optical Encoders
Optical encoders are the most accurate of all the sensing methods. A
rotary optical encoder consists of a light source such as an LED and a
rotating disk that is patterned with a series of opaque lines and
alternating translucent slots. As the light passes through the rotating
disk, a photosensor mounted on the opposite side of the disk detects
the light and generates a sinusoidal electrical signal that corresponds
to the presence of light detected from the translucent slots and the
absence of light from the opaque lines. An electrical circuit then
converts the sinusoidal signal to a square wave signal, which is a
series of high and low pulses. These pulses are sent to a control
circuit that can be used to measure the pulse count as the encoder
rotates and use that data to determine a position for the rotating
shaft or to control some action based on movement or position.
133
• Magnetic encoders rely on the detection of a change in magnetic
flux to establish the movement and position of an object. A
magnetic rotary encoder consists of a magnetized disk that has a
number of magnetic poles located along its circumference. A
sensor is positioned next to the disk, and as the disk rotates, the
sensor detects the change in the magnetic field as the different
poles in the disk surface pass near the sensor. The changing
magnetic field is used to generate a sinusoidal output signal that
can be converted to a square pulse for counting by a control
circuit. The sensor used in these encoders can either make use of
the Hall effect, which detects a change in voltage or can be
a magnetoresistive sensor that can detect the change in the
magnetic field directly.
• Capacitive encoders are a relatively new sensing technology for

encoder design. The operating principle relies on the detection of a
change in capacitance using a high-frequency reference signal.
With a rotary capacitive encoder, for example, a three-part
arrangement is used to enable signal encoding – a stationary
transmitter, a rotor, and a stationary receiver. The transmitter
generates a high-frequency electrical signal or current that passes
through the rotor towards the receiver. A sinusoidal pattern
stamped on the rotor in metal modulates the AC signal as the rotor
rotates, and the receiver converts the modulated signal into a
series of output pulses that can be used to establish increments of
rotary motion. The rotor generates a changing capacitive reactance
between the signal generated by the transmitter and the metal on
the rotor, which causes a predictable and repeatable distortion in
the AC field.
134
Quadrature encoders
• While single-channel encoders can be used to establish motion and
movement, they suffer from the limitation that they cannot sense
the direction of movement. In a rotary encoder, for example, a
clockwise movement will generate the same output signal as a
counter clockwise movement, therefore the electrical output of
the encoder cannot detect the direction of rotation, only the
magnitude of the motion. This shortcoming can be eliminated by
making use of what is known as a quadrature encoder.
• Quadrature encoders make use of two output channels whose
electrical output signals are out-of-phase. To accomplish this, the
code disk inside of a quadrature encoder will contain two tracks –
one for each of the two signal channels A and B. The coding of
these tracks on the code disk is such that when signals are
generated (say by using an optical light source), the square wave
pulse from channel A is electrically 90o out of phase with the
square wave pulse from channel B. For the case of a rotary
encoder that is rotating in a clockwise direction, for example, the
channel A square wave pulses will “lead” those of channel B, and
when the rotational direction is switched to counter clockwise, the
channel B pulses will lead those of channel A. The use of two signal
channels that are phase-shifted therefore allows the control circuit
receiving the encoder output pulses to distinguish directionality of
motion. The same principle applies to linear motion encoders.
• Incremental quadrature encoders often add an additional signal
channel called a marker or index that serves to establish a
reference point which can then be used to establish the position as
well as the direction of movement.
135
1. Multiplexers:
• A multiplexer (MUX) selects one of many input signals and forwards
the selected input to a single output line. Real-time applications
include:
• Data Routing in Communication Systems:
• Multiplexers are used to manage data transmission between multiple sources and a
single line, optimizing bandwidth and reducing data traffic in systems like fiber-optic
communications or satellite transmission.
• Processor Control and Signal Selection:
• In microprocessor systems, multiplexers are used to select between different data
sources or instructions for processing, enhancing the overall efficiency of the
processor.
• Real-Time Video Streaming:
• Multiplexers are used in video systems to combine multiple video signals for
transmission over a single channel, facilitating multi-camera surveillance systems or
broadcasting multiple video feeds.
• Data Acquisition Systems:
• In real-time data acquisition, multiplexers select various sensor signals to be
processed, minimizing the need for multiple ADCs (Analog-to-Digital Converters).
2. Encoders:
• An encoder converts multiple input signals into a coded output
signal, typically reducing the number of required lines. Applications
include:
• Keyboard Encoding:
• Keyboard encoders translate key presses into binary codes that are processed by the
computer, reducing the number of connections required between the keyboard and
processor.
• Robotic Control Systems:
• In robotic systems, encoders convert angular or linear positions of joints and motors
into digital signals, which are then used for feedback control.
• Wireless Communication:
• Encoders are used to encode data for efficient transmission over wireless channels,
reducing errors and ensuring proper signal reconstruction.
• Memory Address Decoding:
• Encoders simplify the process of selecting memory addresses in large-scale memory
systems, enabling efficient read/write operations in real-time computing.
136
3. Decoders:
• A decoder performs the reverse function of an encoder,
converting coded signals back into their original form or
selecting among many possible lines. Applications include:
• Real-Time Display Systems:
• Decoders are used in display systems to convert encoded video or graphical
data into a format that can be rendered on screens, enabling real-time video
playback.
• Address Decoding in Memory Systems:

• In microprocessor systems, decoders are used to select specific memory
addresses based on a given binary address, improving data retrieval times.
• Error Detection and Correction:

• Decoders are employed in communication systems to interpret received
signals and identify/correct any errors introduced during transmission.
• Microcontroller Systems:
• Decoders are often used in microcontroller-based applications for enabling
specific peripheral devices, such as selecting an I/O port for communication.
137
REAL TIME APPLICATIONS IN DAY TO DAY
LIFE AND TO INDUSTRY
• A real-life example of an encoder is a QR code scanner.
• Encoding Information: A QR code encodes information such as

URLs, text, or contact details into a two-dimensional barcode
format.
• Decoding: When you scan the QR code with a smartphone

camera or a dedicated QR code scanner, the device uses an
encoder-decoder mechanism to interpret the encoded data and
convert it back into a readable format.
• Other Examples:
• Audio Encoding: Converting audio signals into digital formats,

such as MP3 or AAC, which allows for efficient storage and
transmission of music files.
• Video Encoding: Compressing video files into formats like H.264

or HEVC for streaming or storage.
• Data Compression: ZIP files encode multiple files into a single

compressed format for easier sharing and storage.
REAL TIME APPLICATIONS IN DAY TO DAY
LIFE AND TO INDUSTRY
Rotary encoders are commonly used in Industries
Rotary encoders enhance performance and safety in various

automotive applications by providing accurate position data.
Position Tracking: Rotary encoders measure the rotational

position of a shaft or axle. They convert angular movement into an
electrical signal.
Feedback: This information is crucial for applications like steering

systems, motor control, and robotic arms, providing real-time
feedback on position and speed.
Applications:
Electric Vehicles: Used to monitor wheel rotation for stability

control systems.
Industrial Automation: Helps in precise control of machinery

and robotics.
Content Beyond Syllabus
Code Converters
• A code converter is a logic circuit that changes data presented in one type of
binary code to another code of binary code. The following are some of the most
commonly used code converters:
Binary to Gray Converters

• The gray code is often used in digital systems because it has the advantage that
only one bit in the numerical representation changes between successive
numbers. The truth table for the binary-to-gray code converter is shown below,
141
K-map simplification
LOGIC DIAGRAM
142
Gray to Binary Converters
The truth table for the gray-to-binary code converter is shown below,
143
K-map
144
Now, the expressions can be implemented using EX-OR gates
BCD –to-Excess-3 Converters:
Excess-3 is a modified form of a BCD number. The excess-3 code can be derived
from the natural BCD code by adding 3 to each coded number. For example, decimal
12 can be represented in BCD as 0001 0010. Now adding 3 to each digit we get
excess-3 code as 0100 0101 (12 in decimal). With this information the truth table for
BCD to Excess-3 code converter can be determined as,
145
BCD to Excess-3 Converters
K-map
146
Excess-3 to BCD Converter
Truth table:
• From the truth table, the logic expression for the Excess-3 code outputs can be
written as,
• B3= ∑m (11, 12) + ∑d (0, 1, 2, 13, 14, 15)
• B2= ∑m (7, 8, 9, 10) + ∑d (0, 1, 2, 13, 14, 15)
• B1= ∑m (5, 6, 9, 10) + ∑d (0, 1, 2, 13, 14, 15)
• B0= ∑m (4, 6, 8, 10, 12) + ∑d (0, 1, 2, 13, 14, 15)
147
K-map
148
• The steps involved in the BCD-to-binary conversion process are as follows:
• The value of each bit in the BCD number is represented by a binary equivalent or
weight.
• All the binary weights of the bits that are 1‘s in the BCD are added.
• the result of this addition is the binary equivalent of the BCD number
• Two-digit decimal values ranging from 00 to 99 can be represented in BCD by two
4-bit code groups. For example, 1910 is represented as,
• The left-most four-bit group represents 10 and right-most four-bit group

represents 9.
• The binary representation for decimal 19 is 1910 = 110012.
149
BCD to Binary Converters (K-map)
150
151
Binary to BCD Converter
The truth table for binary to BCD converter can be written as,
From the truth table, the logic expression for the BCD code outputs can be written
as,
• B0= ∑m (1, 3, 5, 7, 9, 11, 13, 15)
• B1= ∑m (2, 3, 6, 7, 12, 13)
• B2= ∑m (4, 5, 6, 7, 14, 15)
• B3= ∑m (8, 9)
• B4= ∑m (10, 11, 12, 13, 14, 15)
152
K-map Simplification
153
Binary to BCD Converter
From the above K-map, the logical expression can be obtained as, B0= A
• B1= DCB’+ D’B
• B2= D’C+ CB
• B3= DC’B’
• B4= DC+ DB
Now, from the above expressions the logic diagram can be implemented as,
154
Gray to BCD Converter
The truth table for gray to BCD converter can be written as,
155
From the above K-map, the logical expression can be obtained as,
B0= (G0ÅG1) Å (G2ÅG3)
B1= G’2G1+ G’3G2G’1
B2= G’3G2+ G3G’2G’1
B3= G3G2G’1
B4= G3G’2+ G3G1
156
Gray to BCD Converter
Logic diagram
157
BCD to Gray Converter
The truth table and k-map for gray to BCD converter can be written as,
K-Map simplification
158
Logic diagram
159
16.Assessment Schedule (Proposed Date & Actual Date)
Assessment Proposed Date Actual Date
First Internal Assessment 17 / 10 / 2024 to

22 /10/ 2024
Second Internal Assessment 23/11/2024 to
28/11/2024
Model Examination 16 /12/ 2024 to
23 /12/ 2024
17.Prescribed Text Books & References
TEXT BOOK:
1. M. Morris Mano and Michael D. Ciletti, Digital Design, With an Introduction to the
Verilog HDL, VHDL, and System Verilog, 6th Edition, Pearson, 2018.
2. S.Salivahanan and S.Arivazhagan,Digital Circuits and Design, 5th Edition, Oxford
University Press, 2018.
REFERENCES:
1. A.Anandkumar, Fundamental of digital circuits, 4th Edition, PHI Publication,2016.
2. William Kleitz, Digital Electronics-A Practical approach to VHDL, Prentice Hall
International Inc, 2012.
3. Charles H.Roth, Jr. andLarry L. Kinney, Fundamentals of Logic Design, 7th Edition,
Thomson Learning, 2014.
4.Thomas L. Floyd, Digital Fundamentals, 11th Edition, Pearson Education Inc, 2017.
5. John.M Yarbrough, Digital Logic: Applications and Design, 1st Edition, Cengage
India, 2006.
NPTEL LINK: https://nptel.ac.in/courses/108/105/108105132/

MINI-PROJECTS SUGGESTIONS
Smart Digital School Bell With Timetable Display

The system makes use of a STM32 controller along with a Bluetooth module, school
bell buzzer, LED display 16 x 32 inch along with buttons, basic electronics
components and PCB board in order to develop this system. The STM 32 controller
uses the display to interact with user. It has a Settings mode and running mode. In
the setting mode the system allows user to connect an android device. Once
connected we use an app to program the timetable into the system. The android app
allows user to set today's timetable in the system with timings.
Industrial Production Target Counter Display System

Industries have a variety of production lines that operate day and night, developing
different products. The production lines always work on their targets, production
targets are to be completed on time for lines to keep functioning efficiently. But the
first step towards completing production targets is the ability to be able to keep a
count of the production status and display it along with the current target. This helps
managers and workers to know current status and work accordingly to achieve the
target.
Stop and Go Queue Entry Manager System

We usually end up waiting in queues at various places, from passport renewals to
shopping malls. Managing queues can be a tough task at places where queues move
slowly like security check queue. A separate person needs to be deployed to ask a
person to go and the net person to stop and wait his/her turn.
Well we here automate this task by developing a system that automates this task
using Led display and electronics controller circuitry. The system is designed to
automatically handle queues without needing a separate person to ask people next in
line to stop or Go.
The Stop can Go System provides the following advantages:
Automatic Person Detection
LED display for Stopping and Go Indication with Buzzer
Red Color Stop and Green Colored Go Indicator LED
Digital Car Turning and Braking Indicator
building a fancy Car/Bike Turning Indicator Circuit using 555 Timer IC, with four LEDs
glowing one by one in a particular pattern and we can control the speed or frequency
of this LED indicator by simply turning a Potentiometer.
Walking Stick with Heart Attack Detection

The purpose of this project is to indicate heartbeat condition and it is
designed especially for senior citizens who are prone to suffer from heart-related
problems. This project consists of a microcontroller, an ECG circuitry, and a Bluetooth
module.
The ECG circuitry captures a heartbeat signal from the patient by using sensors and
then sends that signals to a microcontroller. Next, the microcontroller compares the
heartbeat with the normal rate, and if finds above the threshold levels, it will
immediately warn the people around with a buzzing sound. The Bluetooth module
helps in a medical emergency at the time of the heart attack.
Digital Soil Moisture Tester

The digital soil moisture tester is used to monitor the soil condition whether the soil
is wet/dry. This tester is also used to test the wetness or dryness of fabrics made
with cotton, woolen, etc. This tester includes a display with a number of LEDs used
for indication purposes. Once the two test rods are inserted in the soil, then the
display panel will show the magnitude of conductance among the two probes. Based
on the soil resistance, it measures the condition of the soil through the readings of
soil resistance.
Raspberry Pi & Face Recognition based Door Lock

System
In-home security systems, monitoring the people plays an essential role to check
who is coming and leaving the house. We know that the home security system is
mainly designed through password-based but sometimes these can be modified or
stolen easily. To overcome this issue, here is a security system namely door lock
system using face recognition.
This project is mainly used in high-security areas and this system can be powered
with the Raspberry Pi board. This board works with battery power supply & wireless
internet through a USB modem. Whenever any person comes ahead of the door,
then this system identifies the face and compares it with registered data. If the
registered data is matched with that person, the door will open otherwise it
generates an alarm by clicking the photo and sends it to the register person number.
Digital Alarm System

Design a digital alarm system using logic gates and flip-flops. The alarm system
should allow users to set an alarm time and trigger an alarm signal when the current
time matches the set alarm time. Implement features like snooze and reset options.
Elevator Control Simulation

Simulate the control logic of an elevator system using digital logic. Design a circuit
that controls the movement of an elevator between floors, considering factors like
floor requests, door status, and emergency stop. Use LEDs to display the current
floor and direction of movement.
Digital Dice Roller

Create a digital dice roller using combinational logic. When a button is pressed, the
system should generate a random number between 1 and 6 and display it using
LEDs, simulating the roll of a six-sided die.
Traffic Light Simulator

Develop a simulation of a traffic light intersection using digital logic. The system
should control the traffic lights for both directions (NS and EW) and respond to
inputs like pedestrian crossings, ensuring proper traffic flow and safety.
BCD to 7-Segment Decoder

Design a BCD to 7-segment decoder using combinational logic. Create a circuit that
takes a 4-bit binary-coded decimal (BCD) input and displays the corresponding digit
on a 7-segment display.
Digital Combination Lock

Build a digital combination lock system using logic gates and flip-flops. Users
should input a predefined combination using buttons or switches. The lock
should indicate whether the entered combination is correct or not.
Digital Quiz Game

Develop a digital quiz game using logic gates. Create a system that presents
multiple-choice questions to players, allows them to select answers using
buttons, and displays the correct answer after each choice.
Digital Timer
Design a digital timer using counters and logic gates. The timer should have
adjustable preset values and count down to zero, triggering an alert when the
time elapses.
Digital Thermometer
Simulate a digital thermometer using logic gates. Create a system that reads
temperature values from sensors, converts them to binary representation, and
displays the temperature on a 7-segment display.
Digital Combination Generator

Build a digital circuit that generates all possible combinations of a given set of
inputs. For example, if the inputs are A, B, and C, the circuit should produce
outputs like AB, AC, BC, and ABC.
Remember to plan out the design, draw schematics, create truth

tables, and thoroughly test your circuits to ensure they function as
intended.
MINI-PROJECTS IDEAS
1. Multiplexer-Based Projects:
Real-Time Sensor Data Selector:

Use a multiplexer to interface multiple sensors (e.g.,
temperature, humidity, and light sensors) to a single ADC
channel of a microcontroller. The project involves selecting
different sensors in real time and displaying the values on an
LCD or sending them to a PC via UART.
Digital Audio Mixer:
Create a digital audio mixer using a multiplexer to select
between different audio sources (e.g., microphone, music
player) and transmit the selected audio signal to a single
output. This project can include volume control and real-time
switching.
Automated Traffic Light Control System:
Use a multiplexer to control the sequencing of traffic lights at an
intersection. The multiplexer can be used to select different
traffic light configurations based on inputs from sensors or
predefined timing.
Home Security System with Camera Feed Selector:
Implement a system that uses a multiplexer to switch between
multiple camera feeds based on user input or motion sensor
detection. This can be used for real-time monitoring in a home
security system.
MINI-PROJECTS IDEAS
2. Encoder-Based Projects:
Digital Elevator Control System:

Use a priority encoder to implement a simple elevator control system.
The encoder can prioritize floor requests and send control signals to the
elevator motor, indicating which floor to move to next based on user
input.
Wireless Remote Control for Home Appliances:
Design a wireless remote control system using an encoder to transmit
control signals for multiple home appliances (e.g., lights, fans, TV). The
receiver decodes these signals and operates the respective appliances.
Rotary Encoder-Based Volume Controller:
Use a rotary encoder to create a digital volume control for an audio
system. The encoder will increase or decrease the volume digitally and
display the volume level on an LCD screen.
Robot Navigation System:
Implement a robot navigation system using position encoders. The
encoders can monitor the wheel rotation and provide feedback to the
microcontroller for controlling the robot’s movement and trajectory.
3. Decoder-Based Projects:
4-to-16 Line Decoder for Address Selection:

Build a 4-to-16 line decoder to select memory addresses in a
microcontroller-based system. The project can demonstrate how to use a
decoder to extend the addressing range of a microcontroller.
Real-Time Digital Clock:
Implement a digital clock using a 7-segment display decoder. Use the
decoder to drive the segments of multiple 7-segment displays and create
a real-time clock with hours, minutes, and seconds.
Voice-Activated Device Control:
Use a decoder to process voice commands from a microphone
(converted into digital signals) and select specific appliances or devices
to control, such as turning on/off lights or fans.
Binary to Decimal Decoder for Calculator:
Build a simple binary-to-decimal decoder for a basic calculator. The
project can include a keypad to input binary numbers and display the
corresponding decimal value on a 7-segment display.
MINI-PROJECTS IDEAS
4. Demultiplexer-Based Projects:
Remote-Controlled LED Display:

Create a project using a demultiplexer to control multiple LEDs
with a single control input. Use an RF module or infrared
remote to send control signals, and use the demultiplexer to
select which LED to turn on or off.
Real-Time Data Distribution System:
Design a system using a demultiplexer to distribute real-time
data from a single source to multiple displays or storage
devices. This can be used for displaying different sensor
readings or outputs.
Binary Counter with LED Display:
Implement a binary counter using a demultiplexer to drive
LEDs. The demultiplexer will control which LED to turn on based
on the binary count input, creating a visual representation of
the counter.
Multichannel Alarm System:
Design a multichannel alarm system using a demultiplexer to
select which alarm to activate based on different inputs, such as
motion detectors, door sensors, or temperature sensors.
LIST OF LAB EXERCISES
Experiment 2: Design of adders
Experiment 3: Design of subtractors.
Experiment 4: Design of binary adder using IC7483
Experiment 5: Design of Multiplexers & Demultiplexers.
Experiment 6: Design of Encoders and Decoders
Experiment 7: Implementation of a boolean function using a multiplexer.
Thank you
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Department: Science and Humanities

Date: 21st September, 2024

3 Pre Requisites (Course Name with Code) 7

4 Syllabus (With Subject Code, Name, LTPC details) 8

11 Part A Q & A (with K level and CO) 113

12 Part B Qs (with K level and CO) 122

16 Assessment Schedule ( Proposed Date & Actual Date) 160

17 Prescribed Text Books & Reference Books 161

18 Mini Project 162

The Course will enable learners to:

To familiarize the design of various combinational digital circuits using

UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 9

Review of number systems-representation-conversions, Review of Boolean algebra- theorems,

1. Implementation of Boolean expression using logic gates.

UNIT II COMBINATIONAL LOGIC CIRCUITS 9

UNIT III SEQUENTIAL CIRCUITS 9

UNIT IV SYNCHRONOUS SEQUENTIAL CIRCUITS DESIGN 9

Design of clocked sequential circuits - Moore/Mealy models, state minimization, state

UNIT V MEMORY AND PROGRAMMABLE LOGIC DEVICES 9

TOTAL: 45 PERIODS (THEORY) + 30 PERIODS (LAB) = 75 PERIODS

CO4 Analyze synchronous sequential circuits to determine their K3

Knowledge Level Description

Design of Half Adder, 07.10.2024

• Online Logic Circuit Simulator

8. Which combinational circuit is renowned for selecting a single input from

13. Can an encoder be called as multiplexer?

14. One that is not the outcome of magnitude comparator is ____________

19. The observation that a bubbled input OR gate is interchangeable with a

22. The word demultiplex means ___________

23. In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be

25. The binary subtraction of 0 – 0 = ?

1. What does Parity mean?

1 Design of combinational circuits

6 Binary Parallel Adder

7 Carry Look ahead Adder

(i) Combinational circuits

Combinational circuit consists of logic gates whose output at any time is

Block diagram of a combinational logic circuit

For n number of input variables, to a 2𝑛 possible combinational circuit,

Block diagram of a sequential logic circuit

In asynchronous sequential circuits change in input signals can affect memory

Difference Between Combinational and Sequential Circuits

S.No Combinational logic Sequential logic

Any combinational circuit can be designed by the following steps of

• The problem is stated.

• Identify the input and output variables.

• The input and output variables are assigned letter symbols.

• Construction of a truth table to meet input -output requirements.

• Writing Boolean expressions for various output variables in terms

• The simplified Boolean expression is obtained by any method of

• A logic diagram is realized from the simplified Boolean expression

• There should be a minimum number of interconnections.

• Limitation on the driving capability of the gates should not be

• The implementation should have the minimum number of gates,

Block Diagram of Half Adder

K-map simplification for carry and sum

given by the equations,

Sum, S= A’B+ AB’= AÅB

The logic diagram of the half adder is,