MOS Capacitor (MOSCAP)

Quantitative Analysis
How is the gate voltage VG distributed throughout the structure?

From before, we said,

But, Gauss's Law states that the electric displacement must be continuous in
the direction normal to the interface.

where Ks and Kox are the relative dielectric constants in the semiconductor
and the oxide

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 MOS Capacitor (MOSCAP)
Quantitative Analysis

It relates the applied gate voltage to the surface potential!

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 MOS Capacitor (MOSCAP)
Quantitative Analysis
But what about in inversion and accumulation?

For inversion and accumulation we can not invoke the depletion

approximation due to a significant amount of charge near the interface due to
sources other than just ionized dopants (these charges are the electrons and
holes).

In inversion and accumulation, the vast majority of the gate voltage is

dropped across the oxide

In inversion, the depletion width remains ~ constant

Thus, φS can not be much less (greater) than 0 for p-type (n-type)

Thus, φS can not be much greater (less) than 2φF for p-type (n-type)

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 MOS Capacitor (MOSCAP)
With our expression relating the Gate voltage to the surface potential and the fact
that φS=2φF we can determine the value of the threshold voltage of Ideal MOS

Where we have made use of the use of the expression,

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 MOS Capacitor (MOSCAP)

𝑸𝒅
In other way: 𝑽𝑻 = − + 𝟐𝝋𝑭
𝑪𝒐𝒙
(+) n-channel (+) n-channel
(-) p-channel (-) p-channel

Max Depletion width

Depletion Charge

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 Effects of Real Surfaces of MOSCAP

 What are the effects of real surfaces on the MOS

capacitor?

 How does the threshold voltage change when real surfaces

are considered?

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 Effects of Real Surfaces of MOSCAP

During the last lecture, we discussed the ideal MOS capacitor…

The n-type surface that forms as a result of the applied electric field is
the key to transistor operation!

Define a potential qφS which

determines how much band bending
there is at the surface.
• When qφS = 0 we are in flat band
condition.
• When qφS < 0 we have hole
accumulation at the surface.
• When qφS > 0 we have electron
accumulation at the surface.
• When qφS > qφF we have inversion at
the surface.
• Surface should be as strongly n-
type as the body is p-type.

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 Effects of Real Surfaces of MOSCAP

Real surfaces have work function differences…(Note that in Ideal Situation

ФM = ФS which was considered so far)

 Work function differences (ms) can

significantly affect threshold voltage, VT
and other properties.

 The difference is always negative and is

most negative for heavily p-type Si.

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 Effects of Real Surfaces of MOSCAP

The previous band diagram is not at

equilibrium (as revealed by mismatch of At equilibrium and Applied Gate voltage = 0
Fermi filling levels).
So, inevitably, mobile charges will shift
around until Fermi levels are evened out
= equilibrium:

 The negative work function difference

causes the bands to be pulled down further
in equilibrium.
 Holes in semiconductor move AWAY from
surface leaving negative acceptor ions
exposed in a "depletion layer" charge
bending bands

 To achieve flat-band conditions, we must apply a positive voltage to

overcome the inherent bending in the bands
 Clearly, this behavior will lead to shifts in the threshold voltage.

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 Effects of Real Surfaces of MOSCAP

Flat-Band conditions:

V=VFB =ФMS
VFB is the flat band voltage i.e voltage to flatten bands and ФMS is the work
function difference

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 Effects of Real Surfaces of MOSCAP
Ideal oxide = One containing no charge
Real oxide = Amorphous (disordered / non-crystalline)
Best real oxide = SiO2 grown by heating Si in oxygen

Different type of oxide charges:

• Interface traps of density Dit and
trapped charges Qit, located at the Si-
SiO2 interface with energy states within
the silicon forbidden gap
– Bias dependent (occupancy and
Fermi level)
• Fixed oxide charges Qf, located at or
near the surface, immobile under an
applied electric field
• Oxide trapped charges, Qot, created by
X-ray radiation or hot electron injection
• Mobile ionic charges, Qm, sodium ions
are mobile within the oxide under bias
temperature stress conditions
What about the effects of trapped oxide charges?
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 Effects of Real Surfaces of MOSCAP

 Alkali metals can easily be incorporated in the oxide during the fabrication
process.
 These metals induce positive charges in the oxides which induce negative
charges in the metal.
 Positive charges arise from interface states at the Si-SiO2 interface.
 When oxidation is stopped, some ionic silicon is left near the surface.
 These ions along with other uncoupled bonds forms a sheet of positive
charge at the interface.

(NEW!) negative charge induced on

metal gate = changes VT

Qox

Qox

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 Effects of Real Surfaces of MOSCAP

Re-evaluating flat band condition

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 Effects of Real Surfaces of MOSCAP
Based on our knowledge of real surfaces, we must rethink the threshold
voltage…

The threshold voltage becomes

Thus, the threshold voltage must be strong enough to achieve flat-band,

accommodate the charge in the depletion region, and induce the inverted
region

Max Depletion width

Depletion Charge

𝑸𝒐𝒙 𝑸𝒅
𝑽𝑻 = 𝝋𝑴𝑺 − − + 𝟐𝝋𝑭
𝑪𝒐𝒙 𝑪𝒐𝒙
(-) (-) (+) n-channel (+) n-channel
(-) p-channel (-) p-channel

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 MOS Capacitor (MOSCAP)
What about the capacitance of MOS Structure (MOS C-V Curves)?

The capacitance depends on the voltage…

MOS Capacitor is the

series combination of
the oxide and the
voltage dependent
semiconductor
capacitances.

In accumulation:
 The capacitance is
huge.
 Structure acts like a
parallel plate
capacitor piling holes
up at the surface.

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 MOS C-V Curves
Start increasing the voltage across the capacitor…
In depletion:
 Capacitance decreases
as depletion width W
grows until inversion is
reached.
 Charge in depletion layer
of MOS capacitor
increases as ~ (φS)^1/2 so
depletion capacitance
decreases as the
inverse.
 The surface becomes
depleted and the
depletion layer
capacitance needs to be
added in…

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 MOS C-V Curves
In the start of inversion:
On the semiconductor
side of our AC capacitor,
now have TWO variable
charges:
i) Newly forming inversion
layer of electrons at
semiconductor surface
ii) Layer of negatively
charged acceptor ions
covered / uncovered as
holes pushed back and
forth

WHICH CHARGES ARE MOST

IMPORTANT IN DETERMINING AC
CAPACITANCE?
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 MOS C-V Curves
Strong Inversion
High Frequency Case:
Low frequency
 If signal applied to make
measurement is too fast,
inversion layer carriers
can’t respond and do
not contribute. High frequency

 In that case, measured

capacitance is
determined only by
modulation of depletion
layer charge

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 MOS C-V Curves
Strong Inversion

Low Frequency Case:

Low frequency
 If signal applied to make
measurement is slow,
inversion layer carriers
respond and dominate.
High frequency
 In that case, measured
capacitance is
determined only by
modulation of Inversion
layer charge

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 MOS C-V Curves Analysis
Can’t we get more information from the
capacitance-voltage data?
We can get a lot of information from the Cox
capacitance-voltage (C-V) data.

• Insulator thickness
• Substrate doping
• Threshold voltage

By using the capacitance in

accumulation or strong inversion at
low frequency will give us the
insulator thickness.

The capacitance Cmin is the series combination of the capacitance Cox and the
minimum depletion capacitance Cd,min = εs/Wm.
This will give us the maximum depletion width

It’s solution gives NA in terms of Cd,min.

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 MOS C-V Curves Analysis

Once we know the substrate

doping, we can find the
flatband capacitance…

The flatband capacitance is

determined from the Debye
length capacitance…

The Debye length depends on the

doping…

The overall MOS FB capacitance CFB is the series combination of Cdebye and
Cox.
From these values, we can determine VFB the corresponds to CFB.

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 MOS C-V Curves Analysis

VT does not correspond exactly

to Cd,min

Because change of charge in

semiconductor is the sum of
the change in the depletion
charge and the mobile
inversion charge which are
equal at onset of strong
inversion.

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 MOS C-V Curves Analysis

We can gain further information about the

interface states…
 Fast interface state densities
– Defect states can change charge states
rapidly.
– Changes in the surface potential can move the
Fermi energy above or below states in the
bandgap and change their occupancy .
Interface States
These fast interface states give rise to
capacitance in parallel with the depletion
capacitance both of which are in series with the
insulator/oxide capacitance.
• Fast interface states:
– Can follow 1 – 1 kHz changes in gate bias but
not high frequency (> 1 MHz).
– They contribute to the low frequency capacitance
but not the high frequency.
– The differences between these two capacitances
gives the interface state densities as a function of
energy.

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 MOS C-V Curves Analysis
What about mobile ion
Charges (Qm)?
 Fixed oxide charges do
not change charge state.
– Effects on VFB and VT depend on
location relative to interface.

• Mobile ions can change

charge state.

• Heat MOS device to ~ 200 – 300 C

• Apply positive gate voltage (~1 MV/cm in oxide layer)
• Mobile positive ions are repelled to the SiO2-Si interface.
• Make room temperature C-V measurement to determine VFB.
• Switch the bias configuration to negative.
• Now ions drift towards the gate electrode.
• They are now too far away to affect band bending but induce
equal and opposite charge on the gate electrode.
• Make another C-V measurement of VFB.
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 MOS Transistor (MOSFET)
Qualitative Analysis

Flow of current from “Source” to “Drain” is controlled by the “Gate”

voltage.

Control by the Gate voltage is achieved by modulating the conductivity

of the semiconductor region just below the gate. This region is known
as the channel

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 MOS Transistor (MOSFET)
Qualitative Analysis

G=Gate, D=Drain, S=Source, B=Body (substrate, but to avoid

confusion with substrate, B is used)

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 MOS Transistor (MOSFET)
Qualitative Analysis
Assume an n-channel (receives it’s name from the “type” of channel
present when current is flowing) device with its source and substrate
grounded (i. e., VS=VB=0 V).

For any value of VDS:

• When VGS <0 (accumulation), the source to drain path consists of two
back to back diodes. One of these diodes is always reverse biased
regardless of the drain voltage polarity.

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 MOS Transistor (MOSFET)
Qualitative Analysis

For any value of VDS:

When VGS <VT (depletion), there is a deficit of electrons and holes making
the channel very highly resistive. => No Drain current can flow.

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 MOS Transistor (MOSFET)
Qualitative Analysis

Consider now the Inversion case:

First, VDS = 0:

•When VGS > VT , an induced n-type region, an “inversion layer”, forms in the
channel and “electrically connects” the source and drain.

(n-type)

p-type

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 MOS Transistor (MOSFET)
Qualitative Analysis

Inversion case, VGS > VT (continued):

When VDS >0 , the induced n- type region allows current to flow between
the source and drain. The induced channel act like a simple resistor. Thus,
this current, ID, depends linearly on the Drain voltage VD. This mode of
operation is called the linear or “triode”* region.

Inversion layer (n-type)

p-type

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 MOS Transistor (MOSFET)
Qualitative Analysis
Inversion case, VGS > VT (continued):

Drain current verses drain voltage when in the linear or “triode” region.

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 MOS Transistor (MOSFET)
Qualitative Analysis
Inversion case, VGS > VT (continued):

When VDS increases a few tenths of a volt (>0):

 The depletion region near the drain widens (N+ drain is positively biased
i.e. reverse biased with respect to the substrate).
 The electron concentration in the inversion layer near the drain
decreases as they are “sucked out” by the Drain voltage.
 Channel conductance decreases resulting in a drop in the slope of the
ID-VD curve.
Reduced electron concentration in
the Inversion layer near the drain
Inversion layer (n-type)

p-type

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 MOS Transistor (MOSFET)
Qualitative Analysis
Inversion case, VGS > VT (continued):
Drain current verses drain voltage for increasing VDS (still in the “linear”
or triode region).

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 MOS Transistor (MOSFET)
Qualitative Analysis
Inversion case, VGS > VT (continued):

The inversion layer eventually vanishes near the drain end of the channel.
This is called “Pinch-Off” and results in a flat ID-VDS curve

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 MOS Transistor (MOSFET)
Qualitative Analysis
Inversion case, VGS > VT (continued):

ID-VDS curve for the “Saturation Region”

The drain-source voltage, VDS, at which this occurs is called the saturation
voltage, Vsat while the current is called the saturation current, IDsat.

IDsat

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 MOS Transistor (MOSFET)
Qualitative Analysis
Inversion case, VGS > VT (continued):
• For VDS>Vsat the channel length, L, effectively changes by a value ΔL.
• The region of the channel, ΔL is depleted and thus, is high resistivity.
• Accordingly, almost all voltage increases in VDS>Vsat are “dropped across”
this portion of the channel.

High electric fields in this region act similarly to the

collector-base junction in a BJT in active mode,
“stripping” or “collecting” carriers from the channel.

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 MOS Transistor (MOSFET)
Qualitative Analysis
Inversion case, VGS > VT (continued):

 If ΔL<<L, the voltage at the end of the channel will be constant (Vsat ) for all
VDS>Vsat. ID will be constant.

 If ΔL~L, the voltage dropped across the channel (VSAT) varies greatly with
VDS due to large modulations in the electric field across the pinched off
region (E=[VDS - VSAT]/[ΔL]). In this case, ID increases slightly with VDS.

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 MOS Transistor (MOSFET)
Qualitative Analysis

Finally, ID-VDS curves for various VGS

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 MOS Transistor (MOSFET)
I-V Analysis

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 MOS Transistor (MOSFET)
I-V Analysis
Concept of Effective mobility
The mobility of carriers near the interface is
significantly lower than carriers in the
semiconductor bulk due to interface
scattering.
Since the electron concentration also varies
with position, the average mobility of
electrons in the channel, known as the
effective mobility, can be calculated by a
weighted average,

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 MOS Transistor (MOSFET)
I-V Analysis

Drain Current-Voltage Relationship

In the Linear Region, VGS>VT and 0<VDS<Vdsat

Neglecting the diffusion current, and recognizing the current is only in the y-
direction

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 MOS Transistor (MOSFET)
I-V Analysis

To find ID, we need an expression relating φ and QN

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 MOS Transistor (MOSFET)
I-V Analysis
“Capacitor-Like” Model for QN
Assumptions:
 Neglect all but the mobile inversion charge
 For the MOSFET, the charge in the semiconductor is a linear function of
position along the semiconductor side of the plate. Thus, φ varies from 0 to VDS.

Neglect the depletion region charge

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 MOS Transistor (MOSFET)
I-V Analysis
Using “Capacitor-Like” Model for QN we can estimate ID as:

This is known as the “square law” describing the Current-Voltage characteristics in

the “Linear” or “Triode” region.

Note the linear behavior for small VDS (can neglect VDS term).
Note the negative parabolic dependence for larger VDS but still VDS<Vdsat (can NOT
neglect VDS^2 term).

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 MOS Transistor (MOSFET)
I-V Analysis
“Capacitor-Like” Model for QN:
But what about the saturation region?
For VDS>Vdsat the voltage drop across our channel is VDsat with the remaining voltage
(VDS-VDsat) dropped across the pinch-off region

But the charge at the end of the channel is zero due to the pinched off channel

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 MOS Transistor (MOSFET)
I-V Analysis (Output Chracteristics)

Summary of Drain Current-Drain Voltage Characteristic

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 MOS Transistor (MOSFET)

I-V Analysis (Transconductance)

Transconductance

GS
GS

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 MOS Transistor (MOSFET)

I-V Analysis (Transconductance)

Let’s examine the

transconductance…

• We differentiate with
respect to the gate bias.
• Transconductance is zero
below VT due to small
current flowing through
device.
• Goes through maximum
and then decreases due to
channel degradation of
mobility and additional
source/ drain series
resistances.

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 MOS Transistor (MOSFET)

I-V Analysis (Transfer Characteristics)

Here we plot the drain voltage

versus the gate voltage transfer
characteristic…

• The linear region ID versus VG

should be straight.

• Intercept on the VG axis gives

the threshold voltage.

• The slope of this plot divided

by VD gives the conductance of
the channel.

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 MOS Transistor: Deviations From Ideal

Channel Length Modulation Effect

Above “pinch-off” (when VDS >

VDsat=VGS-VT) the channel length
reduces by a value ΔL.

Thus, the expression for drain current,

becomes

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 MOS Transistor: Deviations From Ideal

Channel Length Modulation Effect

But the fraction of the channel that is
pinched off depends linearly on VDS
because the voltage across the pinch-off
region is (VDS-VDsat) so,

where λ is known as the Channel-Length

Modulation parameter and is typically:
0.001 V^-1 < λ <0.1 V^-1

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 Body Effect
 The source and bulk/body will not be at zero volts all of the time
 The p-type bulk will be connected to the lowest supply voltage for an IC
 Discrete MOSFETs may have bulk tied directly to the source

But for ICs we can assume that there can be a positive VSB for NMOSFETs

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 Body Effect

 Increase in threshold voltage (Vt ) with VSB is called the body effect
• Modeled as a change in the threshold voltage as a function of VSB
• The source is, by definition for NMOSFET, at a lower positive potential than the
drain, which is why we use it as our reference voltage

Key Point: Transistors with source NOT at ground are harder to turn on.

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ECC 302, ECE Department, NIT
 Small signal circuit models of the MOS transistor

NMOS

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 NMOS: A Graphical Solution

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 Small Signal Model with Capacitances

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