8051 Interrupt Timers
8051 Interrupt Timers
Dr. P. T. Karule
Professor
Department of Electronics Engineering
Yeshwantrao Chavan College of Engineering, Nagpur (M. S.)
Email: [email protected]
Website: www.ycce.edu
8051 Microcontroller
Interrupts
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Interrupt sources of 8051
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Interrupt Vector Table
Vector Location
Interrupt sources Priority
Addresses
TI or RI 0023H 5th
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Interrupt Circuit
TCON
0
IT0 IE0
INT0
1
OR
TF0
0 Interrupt
IT1 IE1 Sources
INT1
1
TF1
TI
RI
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Interrupt Control Registers
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Interrupt Enable Register (IE)
IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0
ET1 Enable or disable timer1 overflow interrupt. If ET1 = 0, disable. If ET1 = 1, enable.
ET0 Enable or disable timer0 overflow interrupt. If ET0 = 0, disable. If ET0 = 1, enable.
MOV IE, #10000100B ; Enable external interrupt 1 (bit EA=1and bit EX1=1)
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Interrupt Priority Register (IP)
IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0
MOV IE, #10001100B ; Enable external interrupt 1 (bit EA=1, bit EX1=1 & ET1=1)
SETB PT1 ; Timer 1 interrupt has high priority
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TCON
TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0
Timer Interrupt
External Interrupt 1 edge flag. Set by hardware when External Interrupt edge is
IE1
detected. Cleared by hardware when interrupt is processed.
Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level
IT1
triggered External Interrupt.
External Interrupt 0 edge flag. Set by hardware when External Interrupt edge is
IE0
detected. Cleared by hardware when interrupt is processed.
Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level
IT0
triggered External Interrupt.
e.g. Write instructions to set interrupt type for external interrupt 1 as falling edge triggered
& enable the interrupt
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Example
Write program to generate the pulse of width T on P1.5?
Use external interrupt 0 to apply trigger. i.e. to start the pulse.
5V
5V
P3.2 T
(INT0)
P1.5
8051
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Example (Cont..)
Program
$MOD51
ORG 0000H
SJMP START
ORG 0003H
AJMP INT_EX0
START: MOV SP, #40H ; initialise stack pointer
CLR IT0 ; IT0=0, Low level trigger
MOV IE, #10000001B ; EA =1 & EX0 =1, enable INT0
CLR P1.5 ; P1.5 = 0
L1: SJMP L1
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Timer/Counter
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Timers & Counters
Features of Timer Register
Timer Byte
Registers Address
THO TLO 16 bit Timer 0 register
TL0 8AH
TL1 8BH
TH1 TL1 16 bit Timer 1 register
TH0 8CH
TH1 8DH
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Timer / Counter
Timer (C/T = 0)
Internal clock is used to increment the timer register, timer is
incremented after every 12 CLK cycles of internal clock (i.e. One
m/c cycle)
Counter (C/T =1)
External clock is used to increment the timer register, the register
is incremented on a negative edge on input pins T0 / T1.
CLK /12
TMO
D
C/T 8051
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Timer/Counter operation
Timer 0 Registers of 8051
TF0
0
1
TH0 TL0 FFFFH
FF
94
00 FF
50
00 FFFEH
FFFDH
---
---
9452H
Initialize timer 0 with N = 9450H 9451H
9450H
MOV TL0, #50H ---
---
MOV TH0, #94H ---
0004H
0003H
0002H
0001H
0000H
Timer #Value
Range
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Timer/Counter control circuit
TF0
TH0 TL0
CLK
XX XX 0
Timer ON / OFF
TR0
GATE
INT0 8051
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Timer Control Registers
The operation of timer/counter is determined and controlled by
two registers.
SFR Addr Bit addr
– TMOD
TCON 88H 88H to 8FH
– TCON
TMOD 89H --
TMOD is used to select
Timer / Counter (i.e CLK internal / external) (C/T)
Mode of operation of timer (M1M0)
• Mode 0 – 13 bit timer
• Mode 1 - 16 bit timer
• Mode 2 - 8 bit timer
• Mode 3 - Two 8 bit & one 16 bit ( 3 timers)
Timer / Counter control (ON / OFF) (GATE)
• Hardware control
• Software control
TCON is used to select
Timer / counter run ON /OFF (TR)
• Main control for ON / OFF
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TMOD Register
Timer 1 Timer 0
M1 M0 Operating Mode
0 0 Mode 0, 13 bit timer/counter
0 1 Mode 1, 16 bit timer/counter
1 0 Mode 2, 8 bit auto-reload timer/counter
Mode 3, Timer 0 is used as two separate 8 bit timers /counters.
1 1 TL0 is an 8 bit timer/counter controlled by timer 0 control bits.
TH0 is an 8 bit timer/counter controlled by timer 1 control bits.
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TCON
TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0
Timer Interrupt
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TCON
TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0
Timer Interrupt
External Interrupt 1 edge flag. Set by hardware when External Interrupt edge is
IE1
detected. Cleared by hardware when interrupt is processed.
Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level
IT1
triggered External Interrupt.
External Interrupt 0 edge flag. Set by hardware when External Interrupt edge is
IE0
detected. Cleared by hardware when interrupt is processed.
Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level
IT0
triggered External Interrupt.
e.g. Write instructions to set interrupt type for external interrupt 1 as falling edge triggered
& enable the interrupt
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Interrupt Enable Register (IE)
IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0
ET1 Enable or disable timer1 overflow interrupt. If ET1 = 0, disable. If ET1 = 1, enable.
ET0 Enable or disable timer0 overflow interrupt. If ET0 = 0, disable. If ET0 = 1, enable.
MOV IE, #10000100B ; Enable external interrupt 1 (bit EA=1and bit EX1=1)
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Timer - Mode 0 Operation
TF1
TH1 TL1
(8 bit) (5 bit) 0
1
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Programming
Program
$MOD 51
SETB P1.7 ; Set P1.7
MOV TH0, #00H
MOV TL0, #00H ; N = 0000H
MOV TMOD,#00H ; GATE = 0, C/T = 0, M1M0 = 00
SETB TR0 ; TR0 =1
WAIT: JNB TF0, WAIT ; Wait till TF0 =1 (N = 1FFFH)
CLR P1.7 ; Clear P1.7 after overflow
L1: SJMP L1
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Using interrupt
Write program to run Timer 0 as Timer in mode 0 with N = 0000H
& Clear bit P1.7 after interrupt on overflow.
Main Program
$MOD 51
ORG 0000H
SJMP START
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Timer Mode 1
• Timer is used as a 16 bit timer / counter
• After an overflow of 16bits (from 1 to 0), Interrupt flag TFx is
set.
TF1
TH1 TL1
(8 bit) (8 bit) 0
1
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Timer Mode 2 (Reload)
• Timer is used as a 8 bit timer / counter .
• TLx is used as 8 bit counter and THx is used to hold reload
value
TF1
TL1
(8 bit) 0
TH1
(8 bit)
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Timer Mode 3
• Timer 0 is split into two 8 bit timers TL0 & TH1
• TL0 is controlled by timer 0 control bits
• TH0 is controlled by timer 1 control bits
TL0
TF0
(8 bit)
TH0
TF1
(8 bit)
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CLK input for Timer
• Find the timer’s clock frequency and its period for various 8051-based
system, with the crystal frequency 11.0592 MHz when C/T bit of TMOD is 0.
12
XTAL
CLK to Timer
OSC
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Time Delay
To generate a time delay
1. Load the TMOD value register indicating which timer (timer 0 or
timer 1) is to be used and which timer mode (0 or 1) is selected
2. Load registers TL and TH with initial count value
3. Start the timer
4. Keep monitoring the timer flag (TF) with the JNB TFx,target
instruction to see if it is raised
5. Get out of the loop when TF becomes high
6. Stop the timer
7. Clear the TF flag for the next round
8. Go back to Step 2 to load TH and TL again
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Ex 1
• Generate a square wave of 50% duty cycle (with equal portions high
and low) on the P1.5 bit. Timer 0 is to be used to generate the time
delay. Analyze the program
P1.5
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Ex 1…
In the above program the steps.
• TMOD is loaded.
• FFF2H is loaded into TH0-TL0.
• P1.5 is toggled for the high and low portions of the pulse.
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Ex 2
• Write assembly language program to generate delay of 25 msec using
Timer 0 in mode 1.
N = 65535 – 25000 = 40535 = 9657H
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8051 Microcontroller