Computer Systems [2024-25]

Topics 2 & 3: CPU, Memory, Program Execution

& MIPS Assembly – Exercise Sheet [Solutions]
Q#1: Considering the simpler view of instructions, write the machine instructions representing each of
the codes below:

Memory locations/addresses:
num1 = > 4040
num2 = > 5050
Total => 6060
ADD 6060, 4040, 5050
a. int num1= 5;
int num2 = 14;
int total = num1 + num2;

b. int num1 = 50; SUB 6060, 5050, 4040

int num2 = 14;
int total = num2 – num1;

Q#2: Consider the below state of memory, where some values are already stored in different locations:

Value 50 70 14 9 7 44 20
Memory Address 2024 2028 2032 2036 2040 2044 2048 2052

What would be the result of executing the following instructions?

(a) ADD 2028, 2024, 2048 [94, Stored in 2028]
(b) ADD 2036, 2024, 2036 [64, Stored in 2036 and overwrites the 14]
(c) MUL 2028, 2044, 2052 [140, Stored in 2028 and overwrites the 94]
(d) SUB 2040, 2048, 2044 [37, Stored in 2040 and overwrites the 9]
(e) XOR 2052, 2040, 2044 [34, Stored in 2052]

The final memory state will look like:

Value 50 140 70 64 37 7 44 34
Memory Address 2024 2028 2032 2036 2040 2044 2048 2052

What would change if these instructions were to be executed in the following sequence?
(a) XOR 2052, 2040, 2044 [14, Stored in 2052]
(b) ADD 2036, 2024, 2036 [64, Stored in 2036 and overwrites the 14]
(c) ADD 2028, 2024, 2048 [94, Stored in 2028]
(d) SUB 2040, 2048, 2044 [37, Stored in 2040 and overwrites the 9]
(e) MUL 2028, 2044, 2052 [98, Stored in 2028 and overwrites the 94]

When the instructions are executed in a different order, the resultant memory state will be different:
Value 50 98 70 64 37 7 44 14
Memory Address 2024 2028 2032 2036 2040 2044 2048 2052

Q#3: Using the figure below, describe the entire fetch / execute cycle detailing the result of each step in
the cycle for the following machine instruction: ADD 343, 546, 772

PC: 600

Instruction Fitch (IF):

 Execution begins by moving the instruction at the address given by the PC (600) from memory
to the control unit.
 Bits of instruction are placed into the decoder circuit of the Control Unit.
 Once instruction is fetched, the PC can be readied for fetching the next instruction.

Instruction Decode (ID):

 Decoder determines what operation the ALU will perform (ADD), and sets up the ALU.
 Decoder finds the memory addresses of the instruction's data (546, 772).
 Decoder finds the destination address for the Result Return step and places the address in the
RR circuit (343)

Data / Operand Fetch (DF/OF):

 The data values to be operated on are retrieved from memory (40, 23).
 Bits at specified memory locations are copied into locations in the ALU circuitry.
 Data values remain unchanged in the memory.

Instruction Execution (EX):

 The addition circuit adds the two source operands (40, 23) together to produce their sum (63).
 Sum (63) is held in the ALU circuitry (accumulator).

Result Return / Store (RR/ST):

 RR returns the result of EX (63) to the memory location specified by the destination address
(343).
Q#4: A processor is operating at 32MHz. Each instruction takes a minimum of 6 cycles to
execute. The processor has a six-stage pipeline. If a program starts execution at time 0, what is the
theoretical maximum number of instructions that will have completed their execution at the end of 1
millisecond?

Speed = 32MHz = 32,000,000 cycles/second = 32,000 cycles / millisecond

With pipelining:
Number of clock cycles taken by the first instruction = 6 cycles.
After the first instruction has completely executed, one instruction comes out per cycle.
So, number of cycles taken by each remaining instruction = 1 cycle.
Number of executed instructions
= First Instruction (1) + remaining instructions (32,000 cycles/ms – 6 cycles)
= 1 + 31,994 = 31,995 instruction/ms

In practice, there are factors that mean that this theoretical maximum is never reached.

Q#5: What is the value stored in ‘z’ after the execution of the following MIPS assembly code, if x=5?

li $t0, 1
li $t1, 2
lw $t2, &x
L1: bgt $t1, $t2, L2
mul $t0, $t0, $t1
addi $t1, $t1, 1
j L1
L2: sw $t0, &z

The bgt (branch on greater than) instruction compares two registers and jumps to L2 if the content of
register $t1 is greater than the content of register $t2. The equivalent Java code is a for loop:

z = 1;
for (i = 2; i <= x; i++){
z = z * i;
}

Knowing that x = 5 and the index i starts from 2, the result will be:
z = 1 * 2 * 3 * 4 * 5 = 120.

Q#6: Write MIPS assembly code for the following expression.

C = 12 * A + 4 * (B – 5)
Ensure that the assembly code respects the order of evaluation in the above expression.
Assuming, A = 10, and B = 9, show that your assembly code computes the correct answer.
Let’s break the above expression into statements so that each one performs only one operation.
t0 = 12 * A
t1 = B – 5
t2 = 4 * t1
C = t0 + t2
Now we can assign registers, and write the code in MIPS assembly language.
# MIPS Assembly Code -- Execution Results
lw $s0, &A -- [$s0 = 10]
lw $s1, &B -- [$s1 = 9]
mul $t0, $s0, 12 -- [$t0 = 120]
sub $t1, $s1, 5 -- [$t1 = 4]
mul $t2, $t1, 4 -- [$t2 = 16]
add $s2, $t0, $t2 -- [$s2 = 136]
sw $s2, &C -- [C = 136]
We can see that one line of high-level translates to many lines of low-level assembly code!

Q#7: Given the MIPS Instruction set, convert the following MIPS assembly code into
Java/Python-like code. Consider the register assignment proposed at the start of the code.
You may like to refer to the MIPS Instructions cheatsheet available at:
https://jarrettbillingsley.github.io/teaching/classes/cs0447/guides/
instructions.html

MIPS Assembly Code

# $t1 = i
# $t2 = tmp
# $t3 = sum

and $t1, $t1, $0

and $t2, $t2, $0
and $t3, $t3, $0
label:
bgt $t1, 14, exit
mul $t2, $t1, 2
add $t3, $t3, $t2
addi $t1, $t1, 1
j label
exit:
Once we map the variables to registers and dry run the above code, we can easily see that it
behaves like a for loop that starts from 0 and iterates until the value becomes 15 (or greater).
Within the loop, it computes a running sum, which takes the value of iterator i, and doubles its
value before adding it to the previous value of sum variable.
tmp = 0;
sum = 0;
for (int i = 0; i < 15; i++){
tmp = i * 2;
sum = sum + tmp;
}

OR (in a more concise form)

sum = 0;
for (int i = 0; i < 15; i++){
sum = sum + i * 2;
}

Q#8: Consider the following MIPS assembly instructions:

(a) divu $s7, $s4, $s5
(b) srlv $t3, $t9, $t7
(c) sra $t2, $t4, 5
(d) lw $t5, 0x10($t4)
State the type of each instruction, find Field Values and Machine Code for each one of them.
You may like to refer to the MIPS cheatsheet and instructions reference available at the links below:
https://jarrettbillingsley.github.io/teaching/classes/cs0447/guides/
instructions.html
http://alumni.cs.ucr.edu/~vladimir/cs161/mips.html

(a) divu $s7, $s4, $s5

This is an R-Type instruction. Field Values are given below:
Opcode Source 1 Source 2 Dest Shift Func
0 20 21 23 0 27
Machine Code is given below:
Opcode Source 1 Source 2 Dest Shift Func
000000 10100 10101 10111 00000 11011
(b) srlv $t3, $t9, $t7
This is an R-Type instruction. Field Values are given below:
Opcode Source 1 Source 2 Dest Shift Func
0 25 15 11 0 6
Machine Code is given below:
Opcode Source 1 Source 2 Dest Shift Func
000000 11001 01111 01011 00000 000110

(c) sra $t2, $t4, 5

This is an I-Type instruction. Field Values are given below:
Opcode Source 1 Dest Value
3 12 10 5
Machine Code is given below:
Opcode Source 1 Dest Value
000011 01100 01010 0000 0000 0000 0101

(d) lw $t5, 0x10($t4)

This is an I-Type instruction. Field Values are given below:
Opcode Source 1 Dest Value
35 12 13 16
Machine Code is given below:
Opcode Source 1 Dest Value
100011 01100 01101 0000 0000 0001 0000