Microprocessor Interfacing &

Programming
EL-3002
LABORATORY MANUAL
Fall 2024

LAB 01
Verification of ALU Operations and
Implementation of a Basic Memory Model Using
Flip-flops on Proteus

Muhammad Sarmad Fowad 22i-2222

Abdullah Ali 22i-2153 A
STUDENT NAME ROLL NO SEC

______________________________________
LAB ENGINEER SIGNATURE & DATE

MARKS AWARDED: /10

________________________________________________________________
NATIONAL UNIVERSITY OF COMPUTER AND EMERGING SCIENCES (NUCES), ISLAMABAD

Prepared by: Engr. Iqra Akram Version: 2.01

Last Edited by: Engr. Iqra Akram Date: 12 Aug, 2017
Verified by: Dr. Jamshed Iqbal Date: 12 Aug, 2017
 Microprocessor Interfacing & Programming LAB: 01

LAB: 01 ALU Verification and Basic Memory Unit Implementation

Learning Objectives:
a. Brief overview of Proteus.
b. To verify Arithmetic Logic Unit IC (ALU-74HC181) operations
c. How to build a basic model of a memory elements (registers) using flip flops
d. How to read and write from/to registers

Equipment Required:
a. PC
b. Proteus

Introduction:
1. Verification of ALU operations:
 ALU is a digital circuit used to perform arithmetic and logic operations.
 It represents the fundamental building block of the central processing unit (CPU) of
a computer. Modern CPUs contain very powerful and complex ALUs.
 In addition to ALUs, modern CPUs contain a control unit (CU).
 A register is a small amount of storage available as part of a CPU. The control unit
tells the ALU what operation to perform on that data, and the ALU stores the result
in an output register. The control unit moves the data between these registers, the
ALU, and memory.

1.1 ALU working:

 An ALU performs basic arithmetic and logic operations.
 Examples of arithmetic operations are addition, subtraction, multiplication, and
division.
 Examples of logic operations are comparisons of values such as NOT, AND, and
OR.
 All information in a computer is stored and manipulated in the form of binary
numbers, i.e. 0 and 1.
 Transistor switches are used to manipulate binary numbers since there are only two
possible states of a switch: open or closed. An open transistor, through which there
is no current, represents a 0.
 A closed transistor, through which there is a current, represents a 1.

1.2 ALU IC (74HC181):

 The 74HC181 is a 4-bit arithmetic logic unit.

 The 74HC/HCT181 is 4-bit high-speed parallel ALU.
 Controlled by the four function select inputs (S0 to S3).
 Mode control input (M), they can perform all the 16 possible logic operations or 16
different arithmetic operations on active HIGH or active LOW operands.

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 Microprocessor Interfacing & Programming LAB: 01
Mode Select input Active LOW Input and Output
S3 S2 S1 S0 LOGIC(M=H) ARITHMETIC(M=L,Cn=H)
L L L L Ā A
L L L H ?
L L H L ĀB A+
L L H H Logical 0 minus 1
L H L L A plus A
L H L H ? (A + B) plus A
L H H L A minus B minus 1
L H H H A A minus 1
H L L L Ā+B A plus AB
H L L H ?
H L H L ? (A + ) plus AB
H L H H ? AB minus 1
H H L L Logical 1 A plus A(1)
H H L H A+ (A + B) plus A
H H H L A+B (A + ) plus A
H H H H A minus 1 A minus 1

Notes to the functional table:

1. Each bit is shifted to the next more significant position
2. Arithmetic operations expressed in 2s complement

H= High voltage level

L= Low voltage level

Its features include:

 Full carry look-ahead for high-speed arithmetic operation on long words.
 Provides 16 arithmetic operations: add, subtract, and compare, double, plus 12 others.
 Provides all 16 logic operations of two variables: EXCLUSIVE-OR, compare, AND,
NAND, NOR, OR plus 10 other logic operation.
 Output capability: standard, A=B open drain.
 ICC category: MSI

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(a) (b)
74HCT181: (a) pin configuration (b) its proteous view

Pin Names Pin Nos. (Write here)

Select inputs pin Nos.: 3,4,5,6
Control pin No.: 8
Input pin Nos.: 2,23,21,19,1,22,20,18,17
Output pin Nos.: 9,10,11,13
1.3 ALU operation verification block diagram:

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 Microprocessor Interfacing & Programming LAB: 01

Task 1:
Verify all operations of ALU using available IC on Proteus. Display it on seven segment
display.

To evaluate an ALU in Proteus, integrate IC models for simulation and use a seven-segment
display to visually verify the outputs.

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Task 2:
Fill the missing term in the following table.

Mode Select input Active LOW Input and Output

S3 S2 S1 S0 LOGIC(M=H) ARITHMETIC(M=L,Cn=H)
L L L L Ā A

L L L H A+B
L L H L ĀB A+
L L H H Logical 0 minus 1
L H L L A plus A

L H L H B’ (A + B) plus A
L H H L A minus B minus 1
L H H H A A minus 1
H L L L Ā+B A plus AB

H L L H A plus B
H L H L B (A + ) plus AB

H L H H A*B AB minus 1
H H L L Logical 1 A plus A(1)
H H L H A+ (A + B) plus A
H H H L A+B (A + ) plus A
H H H H A minus 1 A minus 1

2. Basic memory model using flip-flops

2.1 Edge triggered Flip-flops

 In electronics, a flip-flop is a circuit that has two stable states and can be used to store state
information.
 It is the basic storage element in sequential logic.
 Flip-flops and latches are a fundamental building block of digital electronics systems used
in computers, communications, and many other types of systems.
 Flip-flops and latches are used as data storage elements. Such data storage can be used for
storage of state, and such a circuit is described as sequential logic.
 Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge
triggered).
 Although the term flip-flop has historically referred generically to both simple and clocked
circuits, in modern usage it is common to reserve the term flip-flop exclusively for
discussing clocked circuits
 The simple ones are commonly called latches. Using this terminology, a latch is level-
sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes
transparent, while a flip flop's output only changes on a single type (positive going or
negative going) of clock edge.

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 Microprocessor Interfacing & Programming LAB: 01

D CK Q
0 0 1
1 1 0

X Q (previous) (previous)
X 0/1 Q (previous) (previous)

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Task 3:
Draw the waveform for D flip flop.

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 Microprocessor Interfacing & Programming LAB: 01
2.2 74HC173 - quad D-type flip-flop with 3 state output (positive-edge
trigger)

 The 74HC/HCT173 is 4-bit parallel load registers with clock enable control, 3-state
buffered outputs (Q0 to Q3) and master reset (MR).
 When the two data enable inputs (E1 and E2) are LOW, the data on the Dn inputs is loaded
into the register synchronously with the LOW-to-HIGH clock (CP) transition.
 When one or both En inputs are HIGH one set-up time prior to the LOW-to-HIGH clock
transition, the register will retain the previous data. Data inputs and clock enable inputs are
fully edge-triggered and must be stable only one set-up time prior to the LOW-to-HIGH
clock transition.
 The master reset input (MR) is an active HIGH asynchronous input. When MR is HIGH,
all four flip-flops are reset (cleared) independently of any other input condition. The 3-state
output buffers are controlled by a 2-input NOR gate.
 When both output enable inputs (OE1 and OE2) are LOW, the data in the register is
presented to the Qn outputs.

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Task 4:
From the above flip flop IC fill the following table.

Pin No. Symbol Name & Function

1, 2 0E1,OE2 Active low allows Output Enable
(logic zero)
3, 4, 5, 6 Q0,Q1,Q2,Q3 Pins that show Output
7 Cn or Cp or Clock pin
CLK
8 GND Ground
9, 10 E1,E2(Active Enable Input that enable at active
low) low
11, 12, 13, 14 D0,D1,D2,D3 Input pins
15 MR Master Reset to clear data.
16 VCC Input voltage.

2.3 Implementing a basic memory model using 74HC173

A basic memory model can be implemented using 74HC173. This IC contains 4 positive edge
triggered D Flip Flops, which can be used to store a 4-bit data. Combining several of these
together can result in the creation of a basic memory block which can be read from and written
to.

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Task 5:
Implement memory using 74HC173. This memory must have the capability of writing to or
reading from any of the 4 memory locations.

To implement a 4x4 memory using four 74HC173 ICs:

1. IC Arrangement: Use four chips to create a 4-bit wide, 4-location memory.

2. Connections: Connect each chip’s data inputs (D0-D3) to a data bus, and outputs
(Q0-Q3) to an output bus.
3. Control:
o Enable (G): Use a decoder to activate the desired memory location.
o Write Enable (M): Toggle for read (high) or write (low).
o Clock (CP): Sync all chips with a common clock.
o Clear (MR): Use a reset line to clear all memory.

Operation:

 Write: Set Write Enable low, select location via decoder, input data, and clock it in.
 Read: Set Write Enable high, select location, and read data from the output bus.

This setup provides a 4x4 bit memory array using 74HC173 ICs.

a) 2x4 (2 memory locations each of 4-bits)

The 2x4 memory configuration comprises 2 memory locations, each capable of storing 4 bits of data.

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b) 4x4 (4 memory locations each of 4-bits)

The 4x4 memory matrix denotes a configuration with 4 memory locations, each capable of storing 4
bits of data.

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 Microprocessor Interfacing & Programming LAB: 01

Marking Criterion:

LLO Statement Assessment Exemplary Proficient Developing Beginning

Method (86%-100%) (71%-85%) (56%-70%) (0%-55%)
2 Use hardware & Practical Skill Utilizes tools with Proficiently uses Navigates tools Struggles with tool
software tools Observation during advanced tools, with basic functionality,
(Proteus, Atmel experimentation proficiency, demonstrating proficiency, using impacting navigation
studio, SuperPro regarding
effectively navigating effective navigation fundamental and use.
programmer, serial individual and team
terminal) to work their features and and utilization. features.
enhance capabilities.
implementation and Successfully Accomplishes Struggles to
debugging Accomplishes tasks completes tasks by tasks with some accomplish tasks due
capabilities with precision and integrating tools limitations in tool to limited tool
creativity, effectively appropriately. integration or use. utilization.
integrating tools for
enhanced outcomes. Shows basic
Adapts to changes adaptability to
and shifts roles some changes but
Demonstrates
within the team struggles with
exceptional
effectively when others.
adaptability by Struggles to adapt to
effectively adjusting needed.
changes or shifts in
to changing team dynamics,
circumstances and affecting progress.
roles within the team
4 Write a Organization /
comprehensive lab Structure The report follows The report follows The report follows The report follows the
report as per the (Report) the prescribed the format. the format, but format, but there may
prescribed format format. each section may have been several
Almost all the not have been omissions.
All the components components of the completely
of the solution are solution are addressed. Most of the necessary
addressed in detail. addressed in detail. diagrams, equations
Some of the and graphs are
All necessary Almost all the necessary missing.
diagrams, equations, necessary diagrams, diagrams,
and graphs are equations and equations and Students do not
correctly labeled. graphs are included. understand the
graphs are missing.
connection between
The procedure and The procedure and the initial problem and
Student may have
results are described results are mostly the outcome.
understood the
clearly and in an described clearly connection
organized fashion. and in an organized between the initial
fashion. problem and the
outcome, but this
understanding is
not expressed in
the report.

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