Rules of RTL Conversion on RISC-V Processor

Design
Demyana Emil
Teaching Assistant, Electrical Department, Faculty of Engineering, Fayoum University, Egypt
Email: [email protected]

Mohammed Hamdy
Assistant professor, Electrical Department, Faculty of Engineering, Fayoum University, Egypt
Email: [email protected]

Gihan Nagib
Associate professor, Electrical Department, Faculty of Engineering, Fayoum University, Egypt
Email: [email protected]

Abstract: Hardware design is an important process in computer architecture, digital electronics and more fields
related to computer science. Register transfer level (RTL) synthesis, an important step in digital hardware design,
abstracts the model of an implemented design to a digital electronics circuit in registers form. This paper introduces
some rules on an implemented design to make it satisfy with the RTL level rules. These rules ease the conversion of
this design to RTL circuit. This process is occurring after simulation level directly. Hence, the paper discusses some
common issues that some hardware designers may make on simulation level that prevent their design to work on RTL
successfully. The work introduces solutions for these issues, in addition to some common simulation errors that can
be avoided. If the rules of RTL have been followed in simulation level (initial step), it reduces more time exerted on
modification on design after the simulation level for making the design available to work on RTL. It is also rare to
find such this topic explained clearly and separately, however, it is so important. This work depends on an
implemented open processor. This processor is single-core and works under RISC-V instruction set.

Keywords: RTL; Open processors; Hardware design; RISC-V.

hardware language [5]. The main simulator tool that
1.INTRODUCTION has been used for testing is Vivado 2020.2 [6]. As
There is a big difference between successfully shown in Figure 1, the block diagram of the Taiga
working design in simulation level, and its availability processor. Most of implemented blocks for this
of working as a digital electronics circuit. In case of processor are shown in Figure 1. The blocks that will
failing to be converted to hardware electronics circuit, be talked about is the memory and the register file.
it can’t be fabricated. It appears successfully work in
simulation but in reality, can’t be converted to
hardware circuit. More designers start in simulation
writing their design but don’t make attention to the
RTL verifications [1]. It makes them get into redesign
the project to adapt RTL rules. This problem is a
critical one because the design itself takes more efforts
and more time to be successfully work. Not more
papers discuss this topic independently. Just few ones
dicuss the RTL system such as the work of Johnson,
R.E., Mcconnell, C., Lake, J.M. [2].
An open RISC-V processor (Taiga) was chosen to
be worked on as a main block [3]. This processor has
various bugs and some of them have been corrected
depended on our developed algorithms (they will be
shown later). This processor is available for Figure 1 Block diagram of single-core Taiga processor
modification, is flexible and modular. It has been [3]
implemented based on RISC-V instruction set
architecture [4]. The design is based on SystemVerilog
 For sure, the coming work isn’t the total rules for language has a fixed always procedure format without
RTL level implementation and verification. Just this additional forms. But SystemVerilog has three types
work is deduced from extensive work design and of always procedures like always [21], always_ff [5]
testing on the open source RISC-V processor. and always_comb [22]. For Verilog, to access always
Additionally, it shows some simulation errors, that body for starting a design, there some assignment rules
should be avoided, and they can be avoided. for included signals like blocking and non-blocking
This work is sectioned as: headline 2 introduces a assignments [23].
related work with RTL model. Headline 3 introduces
some simulation errors that can be corrected and 3. COMMON SIMULATION ERRORS AND
avoided in the future by the designers. Headline 4 CORRECTION
discusses RTL design paradigms. It explains that how On design, the common problem that may be
to be avoided or corrected as possible depended on set occurred is “don’t care signals”. This problem
of different developed algorithms. Additionally, it expresses that the designed block hasn’t finished its
discusses the result of these algorithms after they have process. So, the output still with no value until the
been applied on the processor design. It shows the block process is done. It also affects other dependent
difference among multiple procedures that are mainly signals at the same block in case of combining.
used in the digital electronics design. Headline 5 is a Additionally, it affects other signals in other blocks in
conclusion about what has been achieved; the result of case of block’s output signals dependency.
applied algorithms. In brief, it shows how they have an
effective role on the design, and improved the output Example:
result of some blocks. It contains what has been If interface1 & interface2, shown in Figure 2,
mentioned about simulation errors. In addition, it aren’t initiated at time zero, they become “don’t care”
includes our future work on the processor design and signals. In case inteface1 has arrived but interface2
how RTL rules can be used further more for more hasn’t arrived yet, the output that depends on
enhancement. interface1 and interface2 may become don’t care.

2. RELATED WORK
This partition explains the historical work about
RTL rules of Verilog coding and how it is related with
real hardware circuits [7-8]. These cited rules are
estimated for Verilog HDL (Hardware Design
Language) and can be used for different digital
electronics systems like VLSI [9-10]. But for
SystemVerilog, the design requires additional rules
[11].
Multiple standard HDLs are available for
hardware structure design, to get the preferable one,
Pong makes a good comparison between
SystemVerilog and Verilog [12]. It has been shown
from the previous comparison that the SystemVerilog Figure 2 Block diagram of signal dependency
is prefered for more efficient verification. Like that has
been used in a peripheral device for management Table I shows different logic operations and the
process between two RvCores [13]. SystemVerilog is output signal that depends on set of valuable and don’t
used for more accurate synthesis for complex design care signals. If block3’s output depends on interface1
[14]. RTL has Multiple fields that can be implemented and interface2, the output still “don’t care” in some
like CNN (convolutional neural networks) [15], FINN cases like case1 and case4 in Table I.
matrix vector [16] and can be used in Matlab (math
works) [17]. TABLE I LOGIC OPERATIONS BETWEEN VALUABLE AND
RTL coding purpose is for FPGA [18]. The output DON’T CARE SIGNALS
RTL model is ready to work on the FPGA kits. Like
Interface Interface Logic Outpu
these designs, can be optimized for more 1 2 operatio t (y)
enhancement too [19]. n
Case X 1 OR 1
Additionally, to avoid getting error such as 1 1 X
multiple drivers and so on simulator, some rules are Case X 0 OR X
explained for this purpose [20]. RTL designers always 2 0 X
use the always procedures. Each hardware language Case X 1 AND X
has different forms of always procedures. Verilog 3 1 X
 Case X 0 AND 0 y =1;
4 0 X Else
y =0;

To avoid the problem due to “don’t care” signals, TABLE IV ALGORITHM 2 OF DON’T CARE SIGNAL
there are two solutions that can be implemented. They SOLUTIONS
are shown in Table II.
Algorithm 2
TABLE II DON’T CARE SIGNALS’ SOLUTIONS
If (interface1 & interface2)
Case Solution 1 Solution 2 y =1;
Case2 (in Algorithm 1 Initialize Else
Table I) interface 1&2 y =0;
by zero (in
block 1 &2) The two solutions can be implemented according
Case3 (in Algorithm 2 Initialize to the design. Algorithm 1 and algorithm 2 have been
Table I) interface 2&1 implemented on a RISC-V processor [3]. Figure 3
(in block 2&1) shows the problem that has been result from “don’t
by zero care” signals coming as an input signal to a block in
the processor design.
To solve the above problem in hardware design,
Algorithm 1 and Algorithm 2 implement simple The waveforms in Figure 3 express set of data stored
temporary solutions. These solutions can be at a data structure acting as registers. The locations
implemented for signals that you don’t want to shown in the Figure 3 entitle that there are set of
initialize. locations have updated their contents with new data in
case the others haven’t. This is the problem, the input
TABLE III ALGORITHM OF DON’T CARE SIGNAL
SOLUTIONS
“don’t care” signals have affected this block not to
make it available to update some locations at its data
Algorithm 1 structure unit. Location 3 is an example for those
which have been affected by this problem.
If (interface1 | interface2)

Figure 3 The problem of don’t care affecting output signals of a block design

Figure 4 shows the block signals after

implementing the previous Algorithm 1. Algorithm 2 according to the logic operation processed on the input
is available too. Algorithm 1 has been implemented signals at the block.
Algorithm 2 can be applied if the logic operation on
the block input signals is “And” logic.
 Figure 4 The designed block signals after implementing Algorithm 1

4. RTL RULES Example: always_comb begin

RTL is a required stage in design [24]. As // Code steps;
mentioned in Introduction, it is for conversion your End
design to applicable hardware logic circuit.
3. Always_ff: is a procedure acting as a wrapper
4.1 Main Procedures of code lines in case of changing at a clock
The main important procedures in hardware design signal. It is triggered on positive edge,
are always, always_ff and always_comb. There are negative edge or both [22]. It also can be
also some important statements such as “assign” triggered on another signal acting like the
statement. Each one of the previous process has a clock signal.
different meaning:
Example: always_ff @ (posedge clk) begin
1. Always: is a procedure acting as a wrapper of // Code lines;
a segment of code in case some special End
signals change [21].
4. Assign: is a statement that permanently
Example: always @ (signal) begin copies the right-hand side at the left-hand
// Code segments; side.
End
Example: assign exp_1 = exp_2;
2. Always_comb: is a procedure acting as a
wrapper of design code steps. It is used in 5. If … statement: is an if statement like that in
case you want these code steps permanently C++ language [25].
executed even in no changing on any signals.
It will be triggered automatically once at time Example: if (condition_1 is true) begin
zero [5]. It has no limitation to be triggered. // Code segment;
End
 Else if (condition_2 is true) begin TABLE VI AN EXAMPLE OF ASSIGN STATEMENT INTO
AN ALWAYS PROCEDURE
// Another code segment;
End
Example_1
Else begin Generate
// code segment; Always_ff @ (posedge clk) begin
End If (condition_1 is true) begin
6. Generate statement: it is used if a for loop Assign interface_1 = value_1;
statement will be used (iterative process as .
shown in Table V) or for conditional blocks. .
.
TABLE V ALGORITHM 3 OF GENERATE End
STATEMENT FOR ITERATIVE PROCESS End
Endgenerate
Algorithm 3 Generate statement for iterative
process
Table VI is an example of an unavailable design
Int num = 6; for RTL level but it works normally in simulation. It
Genvar i; should be replaced by another algorithm. Such that is
Generate shown in Table VII.
For (i= 0 ; i < num; i ++) begin
If (condition) begin TABLE VII ALGORITHM 4 OF RULE 1
.
. Algorithm 4
.
End Logic signal_1;
End Assign interface_1 = signal_1;
Endgenerate Generate
Always_ff @ (posedge clk) begin
If (condition_1 is true) begin
4.2 Rules of RTL Level Assign interface_1 = value_1;
For RTL implementation, there some rules for .
.
hardware design. Below examples show obviously
.
what should be taken on HW development. End
End
• Rule_1: not to insert the Assign statement Endgenerate
into any type of always procedure.

The big common error is to insert an assign From example_1; it is shown that the first rule is
statement in any type of the previous always not to insert any assign statement in always_ff
procedure. If the block has interface of set of signals procedure. Figure 5 shows the problem. Figure 6
(Ex: interface_1 shown in the below example (Table shows the waveform after Algorithm 4 is appended.
VI))

Figure 5 Waveform of signals in case assign statement is appended in always_ff procedure

 Figure 6 Waveform of signals after algorithm 4 is implemented

statement body would be updated by zero. Table VIII

• Rule_2: for any implemented memory, in
shows this algorithm applied on always_ff.
RTL on Vivado, it is a must for its size not to
exceed 1000000 bits. TABLE VIII IF STATEMENT INSIDE ALWAYS_FF
PROCEDURE
• Rule_3: from example_1, it is noticed that
assign statement is usually used when Algorithm 5
updating an interface on a current block. It is Always_ff @ (posedge clk) begin
If (condition) begin
the third rule; when updating some signals in .
an interface of the block, it is a must to use .
assign statement. .
End
End
• Rule_4: in any always procedure in case of
using if statement, if the condition has been
Rule 4 is interpreted in Figure 7 on the waveforms
true at a clock cycle, then in the next clock
of an arbitrary block as an application of
cycle, has become false, all signals in the if
Algorithm 5.

Figure 7 Waveform of signals wrapped in always_ff procedure in case of using if statement

 In case of using always_comb instead of always_ff The difference is considered in the clock line.
in Algorithm 5, the waveforms differ a bit (Figure 8).

Figure 8 Waveform of signals wrapped in always_comb procedure in case of using if statement

So, from the two previous figures (Figure 7,8), it is paper has shown that we can apply some RTL rules in
option for the designer to choose the best procedure simulation first, hence we can avoid recodification on
for his design according to the main behavior. In the our developed design. Some extensive tests have
two procedures, it has been found that if the condition applied on an open single RvCore and we have applied
is true, the copying process is done successfully. our developed algorithms and showed our results of
Otherwise, (take into consideration Algorithm 4) these algorithms on the waveforms of arbitrary blocks
interface_1 is updated by zero even signal_1 hasn’t of the processor. We have shown the performance of
been changed to zero. Take into your consideration these blocks before and after applying the algorithms.
that this copying process doesn’t occur continuously These algorithms have corrected more bugs in this
nor automatically. It occurs only in case of true processor design. The paper also has discussed some
condition otherwise interface_1 doesn’t keep its value special simulation errors on design and how they have
taken from signal_1 at a time while true condition. been corrected by multiple methods. It has shown
multiple solutions according to the designer target. It
• Rule_5: if you need to define a memory has been shown that RTL synthesis process has
block, it should be finite in size. different rules from simulation rules. Some rules,
• Rule_6: when the memory is loaded by a result from extensive testing, have been presented and
program, it should start being loaded the explained in details. SystemVerilog hardware
initial address of the memory. Also, it should language has been used to implement the previous
be loaded by a binary program file only. algorithms. Vivado tool is the main tool that has been
used.
In the future, we will invest more time in
improving the design performance according to what
5. CONCLUSION AND FUTURE have been addressed in RTL rules. Additionally, how
WORK to implement a main memory based on RTL rules and
The paper has shown the difference among set of reduce the total number of clock cycles consumed for
procedures and special statements in simulation. it. How to build a simulation memory. How to make
Additionally, simulation level is a base level in digital the design work on the FPGA or Zedboard kits. Hence,
hardware design to check the working design we can compare our result with standard results. We
correctly. The RTL process is a second important level will use standard benchmarks to test and verify the
in hardware design following the simulation level. The total design.
 Implementation of FINN Matrix Vector Compute Unit”,
arXiv:2201.11409v2

REFERENCES [16] Alex Krizhevsky, Ilya Sutskever, Geoffrey E. Hinton, (May

2017), “Image net classification with deep convolutional
[1] A. Yadav, P. Jindal and D. Basappa, (2020), "Study and Analysis neural networks,”
of RTL Verification Tool" IEEE Students Conference on Commun. ACM, vol. 60, no. 6, pp. 84–90.
Engineering & Systems (SCES), pp. 1-6, doi:
10.1109/SCES50439.2020.9236747. [17] “RTL Design Rule Parameters”, retrieved date: [2019], online
at:
[2] Johnson, R.E., Mcconnell, C., Lake, J.M. (1992). “The RTL https://www.mathworks.com/help/hdlcoder/ug/rtl-design-
System: A Framework for Code Optimization” In: Giegerich, rules.html
R., Graham, S.L. (eds) Code Generation — Concepts, Tools,
Techniques. Workshops in Computing. Springer, London. [18] Shipitko, Oleg & Grigoryev, Anton. (2018). Gaussian filtering
https://doi.org/10.1007/978-1-4471-3501-2_14 for FPGA based image processing with High-Level Synthesis
tools, pp. 15-200
[3] Eric Matthews and Lesley Shannon. (2017), “TAIGA: A
Configurable RISC-V Soft-Processor Framework for [19] Johnson, R.E., Mcconnell, C., Lake, J.M. (1992), “The RTL
Heterogeneous Computing Systems Research” SEMANTIC System: A Framework for Code Optimization”. In: Giegerich,
SCHOLAR, Vol III R., Graham, S.L. (eds) Code Generation — Concepts, Tools,
Techniques. Workshops in Computing. Springer, London.
[4] Andrew Waterman, Yunsup Lee, David A. Pattson, Krste https://doi.org/10.1007/978-1-4471-3501-2_14
Asanovic, [May, 2014], “The RISC_V Instruction Set
Manual” Volume 1, Version 2.0 [20] Y. Zhang, H. Ren and B. Khailany, (2020), "Opportunities for
RTL and Gate Level Simulation using GPUs (Invited Talk)",
[5] Vaibbhav Taraate, (2020) “SystemVerilog for Hardware IEEE/ACM International Conference on Computer Aided
Description RTL Design and Verification”. Springer Design (ICCAD), pp. 1-5.
https://doi.org/10.1007/978-981-15-4405-7
[21] Wilson Snyder, (2021) “Verilator”

[6] Vivado Design Suite User Guide, [22] Stuart Sutherland Simon Davidmann Peter Flake,
http://www.xilinx.com/warranty.htm “SystemVerilog For Design Second Edition”. Springer
Science+Business Media, LLC
[7] S. Gayathri and T. C. Taranath, (2017), "RTL synthesis of case
study using design compiler" International Conference on [23] “Programmable Logic/Verilog RTL Coding Guidelines”,
Electrical, Electronics, Communication, Computer, and retreived date: [2017], online at:
Optimization Techniques (ICEECCOT), pp. 1-7, doi: https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_
10.1109/ICEECCOT.2017.8284603. RTL_Coding_Guidelines

[8] Taraate, V. (2019), “RTL Design Guidelines”, In: Advanced [24] Michael Keating and Pierre Bricaud, (2001), “RTL Coding
HDL Synthesis and SOC Prototyping. Springer, Singapore. Guidelines”, National Chiao Tung University, pp. 12-32
https://doi.org/10.1007/978-981-10-8776-9_3
[25] Adam Drozdek, “Data Structures and Algorithms in C++”
[9] (2007), “RTL Coding Guidelines”, In: Digital VLSI Systems www.cengage.com/highered
Design. Springer, Dordrecht. https://doi.org/10.1007/978-1-
4020-5829-5_5 Authors Biography
[10] RTL DESIGN GUIDELINES, retreived date: [2022], online Demyana Emil, is teaching assistant at
available at:
Electrical Department, Electronics and
http://www.asic.co.in/DesignGuidlinesRTLcoding.htm
Communication Engineering major in
[11] “SystemVerilog RTL Tutorial”, retreived date: [2017], online Faculty of Engineering, Fayoum
at: University, Egypt. She has completed
https://www.doulos.com/knowhow/systemverilog/systemverilog- B.Sc. degree in Electronics and
tutorials/systemverilog-rtl-tutorial/ Communication Engineering specialized
in Embedded System at Fayoum
[12] Pong P. Chu, (May 2018), “SystemVerilog vs Verilog in RTL University. Her research interests are
Design”, pp. 1-4
computer architecture, synchronized
[13] Demyana Emil, Mohammed Hamdy, and Jihan Nagib, (2022), data, hardware design and software
“Dual-RvCore32IMA: Implementation of a Peripheral device development.
to Manage Operations of Two RvCores” 4 th International
Conference on Intelligen Computing, Information and Control
System, Springer, pp. 4-10

[14] Stuart Sutherland, Don Mills, (2013), “Synthesizing

SystemVerilog
Busting the Myth that SystemVerilog is only for Verification”,
SNUG Silicon Valley, pp. 4-20

[15] Syed Asad Alam, David Gregg, Giulio Gambardella, Thomas

Preusser, Michaela Blott, (April 2022), “On the RTL
 Gihan Nagib, is associate
Mohammed Hamdy, is professor at Electrical
assistant professor at Engineering Department in
Electrical Department, Faculty of Engineering,
Electronics and Fayoum University, Egypt.
Communication She has completed B.Sc.
Engineering major in degree in Computer and
Faculty of Engineering, system Engineering, Ain
Fayoum University, Shams University. She has completed Diplome
Egypt. He has completed D'etudes Approfondies en Automatique,
B.Sc. degree in Electronics and Communication productique, Theorie des systemes (DEA) from
Engineering department at Fayoum University. He has INPG University, LAG, Grenoble FRANCE. Earned
completed M.Sc. degree in Electronics and her PhD from INPG University, Grenoble, France in
Communication Engineering at Cairo University. His 1994. She has over 26 years’ experience in teaching,
research interests are hardware design, interconnect research and consulting. Her research interests are
network, MultiCore processor and controllers. He has Intelligence Computation, computer networks and
completed PhD in Mechatronics at Japanese University, Computer Architecture. She published many
Egypt. His research interest is image processing. Research papers in various International journals
and conferences.