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The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.

Continuity of document content

The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.

Continuity of ordering part numbers

Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.

www.infineon.com
 EZ-PD CCG4

USB Type-C Port Controller

EZ-PD CCG4, USB Type-C Port Controller

General Description
EZ-PD™ CCG4 is a dual USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG4 provides
a complete dual USB Type-C and USB-Power Delivery port control solution for notebooks, power adapters and docking stations. It
can also be used in dual role and downstream facing port applications. EZ-PD CCG4 uses Cypress’s proprietary M0S8 technology
with a 32-bit, 48-MHz Arm® Cortex®-M0 processor with 128 KB flash and integrates two complete Type-C Transceivers including the
Type-C termination resistors RP and RD.

Applications ■ Integrated dead battery termination for DRP (Power

Source/Sink) applications
■ Notebooks ■ Supports two USB Type-C ports
■ Power adapters ■ Integrated VCONN FETs to power EMCA cables
■ Docking stations ■ Integrated fast role swap and extended data messaging (not
supported for 33-ball CSP part)
Features
Low-Power Operation
32-bit MCU Subsystem
■ 2.7-V to 5.5-V operation
■ 48-MHz Arm Cortex-M0 CPU
■ Independent supply voltage pin for GPIO that allows 1.71-V to
■ 128-KB Flash
5.5-V signaling on the I/Os
■ 8-KB SRAM
■ Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.5 mA
Integrated Digital Blocks System-Level ESD on CC Pins
■ Up to four integrated timers and counters to meet response
■ ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
times required by the USB-PD protocol
on IEC61000-4-2 level 4C (on 40-pin QFN and 33-ball CSP
■ Four run-time serial communication blocks (SCBs) with only)
re-configurable I2C, SPI, or UART functionality
Hot Swappable I/Os
Clocks and Oscillators
■ Integrated oscillator eliminating the need for external clock ■ Port 0 I2C pins and CC1, CC2 pins are hot-swappable

Type-C and USB-PD Support Packages

■ Integrated USB Power Delivery 3.0 support (only PD 2.0 ■ 4.0 mm  4.0 mm, 0.5 mm, 24-pin QFN
support for 33-ball CSP part) ■ 6.0 mm  6.0 mm, 0.6 mm, 40-pin QFN
■ Two integrated USB-PD BMC transceivers ■ 2.4 mm x 2.5 mm, 0.5 mm, 33-ball CSP
[1] [2]
■ Integrated UFP (RD) and current sources for DFP (RP) on ■ Supports extended industrial temperature range
both Type-C ports (–40 °C to +105 °C)

Notes
1. UFP refers to Power Sink.
2. DFP refers to Power Source.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-98440 Rev. *M Revised December 8, 2020
 EZ-PD CCG4

Logic Block Diagram

CCG4: Single-Chip Type-C Controller

MCU Subsystem Integrated Digital Blocks I/O Subsystem

M1
4 x TCPWM CC_PORT05

CORTEX-M0 4 x SCB2

Programmable I/O Matrix

CC_PORT15
(I2C,SPI, UART)
48 MHz

Advanced High-Performance Bus (AHB)

2x VCONN
Profiles and FETs
Configurations (PORT0)

2x VCONN
Flash 2 x Baseband MAC
FETs
(128KB) (PORT1)

2 x Baseband PHY
GPIOs6

SRAM Integrated Rd3 and Rp4

(8KB)

4 x 8-bit SAR ADC

Serial Wire Debug

1. Timer, counter, pulse width modulation block

2. Serial communication block configurable as UART, SPI, or I2C
3. Termination resistor denoting a UFP
4. Current sources to indicate a DFP
5. Configuration channel
6. General purpose input/output

Document Number: 001-98440 Rev. *M Page 2 of 38

 EZ-PD CCG4

Contents
Available Firmware and Software Tools ......................... 4 Ordering Information ...................................................... 29
EZ-PD Configuration Utility ......................................... 4 Ordering Code Definitions ......................................... 29
EZ-PD CCG4 Block Diagram ............................................ 4 Packaging ........................................................................ 30
Functional Overview ........................................................ 5 Acronyms ........................................................................ 33
CPU and Memory Subsystem ..................................... 5 Document Conventions ................................................. 34
USB-PD Subsystem (SS) ............................................ 5 Units of Measure ....................................................... 34
System Resources ...................................................... 6 References and Links to Applications Collaterals ...... 35
Peripherals .................................................................. 7 Knowledge Base Articles ........................................... 35
GPIO ........................................................................... 7 Application Notes ...................................................... 35
Pinouts .............................................................................. 8 Reference Designs .................................................... 35
Power ............................................................................... 18 Kits ............................................................................ 35
Application Diagrams ..................................................... 19 Datasheets ................................................................ 35
Electrical Specifications ................................................ 21 Document History Page ................................................. 36
Absolute Maximum Ratings ....................................... 21 Sales, Solutions, and Legal Information ...................... 38
Device-Level Specifications ...................................... 22 Worldwide Sales and Design Support ....................... 38
Digital Peripherals ..................................................... 24 Products .................................................................... 38
Memory ..................................................................... 26 PSoC® Solutions ...................................................... 38
System Resources .................................................... 26 Cypress Developer Community ................................. 38
Technical Support ..................................................... 38

Document Number: 001-98440 Rev. *M Page 3 of 38

 EZ-PD CCG4

Available Firmware and Software Tools

EZ-PD Configuration Utility
The EZ-PD Configuration Utility is a GUI-based Microsoft Windows application developed by Cypress to guide a CCGx user through
the process of configuring and programming the chip. The utility allows users to:
1. Select and configure the parameters they want to modify
2. Program the resulting configuration onto the target CCGx device.
The utility works with the Cypress supplied CCG1, CCG2, CCG3, and CCG4 kits, which host the CCGx controllers along with a USB
interface. This version of the EZ-PD Configuration Utility supports configuration and firmware update operations on CCGx controllers
implementing EMCA and Display Dongle applications. Support for other applications, such as Power Adapters and Notebook port
controllers, will be provided in later versions of the utility.
You can download the EZ-PD Configuration Utility and its associated documentation at the following link:
http://www.cypress.com/documentation/software-and-drivers/ez-pd-configuration-utility

EZ-PD CCG4 Block Diagram

Figure 1. EZ-PD CCG4 Block Diagram

CPU Subsystem
CCG4
SWD/TC SPCIF
Cortex
32-bit FLASH SRAM ROM
M0
128 KB 8 KB 8 KB
48 MHz
AHB-Lite FAST MUL
Read Accelerator SRAM Controller ROM Controller
NVIC, IRQMX
System Resources
Lite
System Interconnect (Single Layer AHB)
Power
Sleep Control Peripherals
WIC
POR REF
PWRSYS
PCLK Peripheral Interconnect (MMIO)

Clock
Clock Control
WDT 2 x USB-PD 3.0
IMO ILO
4 x TCPWM
IOSS GPIO (5 x ports)

4 x SCB

Reset
Reset Control
XRES
2 X VCONN FET
2 x SAR ADC
CC BB PHY

Test
DFT Logic
DFT Analog

Pads, ESD
Power Modes High Speed I/O Matrix
Active/Sleep
Deep Sleep
27 x GPIOs, 2 OVTs

I/O Subsystem

Document Number: 001-98440 Rev. *M Page 4 of 38

 EZ-PD CCG4

Functional Overview USB-PD Subsystem (SS)

EZ-PD CCG4 has two USB-PD subsystems consisting of USB
CPU and Memory Subsystem
Type-C baseband transceivers and physical-layer logic. These
CPU transceivers perform the BMC and the 4b/5b encoding and
decoding functions as well as the 1.2-V analog front end. This
The Cortex-M0 CPU in EZ-PD CCG4 is part of the 32-bit MCU
subsystem integrates the required termination resistors to
subsystem, which is optimized for low-power operation with
identify the role of the EZ-PD CCG4 solution. RD is used to
extensive clock gating. It mostly uses 16-bit instructions and
identify EZ-PD CCG4 as a UFP in a DRP application. When
executes a subset of the Thumb-2 instruction set. This enables
configured as a DFP, integrated current sources perform the role
fully compatible binary upward migration of the code to higher
of RP or pull-up resistors. These current sources can be
performance processors such as the Cortex-M3 and M4, thus
programmed to indicate the complete range of current capacity
enabling upward compatibility. The Cypress implementation
on VBUS defined in the USB Type-C spec. EZ-PD CCG4
includes a hardware multiplier that provides a 32-bit result in one
responds to all USB-PD communication.
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a wakeup The USB-PD sub-system contains two 8-bit SAR (successive
interrupt controller (WIC). The WIC can wake the processor up approximation register) ADCs for analog to digital conversions.
from the Deep Sleep mode, allowing power to be switched off to The ADCs include an 8-bit DAC and a comparator. The DAC
the main processor when the chip is in the Deep Sleep mode. output forms the positive input of the comparator. The negative
The Cortex-M0 CPU provides a nonmaskable interrupt (NMI) input of the comparator is from a 4-input multiplexer. The four
input, which is made available to the user when it is not in use inputs of the multiplexer are a pair of global analog multiplex
for system functions requested by the user. busses an internal bandgap voltage and an internal voltage
proportional to the absolute temperature. All GPIO inputs can be
The CPU also includes a serial wire debug (SWD) interface,
connected to the global analog multiplex busses through a
which is a 2-wire form of JTAG. The debug configuration used for
switch at each GPIO that can enable that GPIO to be connected
EZ-PD CCG4 has four break-point (address) comparators and
to the mux bus for ADC use. The CC1 and CC2 pins of both
two watchpoint (data) comparators.
Type-C ports are not available to connect to the mux busses.
Flash To support the latest USB-PD 3.0 specification, CCG4 has
The EZ-PD CCG4 device has a flash module with a flash implemented the fast role swap feature. Fast Role Swap enables
accelerator, tightly coupled to the CPU to improve average externally powered docks and hubs to rapidly switch to bus
access times from the flash block. The flash block is designed to power when their external power supply is removed. For more
deliver two wait-states (WS) access time at 48 MHz and with details, refer to Section 6.3.17 (FR_Swap Message) in the
0-WS access time at 16 MHz. The flash accelerator delivers 85% USB-PD 3.0 specification.
of single-cycle SRAM access performance on average. Part of CCG4 is designed to be fully interoperable with revision 3.0 of
the flash module can be used to emulate EEPROM operation if the USB Power Delivery specification as well as revision 2.0 of
required. the USB Power Delivery specification.
SROM CCG4 supports Extended Messages containing data of up to
A supervisory ROM that contains boot and configuration routines 260 bytes. The Extended Messages will be larger than expected
is provided. by the USB-PD 2.0 hardware. To accommodate Revision 2.0
based systems, a Chunking mechanism is implemented such
that Messages are limited to Revision 2.0 sizes unless it is
discovered that both systems support the longer Message
lengths.

Document Number: 001-98440 Rev. *M Page 5 of 38

 EZ-PD CCG4

Figure 2. USB-PD Subsystem

To/From System Resources

vref iref

To/ from AHB 2 x 8-bit ADC

per Type-C port

From AMUX

VCONN FET Enable V5V

TxRx Enable
VCONN
2 x Digital Baseband PHY FETs
Tx_data Enable Logic
from AHB Tx 4b5b SOP BMC
SRAM Encoder Insert Encoder

TX Rp
CRC CC1
Rx_data RX RD1
to AHB Rx 4b5b SOP BMC
SRAM Decoder Detect Decoder CC2
Ref
Comp DB
Active Rd RD2
CC control Rd
CC detect
8kV IEC ESD
2 x Analog Baseband PHY
Deep Sleep Reference Enable Deep Sleep RD1 shorted to CC1 and RD2 shorted to CC2 for DRP applications using
Vref & Iref Gen vref, iref bondwire. For DFP applications, RD1 and RD2 not shorted to CC1 and CC2.
Dead Battery (DB) Rd termination removed after MCU boots up
Functional, Wakeup Interrupts

System Resources CCG4 can operate from three different power sources over the
Power System range of 2.7 to 5.5 V and has three different power modes,
transitions between which are managed by the power system.
The power system is described in detail in the section Power on EZ-PD CCG4 provides Sleep and Deep Sleep low-power
page 18. It provides the assurance that voltage levels are as modes.
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are Clock System
as required for proper function or generate resets (brown-out The clock system for EZ-PD CCG4 consists of the internal main
detect (BOD)) or interrupts (low voltage detect (LVD)). EZ-PD oscillator (IMO) and the internal low-power oscillator (ILO).

Document Number: 001-98440 Rev. *M Page 6 of 38

 EZ-PD CCG4

Peripherals GPIO
Serial Communication Blocks (SCB) EZ-PD CCG4 has 30 GPIOs that includes the I2C and SWD pins,
EZ-PD CCG4 has four SCBs, which can be configured to which can also be used as GPIOs. The I2C pins from only
implement an I2C, SPI, or UART interface. The hardware I2C SCB 0 are overvoltage-tolerant. The number of available GPIOs
blocks implement full multi-master and slave interfaces capable vary with the part numbers. The GPIO block implements the
of multimaster arbitration. In the SPI mode, the SCB blocks can following:
be configured to act as a master or a slave. ■ Seven drive strength modes:
In the I2C mode, the SCB blocks are capable of operating at ❐ Input only
speeds up to 1 Mbps (Fast Mode Plus) and have flexible ❐ Weak pull-up with strong pull-down
buffering options to reduce interrupt overhead and latency for the ❐ Strong pull-up with weak pull-down
CPU. These blocks also support I2C that creates a mailbox ❐ Open drain with strong pull-down
address range in the memory of EZ-PD CCG4 and effectively ❐ Open drain with strong pull-up
reduce I2C communication to reading from and writing to an ❐ Strong pull-up with strong pull-down
array in memory. In addition, the blocks support 8-deep FIFOs
❐ Weak pull-up with weak pull-down
for receive and transmit which, by increasing the time given for
the CPU to read data, greatly reduce the need for clock ■ Input threshold select (CMOS or LVTTL)
stretching caused by the CPU not having read data on time.
■ Individual control of input and output buffer enabling/disabling
The I2C peripherals are compatible with the I2C Standard-mode, in addition to the drive strength modes
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus ■ Hold mode for latching previous state (used for retaining I/O
I/Os are implemented with GPIO in open-drain modes. state in Deep Sleep mode)
The I2C port on SCB 1, SCB 2 and SCB 3 blocks of EZ-PD CCG4 ■ Selectable slew rates for dV/dt related noise control to improve
are not completely compliant with the I2C spec in the following: EMI
■ The GPIO cells for SCB 1 to SCB 3 I2C port are not During power-on and reset, the I/O pins are forced to the disable
overvoltage-tolerant and, therefore, cannot be hot-swapped or state so as not to crowbar any inputs and/or cause excess
powered up independently of the rest of the I2C system. turn-on current. A multiplexing network known as a high-speed
I/O matrix is used to multiplex between various signals that may
■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of connect to an I/O pin.
0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a
VOL maximum of 0.6 V.
■ Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the bus load.

Timer/Counter/PWM Block (TCPWM)

EZ-PD CCG4 has up to four TCPWM blocks. Each implements
a 16-bit timer, counter, pulse-width modulator (PWM), and
quadrature decoder functionality. The block can be used to
measure the period and pulse width of an input signal (timer),
find the number of times a particular event occurs (counter),
generate PWM signals, or decode quadrature signals.

Document Number: 001-98440 Rev. *M Page 7 of 38

 EZ-PD CCG4

Pinouts

Table 1. Pinout for CYPD4225-40LQXIT, CYPD4226-40LQXIT, and CYPD4236-40LQXIT

Pin ESD
Group Pin Name Description
Number Protection
USB Type-C CC1_P0 9 HBM, IEC USB PD connector detect/Configuration Channel 1
Port 0
CC2_P0 7 HBM, IEC USB PD connector detect/Configuration Channel 2
USB Type-C CC1_P1 22 HBM, IEC USB PD connector detect/Configuration Channel 1
Port 1
CC2_P1 24 HBM, IEC USB PD connector detect/Configuration Channel 2
VBUS VBUS_P_CTRL_P0/P1.6 11 HBM Full rail control I/O for enabling/disabling Provider load FET of
Control USB Type-C port 0
VBUS_C_CTRL_P0/P1.7 12 HBM Full rail control I/O for enabling/disabling Consumer load FET of
USB Type-C port 0/SCB0 (see Table 3 on page 14 through
Table 6 on page 14)
VBUS_P_CTRL_P1/P4.2 39 HBM Full rail control I/O for enabling/disabling Provider load FET of
USB Type-C port 1
VBUS_C_CTRL_P1/P4.1 38 HBM Full rail control I/O for enabling/disabling Consumer load FET of
USB Type-C port 1
VBUS_DISCHARGE_P0/ 20 HBM I/O used for discharging VBUS line during voltage change
P2.5
VBUS_DISCHARGE_P1/ 40 HBM I/O used for discharging VBUS line during voltage change
P4.3
VCONN VCONN_MON_P0/P2.4 19 HBM VCONN_MON_P0 (Monitor VCONN for UVP condition on port
Control 0)/GPIO
SCL_2/VCONN_MON_P1/ 25 HBM SCB2 (see Table 3 on page 14 through Table 6 on page 14) or
P2.7 VCONN_MON_P1(Monitor VCONN for UVP condition on port 1)
Over-voltage OVP_TRIP_P0/P2.1 14 HBM VBUS overvoltage output indicator for port 0 (active LOW)
Protection
(OVP) OVP_TRIP_P1/P3.0 21 HBM VBUS overvoltage output indicator for port 1 (active LOW)

GPIOs and VBUS_MON_P0/P2.0 13 HBM VBUS_MON_P0 (VBUS overvoltage protection monitoring

Serial signal)/GPIO
Interfaces
HPD_P0/P2.3 18 HBM HPD_P0 (Hot Plug Detect I/O for port 0)/GPIO
HPD_P1/P3.4 30 HBM HPD_P1 (Hot Plug Detect I/O for port 1)/GPIO
MUX_CTRL_3_P1/ 34 HBM MUX_CTRL_3_P1 (Mux control for port 1) or VBUS Overcurrent
OCP_DET_P1/P3.5 Protection Input for port 1 (active LOW)
MUX_CTRL_2_P1/P3.6 35 HBM MUX_CTRL_2_P1 (Mux control for port 1)/SCB3 (see Table 3 on
page 14 through Table 6 on page 14)
MUX_CTRL_1_P1/P3.7 36 HBM MUX_CTRL_1_P1 (Mux control for port 2)/SCB3 (see Table 3 on
page 14 through Table 6 on page 14)
VBUS_MON_P1/P4.0 37 HBM VBUS_MON_P1(VBUS overvoltage protection monitoring
signal)
VSEL_2_P1/P3.1 27 HBM VSEL_2_P1(Voltage selection control for VBUS on port 1)/GPIO
I2C_SCL_SCB0_EC/P0.1 17 HBM SCB0/SCB3 (see Table 3 on page 14 through Table 6 on page 14)
I2C_SDA_SCB0_EC/P0.0 16 HBM SCB0/SCB2 (see Table 3 on page 14 through Table 6 on page 14)
I2C_INT_EC/P2.2 15 HBM I2C Interrupt line
I2C_SCL_SCB1_AR/ 4 HBM SCB1 (see Table 3 on page 14 through Table 6 on page 14) or
VSEL_1_P1/P1.0 VSEL_1_P1 (Voltage selection control for VBUS on port 1)

Document Number: 001-98440 Rev. *M Page 8 of 38

 EZ-PD CCG4

Table 1. Pinout for CYPD4225-40LQXIT, CYPD4226-40LQXIT, and CYPD4236-40LQXIT (continued)

Pin ESD
Group Pin Name Description
Number Protection
GPIOs and I2C_SDA_SCB1_AR/ 3 HBM SCB0/SCB1 (see Table 3 on page 14 through
Serial VSEL_1_P0/P1.3 Table 6 on page 14) or VSEL_1_P0 (Voltage selection control for
Interfaces VBUS on port 0)
I2C_INT_AR_P0/ 5 HBM I2C interrupt line or VBUS Overcurrent Protection Input for port 0
OCP_DET_P0/P1.4 (active LOW)
I2C_INT_AR_P1/P1.5 6 HBM I2C interrupt line/SCB0/SCB1 (see Table 3 on page 14 through
Table 6 on page 14)
SDA_2/MUX_C- 26 HBM SCB2 (see Table 3 on page 14 through Table 6 on page 14) or
TRL_3_P0/VSEL_2_P0/P2. MUX_CTRL_3_P1 (Mux control for port 0) or VSEL_2_P0
6 (Voltage selection control for VBUS on port 0)
SCL_3/MUX_C- 29 HBM SCB3 (see Table 3 on page 14 through Table 6 on page 14)
TRL_1_P0/P3.3 /MUX_CTRL_1_P0 (Mux control for port 0)
SDA_3/MUX_C- 28 HBM SCB3 (see Table 3 on page 14 through Table 6 on page 14)
TRL_2_P0/P3.2 /MUX_CTRL_2_P0 (Mux control for port 0)
SWD_IO/AR_RST#/P1.1 1 HBM SWD_IO (serial wire debug I/O)/SCB0. See Table 3 on page 14
through Table 6 on page 14.
SWD_CLK/I2C_CFG_EC/ 2 HBM SWD Clock/I2C_CFG_EC
P1.2
Reset XRES[3] 10 HBM Reset input (active LOW)
Power V5V_P0 8 HBM 2.7-V to 5.5-V supply for VCONN FET of Type-C port 0
V5V_P1 23 HBM 2.7-V to 5.5-V supply for VCONN FET of Type-C port 1
VDDIO 32 HBM 1.71-V to 5.5-V supply for I/Os
VCCD 33 HBM 1.8-V regulator output for filter capacitor. This pin cannot drive
external load.
VDDD 31 HBM VDDD supply input/output (2.7 V to 5.5 V)
VSS EPAD HBM Ground supply

Note
3. This is firmware configurable GPIO. By default, this pin is floating. Firmware can add pull-up/pull-down and enable/disable I/O buffers.

Document Number: 001-98440 Rev. *M Page 9 of 38

 EZ-PD CCG4

Figure 3. 40-pin QFN Pin Map (Top View) for CYPD4225-40LQXIT, CYPD4226-40LQXIT, and CYPD4236-40LQXIT

MUX_CTRL_3_P1/OCP_DET_P1/P3.5
VBUS_DISCHARGE_P1/P4.3

VBUS_C_CTRL_P1/P4.1
VBUS_P_CTRL_P1/P4.2

MUX_CTRL_1_P1/P3.7
MUX_CTRL_2_P1/P3.6
VBUS_MON_P1/P4.0

VDDIO
VCCD

VDDD
40
39
38
37
36
35
34
33
32
31
SWD_IO/AR_RST#/P1.1 1 30 HPD_P1/P3.4
SWD_CLK/I2C_CFG_EC/P1.2 2 29 SCL_3/MUX_CTRL_1_P0/P3.3
I2C_SDA_SCB1_AR/VSEL_1_P0/P1.3 3 28 SDA_3/MUX_CTRL_2_P0/P3.2
I2C_SCL_SCB1_AR/VSEL_1_P1/P1.0 4 27 VSEL_2_P1/P3.1
I2C_INT_AR_P0/OCP_DET_P0/P1.4 5 26 SDA_2/MUX_CTRL_3_P0/VSEL_2_P0/P2.6
I2C_INT_AR_P1/P1.5 6 25 SCL_2/VCONN_MON_P1/P2.7
CC2_P0 7 24 CC2_P1
V5V_P0 8 23 V5V_P1
CC1_P0 9 22 CC1_P1
XRES 10 21 OVP_TRIP_P1/P3.0
11
12
13

17
14
15
16

18
19
20
VBUS_MON_P0/GPIO/P2.0
VBUS_C_CTRL_P0/P1.7

I2C_SDA_SCB0_EC/P0.0
I2C_SCL_SCB0_EC/P0.1
VBUS_P_CTRL_P0/P1.6

I2C_INT_EC/P2.2
OVP_TRIP_P0/P2.1

HPD_P0/P2.3

VBUS_DISCHARGE_P0/P2.5
VCONN_MON_P0/P2.4

Document Number: 001-98440 Rev. *M Page 10 of 38

 EZ-PD CCG4

Table 2. Pinout for CYPD4125-40LQXIT and CYPD4126-40LQXIT

Pin ESD
Group Pin Name Description
Number Protection
USB Type-C Port 0 CC1_P0 9 HBM, IEC USB PD connector detect/Configuration Channel 1
CC2_P0 7 HBM, IEC USB PD connector detect/Configuration Channel 2
VBUS Control VBUS_P_CTRL_P0/P1.6 11 HBM Full rail control I/O for enabling/disabling. Provider load FET
of USB Type-C port 0.
VBUS_C_CTRL_P0/P1.7 12 HBM Full rail control I/O for enabling/disabling. Consumer load
FET of USB Type-C port 0/SCB0 (see Table 3 on page 14
through
Table 6 on page 14).
VBUS_DIS- 20 HBM I/O used for discharging VBUS line during voltage change
CHARGE_P0/P2.5
VCONN Control VCONN_MON_P0/P2.4 19 HBM VCONN_MON_P0 (Monitor VCONN for OVP condition on
port 0)/GPIO
Over-voltage OVP_TRIP_P0/P2.1 14 HBM VBUS overvoltage output indicator for port 0 (active LOW)
Protection (OVP)
GPIOs and Serial P3.1 27 HBM SCB2 (see Table 3 on page 14 through Table 6 on page
Interfaces 14)/GPIO
VBUS_MON_P0/P2.0 13 HBM VBUS_MON_P0 (VBUS overvoltage protection monitoring
signal)/GPIO
HPD_P0/P2.3 18 HBM HPD_P0 (Hot Plug Detect I/O for port 0)/GPIO
P3.0 21 HBM GPIO
P3.4 30 HBM
P3.5 34 HBM
P3.6 35 HBM GPIO/SCB3 (see Table 3 on page 14 through Table 6 on page
14)
P3.7 36 HBM
P4.0 37 HBM GPIO
P4.1 38 HBM
P4.2 39 HBM
P4.3 40 HBM
I2C_SCL_SCB0_EC/P0.1 17 HBM SCB0/SCB3 (see Table 3 on page 14 through Table 6 on
page 14)
I2C_SDA_SCB0_EC/ 16 HBM SCB0/SCB2 (see Table 3 on page 14 through Table 6 on
P0.0 page 14)
I2C_INT_EC/P2.2 15 HBM I2C interrupt line
I2C_SCL_SCB1_AR/P1.0 4 HBM SCB1 (see Table 3 on page 14 through Table 6 on page 14)
I2C_SDA_SCB1_AR/ 3 HBM SCB0 or SCB1 (see Table 3 on page 14 through
VSEL_1_P0/P1.3 Table 6 on page 14) or voltage selection control for VBUS on
port 0
I2C_INT_AR_P0/ 5 HBM I2C interrupt line or VBUS Overcurrent Protection Input for
OCP_DET_P0/P1.4 port 0 (Active LOW)
P1.5 6 HBM GPIO/SCB0/SCB1 (see Table 3 on page 14 through Table 6
on page 14)
SCL_2/P2.7 25 HBM GPIO/SCB2 (see Table 3 through Table 6)
SDA_2/ 26 HBM SCB2 (see Table 3 on page 14 through Table 6 on page 14)
MUX_CTRL_3_P0/ or MUX_CTRL_3_P0 (Mux control for port 0), or Voltage
VSEL_2_P0/P2.6 selection control for VBUS on port 0

Document Number: 001-98440 Rev. *M Page 11 of 38

 EZ-PD CCG4

Table 2. Pinout for CYPD4125-40LQXIT and CYPD4126-40LQXIT (continued)

Pin ESD
Group Pin Name Description
Number Protection
GPIOs and Serial SCL_3/ 29 HBM SCB3 (see Table 3 on page 14 through Table 6 on page 14)
Interfaces MUX_CTRL_1_P0/P3.3 or MUX_CTRL_1_P0 (Mux control for port 0)
SDA_3/ 28 HBM SCB3 (see Table 3 on page 14 through Table 6 on page 14)
MUX_CTRL_2_P0/P3.2 or MUX_CTRL_2_P0 (Mux control for port 0)
SWD_IO/AR_RST#/P1.1 1 HBM Serial wire debug I/O (SWD IO)/SCB0. See Table 3 on page
14 through Table 6 on page 14 or Alpine Ridge Reset.
SWD_CLK/I2C_CFG_EC/ 2 HBM SWD Clock/I2C_CFG_EC
P1.2
Reset XRES[4] 10 HBM Reset input (active LOW)
Power V5V_P0 8 HBM 2.7-V to 5.5-V supply for VCONN FET of Type-C port 0
VDDIO 32 HBM 1.71-V to 5.5-V supply for I/Os
VCCD 33 HBM 1.8-V regulator output for filter capacitor. This pin cannot
drive external load.
VDDD 31 HBM VDDD supply I/O (2.7 V to 5.5 V)
VSS EPAD HBM Ground supply
No Connect NC 22 - These pins are not bonded
NC 23 -
NC 24 -

Note
4. This is firmware configurable GPIO. By default, this pin is floating. Firmware can add pull-up/pull-down and enable/disable IO buffers.

Document Number: 001-98440 Rev. *M Page 12 of 38

 EZ-PD CCG4

Figure 4. 40-pin QFN Pin Map (Top View) for CYPD4125-40LQXIT and CYPD4126-40LQXIT

OCP_DET_P0/P3.5

VDDIO
VCCD

VDDD
P4.3
P4.2
P4.1
P4.0
P3.7
P3.6
40
39
38
37
36
35
34
33
32
31
SWD_IO/AR_RST#/P1.1 1 30 P3.4
SWD_CLK/I2C_CFG_EC/P1.2 2 29 SCL_3/MUX_CTRL_1_P0/P3.3
I2C_SDA_SCB1_AR/VSEL_1_P0/P1.3 3 28 SDA_3/MUX_CTRL_2_P0/P3.2
I2C_SCL_SCB1_AR/P1.0 4 27 P3.1
I2C_INT_AR_P0/OCP_DET_P0/P1.4 5 26 SDA_2/MUX_CTRL_3_P0/VSEL_2_P0/P2.6
P1.5 6 25 SCL_2/P2.7
CC2_P0 7 24 NC
V5V_P0 8 23 NC
CC1_P0 9 22 NC
XRES 10 21 P3.0
11
12
13

17
14
15
16

18
19
20
VBUS_P_CTRL_P0/P1.6
VBUS_C_CTRL_P0/P1.7

I2C_SCL_SCB0_EC/P0.1

VBUS_DISCHARGE_P0/P2.5
VBUS_MON_P0/P2.0
OVP_TRIP_P0/P2.1
I2C_INT_EC/P2.2
I2C_SDA_SCB0_EC/P0.0

HPD_P0/P2.3
VCONN_MON_P0/P2.4

Document Number: 001-98440 Rev. *M Page 13 of 38

 EZ-PD CCG4

Table 3. Serial Communication Block (SCB0) Configuration

GPIO UART SPI Master SPI Slave I2C Master I2C Slave
P1.7 UART_TX_SCB0 SPI_MOSI_SCB0 SPI_MOSI_SCB0 VBUS_C_CTRL_P0 VBUS_C_CTRL_P0
P2.1 UART_RX_SCB0 SPI_CLK_SCB0 SPI_CLK_SCB0 VSEL_2_P0/ VSEL_2_P0/
VCONN_MON_P0 VCONN_MON_P0
P0.1 UART_RTS_SCB0 SPI_MISO_SCB0 SPI_MISO_SCB0 I2C_SDA_SCB0 I2C_SDA_SCB0
P0.0 UART_CTS_SCB0 SPI_SEL_SCB0 SPI_SEL_SCB0 I2C_SCL_SCB0 I2C_SCL_SCB0

Table 4. Serial Communication Block (SCB1) Configuration

GPIO UART SPI Master SPI Slave I2C Master I2C Slave
P1.0 UART_TX_SCB1 SPI_CLK_SCB1 SPI_CLK_SCB1 I2C_SCL_SCB1 I2C_SCL_SCB1
P1.3 UART_RX_SCB1 SPI_MISO_SCB1 SPI_MISO_SCB1 I2C_SDA_SCB1 I2C_SDA_SCB1
P1.5 UART_RTS_SCB1 SPI_SEL_SCB1 SPI_SEL_SCB1 GPIO GPIO
P1.1 UART_CTS_SCB1 SPI_MOSI_SCB1 SPI_MOSI_SCB1 SWD_IO SWD_IO

Table 5. Serial Communication Block (SCB2) Configuration

GPIO UART SPI Master SPI Slave I2C Master I2C Slave
P2.6 UART_TX_SCB2 SPI_MISO_SCB2 SPI_MISO_SCB1 I2C_SDA_SCB2 I2C_SDA_SCB2
P2.7 UART_RX_SCB2 SPI_MOSI_SCB2 SPI_MOSI_SCB2 I2C_SCL_SCB2 I2C_SCL_SCB2
P0.0 UART_RTS_SCB2 SPI_SEL_SCB2 SPI_SEL_SCB2 I2C_SCL_SCB0 I2C_SCL_SCB0
P3.0 UART_CTS_SCB2 SPI_CLK_SCB2 SPI_CLK_SCB2 AR_RST# AR_RST#

Table 6. Serial Communication Block (SCB3) Configuration

GPIO UART SPI Master SPI Slave I2C Master I2C Slave
P3.2 UART_TX_SCB3 SPI_MOSI_SCB3 SPI_MOSI_SCB3 I2C_SDA_SCB3 I2C_SDA_SCB3
P3.3 UART_RX_SCB3 SPI_MISO_SCB3 SPI_MISO_SCB3 I2C_SCL_SCB3 I2C_SCL_SCB3
P3.7 UART_RTS_SCB3 SPI_SEL_SCB3 SPI_SEL_SCB3 GPIO GPIO
P3.6 UART_CTS_SCB3 SPI_CLK_SCB3 SPI_CLK_SCB3 GPIO GPIO

Document Number: 001-98440 Rev. *M Page 14 of 38

 EZ-PD CCG4

Table 7. Pin List for CYPD4126-24LQXIT and CYPD4136-24LQXIT

Pin Name Pin Number ESD Protection Description
P1.2 1 HBM GPIO/SWD_CLK
P1.3 2 HBM GPIO
P1.5 3 HBM GPIO
CC2 4 HBM Configuration Channel 2
V5V 5 HBM 2.7-V to 5.5-V supply for VCONN FET of Type-C
CC1 6 HBM Configuration Channel 1
XRES 7 HBM Reset input (active LOW)
P1.7 8 HBM GPIO
P0.0 9 HBM SCB0_I2C_SDA
P0.1 10 HBM SCB0_I2C_SCL
P2.3 11 HBM HotPlug_Detect
P2.5 12 HBM GPIO/VBUS_DISCHARGE
P3.0 13 HBM GPIO
P2.6 14 HBM GPIO
P3.1 15 HBM GPIO
P3.2 16 HBM SCB3_I2C_SDA
P3.3 17 HBM SCB3_I2C_SCL
P3.4 18 HBM GPIO
GND 19 HBM Ground supply
VDDD 20 HBM VDDD supply input/output (2.7 V to 5.5 V)
VDDIO 21 HBM 1.71-V to 5.5-V supply for I/Os
VCCD 22 HBM 1.8-V regulator output for filter capacitor. This pin cannot drive external load.
P3.6 23 HBM GPIO
P1.1 24 HBM GPIO/SWD_DATA
VSS 25/EPAD HBM Ground supply

Figure 5. 24-pin QFN Pin Map for CYPD4126-24LQXIT and CYPD4136-24LQXIT

VDDIO
VCCD

VDDD

GND
P1.1
P3.6
24
23
22
21
20

19

P1.2 1 18 P3.4

P1.3 2 17 P3.3

P1.5 3 16 P3.2
24-QFN
CC2 4 15 P3.1

V5V 5 14 P2.6
CC1 6 13 P3.0
10
11

12
7
8
9
XRES
P1.7
P0.0
P0.1
P2.3

P2.5

Document Number: 001-98440 Rev. *M Page 15 of 38

 EZ-PD CCG4

Table 8. Pin List for CYPD4225A0-33FNXIT

Pin Name CCG4 Ball # ESD Description

Protection
P3.1 C6 HBM GPIO
P3.6 A6 HBM GPIO
P0.0 F5 HBM GPIO/optional SWD_DATA
P0.1 G8 HBM GPIO/optional SWD_CLK
P1.0 C10 HBM GPIO
P1.1 B11 HBM GPIO/SWD_DATA
P1.2 A10 HBM GPIO/SWD_CLK
P1.3 B9 HBM GPIO
P1.5 B7 HBM GPIO
P1.7 G10 HBM GPIO
P2.1 F7 HBM GPIO
P2.3 G6 HBM GPIO
P2.6 D5 HBM GPIO
P2.7 D3 HBM GPIO
P3.0 G4 HBM GPIO
P3.2 C2 HBM GPIO
P3.3 C4 HBM GPIO
P3.4 B1 HBM GPIO
USB PD connector detect/ Configuration Channel 2 - Port 0. This pin can be hot
CC2_P0 D9 HBM, IEC swappable.
V5V_P0 E10 HBM 5V supply for VCONN FETs - Port 0.
USB PD connector detect/ Configuration Channel 1 - Port 0. This pin can be hot
CC1_P0 E8 HBM, IEC swappable. RD1_P0 is shorted to CC1_P0.
XRES F9 HBM Reset input.
USB PD connector detect/ Configuration Channel 1 - Port 1. This pin can be hot
CC1_P1 F3 HBM, IEC swappable. RD1_P1 is shorted to CC1_P1.
V5V_P1 E4 HBM 5V supply for VCONN FETs - Port 1.
USB PD connector detect/ Configuration Channel 2- Port 1. This pin can be hot
CC2_P1 E2 HBM, IEC swappable.
VDDD B3 HBM VDDD supply input/output (2.7 V to 5.5 V)
VDDIO B5 HBM 1.71-V to 5.5-V supply for I/Os
VCCD A8 HBM 1.8-V regulator output for filter capacitor. This pin cannot drive external load.
VSS A2, C8, G2 HBM Ground supply
RD2_P0 D7 HBM Rd for Port 0.
RD2_P1 E6 HBM Rd for Port 1.

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 EZ-PD CCG4

Figure 6. 33-CSP Ball Map for CYPD4225A0-FNXIT (Bottom View)

10 8 6 4 2
11 9 7 5 3 1

P1.2 VCCD P3.6 VSS A

P1.1 P1.3 P1.5 VDDI O VDDD P3.4 B

P1.0 VSS P3.1 P3.3 P3.2 C

CC 2_P0 RD 2_P0 P2.6 P2.7 D

V5V_P0 CC 1_P0 RD 2_P1 V5V_P1 CC 2_P1 E

XRES P2.1 P0.0 CC 1_P1 F

P1.7 P0.1 P2.3 P3.0 VSS G

Document Number: 001-98440 Rev. *M Page 17 of 38

 EZ-PD CCG4

Power A separate I/O supply pin, VDDIO, allows the GPIOs to operate
at levels from 1.71 V to 5.5 V. The VDDIO pin can be equal to or
The following power system diagram shows the set of power less than the voltages connected to the V5V_P0 or V5V_P1 and
supply pins as implemented in EZ-PD CCG4. VDDD pins. The VDDIO supply should be less than or equal to
VDDD supply.
CCG4 will be able to operate from three possible external supply
sources: V5V_P0 for first Type-C port, V5V_P1 for second Type- The VCCD output of EZ-PD CCG4 must be bypassed to ground
C port and VDDD. via an external capacitor (in the range of 80 to 120 nF; X5R
CCG4 has the power supply input V5V_P0 and V5V_P1 pins for ceramic or better).
providing power to EMCA cables through integrated VCONN Bypass capacitors must be used from VDDD and V5V_P0 or
FETs. There are two VCONN FETs in CCG4 per Type-C port to V5V_P1 pins to ground; typical practice for systems in this
power either CC1 or CC2 pin. These FETs are capable of frequency range is to use a 0.1-µF capacitor on VDDD, V5V_P0
providing a minimum of 1W on the CC1 and CC2 pins for the and V5V_P1. Note that these are simply rules of thumb; for
EMCA cables. In USB-PD applications, the valid levels on critical applications, the PCB layout, lead inductance, and the
V5V_P0 and V5V_P1 supplies can range from 4.85 V to 5.5 V. bypass capacitor parasitic should be simulated to design and
The device’s internal operating power supply is derived from obtain optimal bypassing.
VDDD. In UFP mode, CCG4 operates in 2.7 V– 5.5V. In DFP and Figure 7 shows an example of the power supply bypass
DRP modes, it operates in the 3.0 V–5.5 V range. capacitors.
Figure 7. EZ-PD CCG4 Power and Bypass Scheme Example

[6] [7]
CC1_P1 CC2_P1

[5]
V5V_P1

CC1_P0 CC2_P0

V5V_P0 VDDD
Core Regulator
(SRSS-Lite)
VDDIO VCCD
2 x CC
GPIOs Core
Tx/Rx

VSS

Notes
5. V5V_P0 denoted power supply input for Type-C port 0
V5V_P1 denoted power supply input for Type-C port 1
6. CC1_P0:USB PD connector detect/Configuration Channel 1 for Type-C port 0
CC1_P1:USB PD connector detect/Configuration Channel 1 for Type-C port 1
7. CC2_P0:USB PD connector detect/Configuration Channel 2 for Type-C port 0
CC2_P1:USB PD connector detect/Configuration Channel 2 for Type-C port 1

Document Number: 001-98440 Rev. *M Page 18 of 38

 EZ-PD CCG4

Application Diagrams For the dual Type-C notebook application, these Type-C ports
can be power providers or power consumers simultaneously. In
Figure 8 and Figure 9 on page 20 show a dual Type-C port and addition, the CCG4 device controls the transfer of DisplayPort
a single Type-C port Notebook DRP application diagram using a signals over the Type-C interface using the display mux
CCG4 device. The Type-C port can be used as a power provider controllers.
or a power consumer. Optional FETs are provided for applications that need to provide
In each of these applications, CCG4 communicates with the power for accessories and cables using VCONN pin of the
Embedded Controller (EC), which manages the Battery Charger Type-C receptacle. VBUS FETs are also used for providing
Controller (BCC) to control the charging and discharging of power over VBUS and for consuming power over VBUS. A
internal battery. It also controls the Data Mux to route the VBUS_DISCHARGE FET controlled by CCG4 device is used to
HighSpeed signals either to the USB chipset (during normal quickly discharge VBUS after the Type-C connection is
mode) or the DisplayPort Chipset (during Alternate Mode).The detached.
SBU, SuperSpeed, and HighSpeed lines are routed directly from
the Display Mux of the notebook to the Type-C receptacle.
Figure 8. CCG4 in a Dual Port Notebook Application using CYPD4225-40LQXIT
HS 2

USB 3.0
SSTX/RX 4
HOST
TX 4

RX 4
MUX
ML_LANE_[0:3]N 4 SBU 2
ML_LANE_[0:3]P 4
DISPLAY PORT
CONTROLLER 1 AUX P/N 2

HPD_P0

I2C_SCL I2C_SDA

VBUS_SINK

49.9KO
4.7 uF 100 KO 4.7 uF
100 KO 2

VBUS_C_CTRL_P0 10 O

100 KO
2

SBU
SSTX/RX
DP/DM
DP/DM
VBUS_SOURCE
VBUS

OPTIONAL VDDIO SUPPLY. CAN SHORT

TO VDDD IN SINGLE SUPPLY SYSTEMS. 49.9KO
100 KO
4.7 uF
5.0V 5.0V 3.3V VDDIO 100 KO

VBUS_P_CTRL_P0 10 O

1µF 1µF 1µF 0.1µF 100 KO

23

31

32

33
8

1
V5V_P1

V5V_P0

VDDD

VDDIO

VCCD

SWD_IO/AR_RST#

2
SWD_CLK/I2C_CFG_EC 200 O
TYPE-C
TO DISPLAY_PORT HPD_P0 18 VBUS_DISCHARGE_P0 10 O
CONTROLLER 1 HPD_P0/GPIO
VBUS RECEPTACLE 1
100 KO 100 KO
TO DISPLAY PORT HPD_P1 30
HPD_P1/GPIO 13 VBUS_MON_P0
CONTROLLER 2 VBUS_MON_P0/GPIO
19 VCONN_MON_P0/GPIO 10 KO 0.1µF
VSEL_2_P0
VSEL_1_P0

14 7 CC2
OVP_TRIP_P0 CC2_P0

VSEL_2_P1 27 9
VSEL_2_P1/GPIO CC1_P0 CC1
DC/DC
OR VDDIO VDDIO
11 VBUS_P_CTRL_P0 330pF
CHARGER AC-DC VBUS_P_CTRL_P0
330pF

SECONDARY 100 KO 10 VBUS_DISCHARGE_P0

XRES VBUS_DISCHARGE_P0 20 GND
(5-20V) 0.1µF
2.2 KO
21 12 VBUS_C_CTRL_P1
CCG4
VSEL_2_P1

OVP_TRIP_P1
VSEL_1_P1

2.2 KO VBUS_C_CTRL_P0
2.2 KO
EMBEDDED 15
I2C_INT_EC
(CYPD4225-40LQXIT)
CONTROLLER 34
17
40-QFN MUX_CTRL_3_P1/GPIO GND
I2C_SCL_SCB0_EC
35
16 MUX_CTRL_2_P1/GPIO
I2C_SDA_SCB0_EC
VSEL_1_P1 4 36
I2C_SCL_SCB1_AR/VSEL_1_P1 MUX_CTRL_1_P1/GPIO

VSEL_1_P0 3 VBUS_C_CTRL_P1
I2C_SDA_SCB1_AR/VSEL_1_P0 VBUS_C_CTRL_P1 38

5 VBUS_P_CTRL_P1
I2C_INT_AR_P0 VBUS_P_CTRL_P1 39
6
I2C_INT_AR_P1 VBUS_DISCHARGE_P1
VBUS_DISCHARGE_P1 40
VDDIO
25
SCL_2/VCONN_MON_P1/GPIO 24
CC2_P1 CC2
2.2 KO 2.2 KO VSEL_2_P0 26
SDA_2/MUX_CTRL_3_P0/VSEL_2_P0
I2C MASTER I2C_SCL 29 22
CC1_P1 CC1
SCL_3/MUX_CTRL_1_P0/GPIO
FOR ALT VBUS
MODE MUX I2C_SDA 28 330pF 330pF
TYPE-C
SDA_3/MUX_CTRL_2_P0/GPIO 100 KO
CONTROL RECEPTACLE 2
37 VBUS_MON_P2
CONNECTED EPAD VBUS_MON_P1
VSS
TO TYPE -C 10 KO 0.1µF
PORT1 or
PORT2

VBUS_SINK
SSTX/RX

DP/DM
DP/DM

VBUS
SBU

49.9KO
100 KO 2
4.7 uF 4.7 uF

2
VBUS_C_CTRL_P1 10 O

100 KO

VBUS (5-20V)
VBUS_SOURCE

49.9KO
100 KO
4.7 uF

VBUS_P_CTRL_P1 10 O

100 KO

200 O

VBUS_DISCHARGE_P1 10 O

100 KO

HS 2

USB 3.0
SSTX/RX 4
HOST
TX 4

RX 4
MUX
ML_LANE_[0:3]N 4
SBU 2
ML_LANE_[0:3]P 4
DISPLAY PORT
CONTROLLER 2 AUX P/N 2

HPD_P1

I2C_SCL I2C_SDA

Document Number: 001-98440 Rev. *M Page 19 of 38

 EZ-PD CCG4

Figure 9. CCG4 in a Single Port Notebook Application using CYPD4125-40LQXIT

HS 2

USB 3.0
SSTX/RX 4 TX 4
HOST

RX 4

MUX SBU 2
ML_LANE_[0:3]N 4
ML_LANE_[0:3]P 4
DISPLAY PORT
CONTROLLER 1 AUX P/N 2

HPD_P0
VBUS_SINK
I2C_SCL I2C_SDA CHARGER

49.9KO 2
4.7 uF 100 KO
100 KO
VBUS_C_CTRL_P0 10 O

100 KO
2
VSEL_2_P0
DC/DC VBUS (5-20V)

SBU

DP/DM
SSTX/RX
DP/DM
OR VBUS_SOURCE
VSEL_1_P0 AC-DC VBUS
SECONDARY
OPTIONAL VDDIO SUPPLY. CAN SHORT
(5-20V) TO VDDD IN SINGLE SUPPLY SYSTEMS. 49.9KO
4.7 uF 100 KO 4.7 uF
5.0V 3.3V VDDIO 100 KO

VBUS_P_CTRL_P0 10 O

1µF 1µF 0.1µF 100 KO

31

32

33
23

8
1 200O

NC

V5V_P0

VDDD

VDDIO

VCCD
SWD_IO/AR_RST#
VBUS_DISCHARGE_P0 10 O
2
SWD_CLK/I2C_CFG_EC
TO DISPLAY_PORT 100 KO TYPE-C
CONTROLLER 1 HPD_P0 18
HPD_P0/GPIO
VBUS RECEPTACLE 1
100 KO
13 VBUS_MON_P0
VBUS_MON_P0/GPIO
19 VCONN_MON__P0/GPIO 10 KO 0.1µF

14 7
OVP_TRIP_P0 CC2_P0 CC2
9
CC1_P0 CC1
VDDIO VDDIO
11 VBUS_P_CTRL_P0 330pF 330pF
VBUS_P_CTRL_P0
100 KO
10 20 VBUS_DISCHARGE_P0
XRES VBUS_DISCHARGE_P0 GND
2.2 KO 0.1µF
21 12 VBUS_C_CTRL_P0
2.2 KO GPIO CCG4 VBUS_C_CTRL_P0
2.2 KO
EMBEDDED 15
I2C_INT_EC (CYPD4125-40LQXIT)
CONTROLLER 40-QFN GPIO
27
17 I2C_SCL_SCB0_EC
30
16 GPIO
I2C_SDA_SCB0_EC
4 34
I2C_SCL_SCB1_AR GPIO
VSEL_1_P0 3 35
I2C_SDA_SCB1_AR/VSEL_1_P0 GPIO

VDDIO 5
I2C_INT_AR_P0 GPIO 36
6
GPIO
GPIO 37
25 38
2.2 KO SCL_2 GPIO
2.2 KO VSEL_2_P0 26
SDA_2/MUX_CTRL_3_P0/VSEL_2_P0 39
I2C_SCL GPIO
I2C MASTER FOR ALT MODE 29
SCL_3/MUX_CTRL_1_P0 40
MUX CONTROL CONNECTED TO I2C_SDA GPIO
28
TYPE-C PORT1 SDA_3/MUX_CTRL_2_P0 24
NC
EPAD
VSS 22
NC

Document Number: 001-98440 Rev. *M Page 20 of 38

 EZ-PD CCG4

Electrical Specifications
Absolute Maximum Ratings
Table 9. Absolute Maximum Ratings[8]
Parameter Description Min Typ Max Unit Details/Conditions
VDDD_MAX Digital supply relative to VSS –0.5 – 6 V Absolute max
V5V_P0 Max supply voltage relative to VSS – – 6 V Absolute max
V5V_P1 Max supply voltage relative to VSS – – 6 V Absolute max
VDDIO_MAX Max supply voltage relative to VSS – – 6 V Absolute max
VGPIO_ABS GPIO voltage –0.5 – VDDIO + 0.5 V Absolute max
IGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute max
IGPIO_injection GPIO injection current, Max for VIH –0.5 – 0.5 mA Absolute max, current
> VDDD, and Min for VIL < VSS injected per pin
ESD_HBM Electrostatic discharge human 2200 – – V –
body model
ESD_CDM Electrostatic discharge charged 500 – – V –
device model
LU Pin current for latch-up –200 – 200 mA –
ESD_IEC_CON Electrostatic discharge 8000 – – V Contact discharge on CC1
IEC61000-4-2 and CC2 pins
ESD_IEC_AIR Electrostatic discharge 15000 – – V Air discharge for pins CC1
IEC61000-4-2 and CC2

Note
8. Usage above the absolute maximum conditions listed in Table 9 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.

Document Number: 001-98440 Rev. *M Page 21 of 38

 EZ-PD CCG4

Device-Level Specifications
All specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V,
except where noted.
Table 10. DC Specifications
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID.PWR#1 VDDD Power supply input voltage 2.7 – 5.5 V UFP applications
SID.PWR#1_A VDDD Power supply input voltage 3.15 – 5.5 V DFP/DRP applications
SID.PWR#26 V5V_P0, Power supply input voltage 4.85 – 5.5 V –
V5V_P1
PWR#13 VDDIO GPIO power supply 1.71 – 5.5 V –
SID.PWR#24 VCCD Output voltage (for core logic) – 1.8 – V –
SID.PWR#15 CEFC External regulator voltage 80 100 120 nF X5R ceramic or better
bypass on VCCD
SID.PWR#16 CEXC Power supply decoupling 0.8 1 – µF X5R ceramic or better
capacitor on VDDD
SID.PWR#27 CEXV Power supply decoupling – 0.1 – µF X5R ceramic or better
capacitor on V5V_P0 and
V5V_P1
Active Mode, VDDD = 2.7 to 5.5 V. Typical values measured at VDD = 3.3 V.
SID.PWR#4 IDD12 Supply current – 10 – mA V5V_P0 and V5V_P1 = 5 V,
TA = 25 °C,
CC I/O IN Transmit or Receive, no
I/O sourcing current, CPU at 24
MHz, two PD ports active
Sleep Mode, VDDD = 2.7 to 5.5 V
SID25A IDD20A I2C wakeup – 2.5 4.0 mA VDDD = 3.3 V, TA = 25 °C, all blocks
WDT ON except CPU are ON, CC I/O ON, no
IMO at 48 MHz I/O sourcing current
Deep Sleep Mode, VDDD = 2.7 to 3.6 V (Regulator on)
SID34 IDD29 VDDD = 2.7 to 3.6 V – 80 – µA VDDD = 3.3 V, TA = 25 °C
I2C wakeup and WDT ON
SID_DS IDD_DS VDDD = 2.7 to 3.6 V – 2.5 – µA Power source = VDDD, Type-C not
CC wakeup ON attached, CC enabled for wakeup,
RP disabled
SID_DS1 IDD_DS1 VDDD = 2.7 to 3.6 V – 100 – µA Power source = VDDD, Type-C not
CC wakeup ON attached, CC enabled for wakeup,
RP and RD connected at 70 ms
intervals by CPU. RP, RD
connection should be enabled for
both PD ports.
XRES Current
SID307 IDD_XR Supply current while XRES – 1 10 µA –
asserted

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 EZ-PD CCG4

Table 11. AC Specifications

Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID.CLK#4 FCPU CPU frequency DC – 48 MHz 3.0 V VDDD 5.5 V
SID.PWR#20 TSLEEP Wakeup from sleep mode – 0 – µs Guaranteed by
characterization
SID.PWR#21 TDEEPSLEEP Wakeup from Deep Sleep mode – – 35 µs 24-MHz IMO. Guaranteed by
characterization.
SID.XRES#5 TXRES External reset pulse width 5 – – µs Guaranteed by
characterization
SYS.FES#1 T_PWR_RDY Power-up to “Ready to accept – 5 25 ms Guaranteed by
I2C / CC command” characterization

I/O
Table 12. I/O DC Specifications
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID.GIO#37 VIH [9] Input voltage HIGH threshold 0.7 × VDDIO – – V CMOS input
SID.GIO#38 VIL Input voltage LOW threshold – – 0.3 × VDDIO V CMOS input
SID.GIO#39 VIH[9] LVTTL input, VDDIO < 2.7 V 0.7× VDDIO – – V –
SID.GIO#40 VIL LVTTL input, VDDIO < 2.7 V – – 0.3 × VDDIO V –
[9] LVTTL input, VDDIO  2.7 V
SID.GIO#41 VIH 2.0 – – V –
SID.GIO#42 VIL LVTTL input, VDDIO  2.7 V – – 0.8 V –
SID.GIO#33 VOH Output voltage HIGH level VDDIO –0.6 – – V IOH = 4 mA at 3 V VDDIO
SID.GIO#34 VOH Output voltage HIGH level VDDIO –0.5 – – V IOH = 1 mA at 1.8 V VDDIO
SID.GIO#35 VOL Output voltage LOW level – – 0.4 V IOL = 4 mA at 1.8 V VDDIO
SID.GIO#36 VOL Output voltage LOW level – – 0.6 V IOL = 8 mA at 3 V VDDIO
SID.GIO#5 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ –
SID.GIO#6 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ –
SID.GIO#16 IIL Input leakage current – – 2 nA 25 °C, VDDIO = 3.0 V
(absolute value)
SID.GIO#17 CIN Input capacitance – – 7 pF –
SID.GIO#43 VHYSTTL Input hysteresis LVTTL 25 40 – mV VDDIO  2.7 V. Guaranteed
by characterization.
SID.GPIO#44 VHYSCMOS Input hysteresis CMOS 0.05 × VDDIO – – mV Guaranteed by
characterization
SID69 IDIODE Current through protection – – 100 µA Guaranteed by
diode to VDDIO/Vss characterization
SID.GIO#45 ITOT_GPIO Maximum total source or sink – – 200 mA Guaranteed by
chip current characterization

Note
9. VIH must not exceed VDDIO + 0.2 V.

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 EZ-PD CCG4

Table 13. I/O AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID70 TRISEF Rise time 2 – 12 ns 3.3-V VDDIO, Cload = 25 pF
SID71 TFALLF Fall time 2 – 12 ns 3.3-V VDDIO, Cload = 25 pF

XRES
Table 14. XRES DC Specifications
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID.XRES#1 VIH Input voltage HIGH threshold 0.7 × VDDIO – – V CMOS input
SID.XRES#2 VIL Input voltage LOW threshold – – 0.3 × VDDIO V CMOS input
SID.XRES#3 CIN Input capacitance – – 7 pF –
SID.XRES#4 VHYSXRES Input voltage hysteresis – – 0.05 × VDDIO mV Guaranteed by
characterization

Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Pulse Width Modulation (PWM) for GPIO Pins
Table 15. PWM AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID.TCPWM.3 TCPWMFREQ Operating frequency – Fc – MHz Fc max = CLK_SYS. Maximum = 48 MHz
SID.TCPWM.4 TPWMENEXT Input trigger pulse width – 2/Fc – ns For all trigger events
SID.TCPWM.5 TPWMEXT Output trigger pulse width – 2/Fc – ns Minimum possible width of Overflow,
Underflow, and CC (Counter equals
Compare value) outputs
SID.TCPWM.5A TCRES Resolution of counter – 1/Fc – ns Minimum time between successive
counts
SID.TCPWM.5B PWMRES PWM resolution – 1/Fc – ns Minimum pulse width of PWM output
SID.TCPWM.5C QRES Quadrature inputs resolution – 1/Fc – ns Minimum pulse width between
quadrature-phase inputs

I2C
Table 16. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID153 FI2C1 Bit rate – – 1 Mbps –

UART
Table 17. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID162 FUART Bit rate – – 1 Mbps –

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 EZ-PD CCG4

SPI
Table 18. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID166 FSPI SPI operating frequency – – 8 MHz –
(Master; 6X oversampling)

Table 19. Fixed SPI Master Mode AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID167 TDMO MOSI valid after SClock – – 15 ns –
driving edge
SID168 TDSI MISO valid before SClock 20 – – ns Full clock, late MISO sampling
capturing edge
SID169 THMO Previous MOSI data hold 0 – – ns Referred to Slave capturing edge
time

Table 20. Fixed SPI Slave Mode AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID170 TDMI MOSI valid before Sclock 40 – – ns –
capturing edge
SID171 TDSO MISO valid after Sclock driving – – 48 + (3 × ns TSCB = TCPU =
edge TSCB) 1/24 MHz
SID171A TDSO_EXT MISO valid after Sclock driving – – 48 ns –
edge in Ext Clk mode
SID172 THSO Previous MISO data hold time 0 – – ns –
SID172A TSSELSCK SSEL valid to first SCK valid edge 100 – – ns –

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 EZ-PD CCG4

Memory
Table 21. Flash AC Specifications
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID.MEM#4 TROWWRITE[10] Row (block) write time (erase and – – 20 ms –
program)
SID.MEM#3 TROWERASE[10] Row erase time – – 13 ms –
SID.MEM#8 TROWPROGRAM[10] Row program time after erase – – 7 ms –
SID178 TBULKERASE [10] Bulk erase time (128 KB) – – 35 ms –
SID180 TDEVPROG[10] Total device program time – – 25 seconds Guaranteed by
characterization
SID.MEM#6 FEND Flash endurance 100K – – cycles Guaranteed by
characterization
SID182 FRET1 Flash retention. TA  55 °C, 100 K 20 – – years Guaranteed by
P/E cycles characterization
SID182A FRET2 Flash retention. TA  85 °C, 10 K 10 – – years Guaranteed by
P/E cycles characterization
Note
10. It can take as much as 20 milliseconds to write to flash. During this time the device should not be reset, or flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.

System Resources
Power-on-Reset (POR) with Brown Out
Table 22. Imprecise Power On Reset (PRES)
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID185 VRISEIPOR Rising trip voltage 0.80 – 1.50 V Guaranteed by
characterization
SID186 VFALLIPOR Falling trip voltage 0.75 – 1.4 V Guaranteed by
characterization

Table 23. Precise Power On Reset (POR)

Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID190 VFALLPPOR BOD trip voltage in active and 1.48 – 1.62 V Guaranteed by
sleep modes characterization
SID192 VFALLDPSLP BOD trip voltage in deep sleep 1.1 – 1.5 V Guaranteed by
characterization

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 EZ-PD CCG4

SWD Interface
Table 24. SWD Interface Specifications
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID.SWD#1 F_SWDCLK1 3.3 V  VDDIO  5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU clock
frequency
SID.SWD#2 F_SWDCLK2 1.8 V  VDDIO  3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU clock
frequency
SID.SWD#3 T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns Guaranteed by
characterization
SID.SWD#4 T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T – – ns Guaranteed by
characterization
SID.SWD#5 T_SWDO_VALID T = 1/f SWDCLK – – 0.5 × T ns Guaranteed by
characterization
SID.SWD#6 T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns Guaranteed by
characterization

Internal Main Oscillator

Table 25. IMO AC Specifications
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID.CLK#13 FIMOTOL Frequency variation at 24, 36, and – – ±2 % –
48 MHz (trimmed)
SID226 TSTARTIMO IMO startup time – – 7 µs –
SID229 TJITRMSIMO RMS jitter at 48 MHz – 145 – ps –
FIMO – IMO frequency 24 – 48 MHz –

Internal Low-Speed Oscillator

Table 26. ILO AC Specifications
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID234 TSTARTILO ILO startup time – – 2 ms Guaranteed by
characterization
SID236 TILODUTY ILO duty cycle 40 50 60 % Guaranteed by
characterization
SID.CLK#5 FILO ILO frequency 20 40 80 kHz –

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 EZ-PD CCG4

Power Down
Table 27. PD DC Specifications
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID.PD.1 Rp_std DFP CC termination for default USB 64 80 96 µA –
Power
SID.PD.2 Rp_1.5A DFP CC termination for 1.5A power 166 180 194 µA –
SID.PD.3 Rp_3.0A DFP CC termination for 3.0A power 304 330 356 µA –
SID.PD.4 Rd UFP CC termination 4.59 5.1 5.61 kΩ –
SID.PD.5 Rd_DB UFP Dead Battery CC termination on 4.08 5.1 6.12 kΩ All supplies forced to 0 V and
CC1 and CC2 1.0 V applied at CC1 or CC2.
Applicable for DRP applications
only.
SID.PD.15 Vdrop_V5V_CC1 Voltage drop from V5V_P0 and – – 100 mV –
V5V_P1 pins to CC1 pin while
sourcing 215 mA.
CC1 and CC2 pins of Port0 and
Port1 are not short circuit protected.
Max sourcing current allowed is
500 mA.
SID.PD.16 Vdrop_V5V_CC2 Voltage drop from V5V_P0 and – – 100 mV –
V5V_P1 pins to CC2 pin while
sourcing 215 mA.
CC1 and CC2 pins of Port0 and
Port1 are not short circuit protected.
Max allowed sourcing current is
500 mA.

Analog to Digital Converter

Table 28. ADC DC Specifications
Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID.ADC.1 Resolution ADC resolution – 8 – bits –
SID.ADC.2 INL Integral nonlinearity –1.5 – 1.5 LSB –
SID.ADC.3 DNL Differential nonlinearity –2.5 – 2.5 LSB –
SID.ADC.4 Gain Error Gain error –1.0 – 1.0 LSB –

Table 29. ADC AC Specifications

Spec ID Parameter Description Min Typ Max Unit Details/Conditions
SID.ADC.5 SLEW_Max Rate of change of sampled voltage – – 3 V/ms –
signal

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 EZ-PD CCG4

Ordering Information
The EZ-PD CCG4 part numbers and features are listed in Table 30.
Table 30. EZ-PD CCG4 Ordering Information
Type-C PD Dead Battery Termination
Part Number Application Ports TCPWM Spec# Termination Resistor Role Package

CYPD4125-40LQXIT Notebooks, desktops 1 4 PD2.0 Yes RP[11], RD[12], RD-DB[12] DRP 40-pin QFN
[11] [12] [12]
CYPD4225-40LQXIT Notebooks, desktops 2 4 PD2.0 Yes RP , RD , RD-DB DRP 40-pin QFN
CYPD4126-40LQXIT Notebooks, desktops 1 2 PD3.0 Yes RP[11], RD[12], RD-DB[12] DRP 40-pin QFN
CYPD4226-40LQXIT Notebooks, desktops 2 2 PD3.0 Yes RP [11], RD [12], RD-DB [12] DRP 40-pin QFN
CYPD4236-40LQXIT Docking station 2 2 PD3.0 No RP[11], RD[12] DRP 40-pin QFN
CYPD4236-40LQXQT Dual Port Power Adapter 2 2 PD3.0 No RP[11], RD[12] DFP 40-pin QFN
CYPD4126-24LQXIT Notebooks, desktops 1 2 PD3.0 Yes RP [11], RD [12], RD-DB [12] DRP 24-pin QFN
CYPD4136-24LQXIT Docking station 1 2 PD3.0 No RP[11], RD[12] DRP 24-pin QFN
[11] [12] [12]
CYPD4225A0-33FNXIT Notebooks, desktops 2 4 PD2.0 Yes RP , RD , RD-DB DRP 33-ball CSP

Ordering Code Definitions

CY PD 4 1/2 2/3 2/3 XX - XX XX X X XX X
T = Tape and reel

ES (Optional Field): Pre-production Engineering Samples only.

Temperature Range: I = Industrial (-40 oC to 85 oC);
Q = Extended Industrial (-40 oC to 105 oC)
X = Pb-free

Package Type: FN = CSP

Number of pins in the package

Si Rev = A0 (Optional Field)

Device Role: Unique combination of role and termination:
X = 5 or 6
Feature: Unique Applications
2 = Notebooks, desktops; 3 = Docking station

Number of Type-C Ports: 1 = 1 Port, 2 = 2 Ports

Product Type: 4 = Fourth Generation Product Family, CCG4

Marketing Code: PD = Power Delivery product family

Company ID: CY = Cypress

Notes
11. Termination resistor denoting a downstream facing port.
12. Termination resistor denoting an accessory or upstream facing port.

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 EZ-PD CCG4

Packaging
Table 31. Package Characteristics
Parameter Description Conditions Min Typ Max Unit
TA Operating ambient temperature – –40 25 85 °C
TJ Operating junction temperature – –40 – 100 °C
TJA Package JA (40-pin QFN) – – 31 – °C/W
TJC Package JC (40-pin QFN) – – 29 – °C/W
TJA Package JA (24-pin QFN) – – 22 – °C/W
TJC Package JC (24-pin QFN) – – 29 – °C/W
TJA Package JA (33-ball CSP) – – 24 – °C/W
TJC Package JC (33-ball CSP) – – 1 – °C/W

Table 32. Solder Reflow Peak Temperature

Package Maximum Peak Temperature Maximum Time within 5 °C of Peak Temperature
24-pin QFN 260 °C 30 seconds
40-pin QFN 260 °C 30 seconds
33-ball CSP 260 °C 30 seconds

Table 33. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package MSL
24-pin QFN MSL 3
40-pin QFN MSL 3
33-ball CSP MSL 1

Figure 10. 40-Pin QFN (6 × 6 × 0.6 mm), LR40A/LQ40A 4.6 × 4.6 E-PAD (Sawn) Package Outline, 001-80659

001-80659 *A

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 EZ-PD CCG4

Figure 11. 24-pin QFN Package Outline

002-16934 *C

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 EZ-PD CCG4

Figure 12. 33-ball CSP Package Outline

NOTES:
DIMENSIONS
SYMBOL 1. ALL DIMENSIONS ARE IN MILLIMETERS.
MIN. NOM. MAX. 2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

A - - 0.514 3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.

- - 4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

A1 0.169
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
D 2.443 BSC
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
E 2.510 BSC SIZE MD X ME.

D1 2.000 BSC 5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A

E1 2.078 BSC PLANE PARALLEL TO DATUM C.

11 6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
MD
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
ME 7
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
N 33 "SD" OR "SE" = 0.
• ••• 0.235 0.265 0.295 WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
eD 0.40 BSC
7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
eE 0.693 BSC
METALIZED MARK, INDENTATION OR OTHER MEANS.
eDs / eEs 0.40 BSC 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
SD / SE 0.00 BSC
9. JEDEC SPECIFICATION NO. REF. : N/A. 002-28711 **
TITLE
PACKAGE OUTLINE, 33 BALL WLCSP

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 EZ-PD CCG4

Acronyms Table 34. Acronyms Used in this Document (continued)

Table 34. Acronyms Used in this Document Acronym Description

opamp operational amplifier
Acronym Description
OCP overcurrent protection
ADC analog-to-digital converter
OVP overvoltage protection
API application programming interface
PCB printed circuit board
Arm® advanced RISC machine, a CPU architecture
PD power delivery
CC configuration channel
PGA programmable gain amplifier
CPU central processing unit
PHY physical layer
cyclic redundancy check, an error-checking
CRC
protocol POR power-on reset
CS current sense PRES precise power-on reset
DFP downstream facing port PSoC® Programmable System-on-Chip™
digital input/output, GPIO with only digital PWM pulse-width modulator
DIO
capabilities, no analog. See GPIO.
RAM random-access memory
DRP dual role port
RISC reduced-instruction-set computing
electrically erasable programmable read-only
EEPROM RMS root-mean-square
memory
RTC real-time clock
a USB cable that includes an IC that reports cable
EMCA characteristics (e.g., current rating) to the Type-C RX receive
ports
SAR successive approximation register
EMI electromagnetic interference
SCL I2C serial clock
ESD electrostatic discharge
SDA I2C serial data
FPB flash patch and breakpoint
S/H sample and hold
FS full-speed
Serial Peripheral Interface, a communications
SPI
GPIO general-purpose input/output protocol
IC integrated circuit SRAM static random access memory
IDE integrated development environment SWD serial wire debug, a test protocol
I2C, or IIC Inter-Integrated Circuit, a communications protocol TX transmit
ILO internal low-speed oscillator, see also IMO a new standard with a slimmer USB connector and
Type-C a reversible cable, capable of sourcing up to 100 W
IMO internal main oscillator, see also ILO
of power
I/O input/output, see also GPIO
Universal Asynchronous Transmitter Receiver, a
UART
LVD low-voltage detect communications protocol
LVTTL low-voltage transistor-transistor logic USB Universal Serial Bus
MCU microcontroller unit USB input/output, CCG4 pins used to connect to a
USBIO
USB port
NC no connect
XRES external reset I/O pin
NMI nonmaskable interrupt
NVIC nested vectored interrupt controller

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 EZ-PD CCG4

Document Conventions Table 35. Units of Measure (continued)

Symbol Unit of Measure
Units of Measure
µV microvolt
Table 35. Units of Measure
µW microwatt
Symbol Unit of Measure
mA milliampere
°C degrees Celsius
ms millisecond
Hz hertz
mV millivolt
KB 1024 bytes
nA nanoampere
kHz kilohertz
ns nanosecond
k kilo ohm
 ohm
Mbps megabits per second
pF picofarad
MHz megahertz
ppm parts per million
M mega-ohm
ps picosecond
Msps megasamples per second
s second
µA microampere
sps samples per second
µF microfarad
V volt
µs microsecond

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 EZ-PD CCG4

References and Links to Applications Application Notes

Collaterals ■ AN96527 - Designing USB Type-C Products Using Cypress’s
CCG1 Controllers
Knowledge Base Articles
■ AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™
■ Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and CCG2
CCG4 - KBA210740
■ AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2
■ Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™
CCG4 Using PSoC® Programmer and MiniProg3 - KBA96477 ■ AN210403 - Hardware Design Guidelines for Dual Role Port
Applications Using EZ-PD™ USB Type-C Controllers
■ CCGX Frequently Asked Questions (FAQs) - KBA97244
■ AN210771 - Getting Started with EZ-PD™ CCG4
■ Handling Precautions for CY4501 CCG1 DVK - KBA210560
Reference Designs
■ Cypress EZ-PD™ CCGx Hardware - KBA204102
■ Difference between USB Type-C and USB-PD - KBA204033 ■ EZ-PD™ CCG2 Electronically Marked Cable Assembly
(EMCA) Paddle Card Reference Design
■ CCGx Programming Methods - KBA97271
■ EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution
■ Getting started with Cypress USB Type-C Products -
KBA04071 ■ CCG1 USB Type-C to DisplayPort Cable Solution
■ Type-C to DisplayPort Cable Electrical Requirements ■ CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution
■ Dead Battery Charging Implementation in USB Type-C ■ EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution
Solutions - KBA97273
■ CCG1 Electronically Marked Cable Assembly (EMCA) Paddle
■ Termination Resistors Required for the USB Type-C Connector Card Reference Design
– KBA97180
■ CCG1 USB Type-C to Legacy USB Device Cable Paddle Card
■ VBUS Bypass Capacitor Recommendation for Type-C Cable Reference Schematics
and Type-C to Legacy Cable/Adapter Assemblies – KBA97270
■ EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle
■ Need for Regulator and Auxiliary Switch in Type-C to
DisplayPort (DP) Cable Solution - KBA97274 ■ EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution
■ Need for a USB Billboard Device in Type-C Solutions – ■ CCG2 20W Power Adapter Reference Design
KBA97146
■ CCG2 18W Power Adapter Reference Design
■ CCG1 Devices in Type-C to Legacy Cable/Adapter Assemblies
– KBA97145 ■ EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference
Design Kit
■ Cypress USB Type-C Controller Supported Solutions –
KBA97179 Kits
■ Termination Resistors for Type-C to Legacy Ports – KBA97272 ■ CY4501 CCG1 Development Kit
■ Handling Instructions for CY4502 CCG2 Development Kit – ■ CY4502 EZ-PD™ CCG2 Development Kit
KBA97916
■ CY4531 EZ-PD CCG3 Evaluation Kit
■ Thunderbolt™ Cable Application Using CCG3 Devices -
KBA210976 ■ CY4541 EZ-PD™ CCG4 Evaluation Kit
■ Power Adapter Application Using CCG3 Devices - KBA210975 Datasheets
■ Methods to Upgrade Firmware on CCG3 Devices - KBA210974
■ CCG1 Datasheet: USB Type-C Port Controller with Power
■ Device Flash Memory Size and Advantages - KBA210973 Delivery
■ Applications of EZ-PD™ CCG4 - KBA210739 ■ CYPD1120 Datasheet: USB Power Delivery Alternate Mode
Controller on Type-C
■ CCG2: USB Type-C Port Controller Datasheet
■ CCG3: USB Type-C Controller Datasheet

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 EZ-PD CCG4

Document History Page

Document Title: EZ-PD CCG4, USB Type-C Port Controller
Document Number: 001-98440
Submission
Revision ECN Date Description of Change

** 4921014 09/24/2015 New data sheet.

*A 4999504 11/03/2015 Updated Pinouts:
Updated Table 1.
Updated Table 2.
Updated Figure 3.
Updated Figure 4.
Updated Application Diagrams:
Updated Figure 8.
Updated Figure 9.
Updated Electrical Specifications:
Updated Absolute Maximum Ratings:
Updated Table 9.
Updated Device-Level Specifications:
Updated Table 10.
Updated Digital Peripherals:
Updated SPI:
Updated Table 20.
Updated System Resources:
Updated Internal Main Oscillator:
Updated Table 25.
*B 5049109 12/14/2015 Updated Electrical Specifications:
Updated Device-Level Specifications:
Updated Table 10.
Updated System Resources:
Updated Analog to Digital Converter:
Updated Table 28.
*C 5141544 03/02/2016 Updated Features:
Updated Low-Power Operation:
Replaced “Sleep: 2 mA” with “Sleep: 2.5 mA”.
Updated Pinouts:
Updated Table 1:
Updated details in “Description” column corresponding to pins 34, 5, and 10.
Updated Table 2:
Updated details in “Description” column corresponding to pins 5, and 10.
Updated Application Diagrams:
Updated Figure 8.
Updated Figure 9.
Updated Electrical Specifications:
Updated Digital Peripherals:
Updated I2C:
Removed table “Fixed I2C DC Specifications”.
Updated UART:
Removed table “Fixed UART DC Specifications”.
Updated SPI:
Removed table “Fixed SPI DC Specifications”.
Updated System Resources:
Updated Internal Main Oscillator:
Removed table “IMO DC Specifications”.
Updated Internal Low-Speed Oscillator:
Removed table “ILO DC Specifications”.
Updated copyright information.
*D 5290129 05/31/2016 Updated EZ-PD CCG4 Block Diagram:
Updated Figure 1.
Updated Functional Overview:
Updated USB-PD Subsystem (SS):
Updated description (Updated to include support for PD 3.0 features).
Updated Table 33.
*E 5307418 06/14/2016 Added Available Firmware and Software Tools.
Updated Application Diagrams:
Added description (Added descriptive notes).
Added References and Links to Applications Collaterals.
Updated Cypress logo and copyright information.

Document Number: 001-98440 Rev. *M Page 36 of 38

 EZ-PD CCG4

Document History Page (continued)

Document Title: EZ-PD CCG4, USB Type-C Port Controller
Document Number: 001-98440
Revision ECN Submission Description of Change
Date
*F 5669709 03/30/2017 Changed status from Preliminary to Final.
Updated Electrical Specifications:
Updated Device-Level Specifications:
Updated Table 10:
Changed typical value of IDD29 parameter from 60 µA to 80 µA corresponding to Condition “VDDD = 3.3
V, TA = 25 °C”.
Updated Ordering Information:
Updated Table 30:
Updated part numbers.
Updated to new template.
*G 5830717 07/24/2017 Updated Pinouts:
Added Table 7.
Added Figure 5.
Updated Ordering Information:
Updated Table 30:
Updated part numbers.
Updated Packaging:
Added spec 002-16934 *A.
Completing Sunset Review.
*H 5899958 09/29/2017 Updated Pinouts:
Updated Table (Updated caption only).
Updated Table 2 (Updated caption only).
Updated Figure 3 (Updated caption only).
Updated Figure 4 (Updated caption only).
Updated Electrical Specifications:
Updated Device-Level Specifications:
Updated Table 10:
Changed minimum value of VDDD parameter from 3 V to 3.15 V corresponding to Test Condition
“DFP/DRP applications”.
*I 5963293 11/10/2017 Updated Ordering Information:
No change in part numbers.
Updated Ordering Code Definitions:
Updated details under “Device Role”.
*J 6045099 01/25/2018 Updated Electrical Specifications:
Updated Device-Level Specifications:
Updated I/O:
Updated Table 12:
Changed maximum value of VOL parameter from 0.6 V to 0.4 V corresponding to Test Condition “IOL =
4 mA at 1.8 V VDDIO”.
Updated to new template.
*K 6217334 06/26/2018 Updated Ordering Code Definitions.
*L 6730730 11/15/2019 Changed document status from Final to Preliminary.
Updated Features.
Updated Table 1 through Table 7 and Table 31 through Table 33.
Updated Figure 3 and Figure 4.
Added CY MPN “CYPD4225A0-33FNXIT” to Table 30.
Added Table 8 for 33-ball CSP part.
Added Figure 6 for 33-ball CSP part.
Added Figure 12 for 33-ball CSP part.
Updated Ordering Code Definitions.
Updated spec 002-16934 *B in Packaging.
Updated SCB nomenclatures from SCB1 thru SCB4 to SCB0 thru SCB3 across the entire document.
Updated Port 1 and Port 2 nomenclatures to Port 0 and Port 1 across the entire document.
*M 7037701 12/08/2020 Removed Preliminary status.
Updated Features.
Added CY MPN “CYPD4236-40LQXQT” to Table 30.
Updated Table 31.
Updated Ordering Code Definitions.
Updated Figure 11 in Packaging (spec 002-16934 *B to *C).
Updated Sales, Solutions, and Legal Information.

Document Number: 001-98440 Rev. *M Page 37 of 38

 EZ-PD CCG4

Sales, Solutions, and Legal Information

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Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB
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Document Number: 001-98440 Rev. *M Revised December 8, 2020 Page 38 of 38