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Dec To Display

VHDL Decodificador3_8 to display

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tevadal456
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8 views1 page

Dec To Display

VHDL Decodificador3_8 to display

Uploaded by

tevadal456
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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----------------------------------------------------------------------------------

-- Company:
-- Engineer:
--
-- Create Date: 11.10.2024 09:49:14
-- Design Name:
-- Module Name: decToDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decToDisplay is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (0 to 6));
end decToDisplay;

architecture Behavioral of decToDisplay is


signal tmp : std_logic_vector(0 to 6);

begin
with a select
tmp<=
"0110000" when "0001",
"1101101" when "0010",
"1111001" when "0011",
"0110011" when "0100",
"1011011" when "0101",
"1011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"11100111" when "1001",
"0000000" when others;

y<=tmp;

end Behavioral;

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