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Minority

VHDL minority

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tevadal456
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8 views1 page

Minority

VHDL minority

Uploaded by

tevadal456
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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----------------------------------------------------------------------------------

-- Company:
-- Engineer:
--
-- Create Date: 11.10.2024 08:51:01
-- Design Name:
-- Module Name: minority - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity minority is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
z : out STD_LOGIC);
end minority;

architecture Behavioral of minority is

begin
Z <= ((not A) and (not B)) or ((not A) and (not C)) or ((not B) and (not C));

end Behavioral;

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