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Experiment 6 DCLD Lab

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Neeraj Kumar
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20 views7 pages

Experiment 6 DCLD Lab

Uploaded by

Neeraj Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Experiment: 6

Student Name: Neeraj Kumar Baidya UID: 20BCA1455


Branch: BCA Section/Group: 4/B
st
Semester: 1 Date of Performance:08/01/2021
Subject Name: DIGITAL CIRCUIT AND LOGIC DESIGN LAB
Subject Code: 20CAP115

1. Aim/Overview of the practical:

a) Implement Half adder using NOR gate on Breadboard.

b) Implement Full adder using NAND gate on Breadboard.

2. Task to be done:

a) Implement Half adder using NOR gate on Breadboard.

b) Implement Full adder using NAND gate on Breadboard.

3. Hardware Required:
(Instructions: Components used in circuits)
(a).
1------ Coin cell 3V battery
1-------Breadboard
1-------DIP SWITCH
1-------Blue led
1-------Yellow Led
2-------7402 IC

1
(b).
1------- Coin cell 3V battery
1------- Breadboard
1------- DIP SWITCH
1------- Blue Led
1------- Yellow Led
3------- 7400 IC

4. Steps for experiment/practical:


(a).
A and B both are high it generates a carry.

A=1, B=0, it gives sum.

2
If A=0, B=1 it also gives sum.

(b).

A=1, B and C are low.

A & B are low and C=1.

A & C are low and B is high.

3
A, B and C are low.

A, B and C all are high.

A & B are high and C is low.

4
A is low rest of all are high.

A & C are high and B is low.

5. Observations:

(a). It works correctly as half adder if we use NOR GATES to implement this and 7 NOR
GATES are used .

(b). To implement full adder using NAND GATES we have to use 3 IC's for 9 Nand gates.

5
6. Calculations:

(Instructions: Paste the Complete truth table of the circuits)


(a).
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

(b).

A B C Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

7. Output:
6
(Instructions: Mentions on which points LEDs will glow in figure 1)

(Example: The led will glow on input 000)

(a). The output for sum is (01,10) and for carry (11).

(b). The output for sum (001,010,100,111) and for carry (011,101,110,111).

9. Learning outcomes (What I have learnt):

1. Half adder.

2. Full adder.

3. Half adder via NOR GATE.

4. Full adder via NAND GATE.

Evaluation Grid (To be created as per the SOP and Assessment guidelines by the faculty):

Sr. No. Parameters Marks Obtained Maximum Marks


1. Circuits Design
2. Truth table for AIM 1
3. Truth table for AIM 2

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