FM24C16B

16-Kbit (2K × 8) Serial (I2C) F-RAM

16-Kbit (2K × 8) Serial (I2C) F-RAM

Features Functional Description

■ 16-Kbit ferroelectric random access memory (F-RAM) logically The FM24C16B is a 16-Kbit nonvolatile memory employing an
organized as 2K × 8 advanced ferroelectric process. A ferroelectric random access
14
❐ High-endurance 100 trillion (10 ) read/writes memory or F-RAM is nonvolatile and performs reads and writes
❐ 151-year data retention (See Data Retention and Endurance similar to a RAM. It provides reliable data retention for 151 years
on page 10) while eliminating the complexities, overhead, and system-level
❐ NoDelay™ writes reliability problems caused by EEPROM and other nonvolatile
❐ Advanced high-reliability ferroelectric process memories.

■ Fast 2-wire Serial interface (I2C) Unlike EEPROM, the FM24C16B performs write operations at
bus speed. No write delays are incurred. Data is written to the
❐ Up to 1-MHz frequency
2 memory array immediately after each byte is successfully
❐ Direct hardware replacement for serial (I C) EEPROM
transferred to the device. The next bus cycle can commence
❐ Supports legacy timings for 100 kHz and 400 kHz
without the need for data polling. In addition, the product offers
■ Low power consumption substantial write endurance compared with other nonvolatile
❐ 100 A active current at 100 kHz memories. Also, F-RAM exhibits much lower power during writes
❐ 4 A (typ) standby current than EEPROM since write operations do not require an internally
elevated power supply voltage for write circuits. The FM24C16B
■ Voltage operation: VDD = 4.5 V to 5.5 V is capable of supporting 1014 read/write cycles, or 100 million
■ Industrial temperature: –40 C to +85 C times more write cycles than EEPROM.
■ 8-pin small outline integrated circuit (SOIC) package These capabilities make the FM24C16B ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
■ Restriction of hazardous substances (RoHS) compliant Examples range from data logging, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of EEPROM can cause data loss. The
combination of features allows more frequent data writing with
less overhead for the system.
The FM24C16B provides substantial benefits to users of serial
(I2C) EEPROM as a hardware drop-in replacement. The device
specifications are guaranteed over an industrial temperature
range of –40 C to +85 C.
For a complete list of related documentation, click here.

Logic Block Diagram

Address 2Kx8
Counter
Latch F-RAM Array
11

Serial to Parallel
SDA Data Latch
Converter
8

SCL
Control Logic
WP

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-84450 Rev. *M Revised December 5, 2018
 FM24C16B

Contents
Pinout ................................................................................ 3 Capacitance .................................................................... 10
Pin Definitions .................................................................. 3 Thermal Resistance ........................................................ 10
Functional Overview ........................................................ 4 AC Test Loads and Waveforms ..................................... 10
Memory Architecture ........................................................ 4 AC Test Conditions ........................................................ 10
I2C Interface ...................................................................... 4 AC Switching Characteristics ....................................... 11
STOP Condition (P) ..................................................... 4 Power Cycle Timing ....................................................... 12
START Condition (S) ................................................... 4 Ordering Information ...................................................... 13
Data/Address Transfer ................................................ 5 Ordering Code Definitions ......................................... 13
Acknowledge/No-acknowledge ................................... 5 Package Diagram ............................................................ 14
Slave Device Address ................................................. 6 Acronyms ........................................................................ 15
Addressing Overview (Word Address) ........................ 6 Document Conventions ................................................. 15
Data Transfer .............................................................. 6 Units of Measure ....................................................... 15
Memory Operation ............................................................ 6 Document History Page ................................................. 16
Write Operation ........................................................... 6 Sales, Solutions, and Legal Information ...................... 18
Read Operation ........................................................... 7 Worldwide Sales and Design Support ....................... 18
Endurance ......................................................................... 8 Products .................................................................... 18
Maximum Ratings ............................................................. 9 PSoC®Solutions ....................................................... 18
Operating Range ............................................................... 9 Cypress Developer Community ................................. 18
DC Electrical Characteristics .......................................... 9 Technical Support ..................................................... 18
Data Retention and Endurance ..................................... 10

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 FM24C16B

Pinout
Figure 1. 8-pin SOIC pinout

NC 1 8 VDD

NC 2 Top View 7 WP
not to scale
NC 3 6 SCL

VSS 4 5 SDA

Pin Definitions
Pin Name I/O Type Description
SDA Input/Output Serial Data/Address. This is a bi-directional pin for the I2C interface. It is open-drain and is intended
to be wire-AND’d with other devices on the I2C bus. The input buffer incorporates a Schmitt trigger for
noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor
is required.
SCL Input Serial Clock. The serial clock pin for the I2C interface. Data is clocked out of the device on the falling
edge, and into the device on the rising edge.
WP Input Write Protect. When tied to VDD, addresses in the entire memory map will be write-protected. When
WP is connected to ground, all addresses are write enabled. This pin is pulled down internally.
VSS Power supply Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.

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 FM24C16B

Functional Overview operation is complete. This is explained in more detail in the

interface section.
The FM24C16B is a serial F-RAM memory. The memory array Note that the FM24C16B contains no power management
is logically organized as 2,048 × 8 bits and is accessed using an circuits other than a simple internal power-on reset. It is the
industry-standard I2C interface. The functional operation of the user’s responsibility to ensure that VDD is within data sheet
F-RAM is similar to serial (I2C) EEPROM. The major difference tolerances to prevent incorrect operation.
between the FM24C16B and a serial (I2C) EEPROM with the
same pinout is the F-RAM's superior write performance, high I2C Interface
endurance, and low power consumption.
The FM24C16B employs a bi-directional I2C bus protocol using
Memory Architecture few pins or board space. Figure 2 illustrates a typical system
configuration using the FM24C16B in a microcontroller-based
When accessing the FM24C16B, the user addresses 2K system. The industry standard I2C bus is familiar to many users
locations of eight data bits each. These eight data bits are shifted but is described in this section.
in or out serially. The addresses are accessed using the I2C
By convention, any device that is sending data onto the bus is
protocol, which includes a slave address (to distinguish other the transmitter while the target device for this data is the receiver.
non-memory devices), a row address, and a segment address. The device that is controlling the bus is the master. The master
The row address consists of 8-bits that specify one of the 256 is responsible for generating the clock signal for all operations.
rows. The 3-bit segment address specifies one of the 8 segments Any device on the bus that is being controlled is a slave. The
within each row. The complete address of 11-bits specifies each FM24C16B is always a slave device.
byte address uniquely. The bus protocol is controlled by transition states in the SDA and
The access time for the memory operation is essentially zero, SCL signals. There are four conditions including START, STOP,
beyond the time needed for the serial protocol. That is, the data bit, or acknowledge. Figure 3 on page 5 and Figure 4 on
memory is read or written at the speed of the I2C bus. Unlike a page 5 illustrates the signal conditions that specify the four
serial (I2C) EEPROM, it is not necessary to poll the device for a states. Detailed timing diagrams are shown in the electrical
ready condition because writes occur at bus speed. By the time specifications section.
a new bus transaction can be shifted into the device, a write

Figure 2. System Configuration using Serial (I2C) nvSRAM

V DD

RPmin = (VDD - VOLmax) / IOL

RPmax = tr / (0.8473 * Cb)

SCL
Microcontroller

SDA

SCL SDA SCL SDA

FM24C16B Other Slave Device

STOP Condition (P) START Condition (S)

A STOP condition is indicated when the bus master drives SDA A START condition is indicated when the bus master drives SDA
from LOW to HIGH while the SCL signal is HIGH. All operations from HIGH to LOW while the SCL signal is HIGH. All commands
using the FM24C16B should end with a STOP condition. If an should be preceded by a START condition. An operation in
operation is in progress when a STOP is asserted, the operation progress can be aborted by asserting a START condition at any
will be aborted. The master must have control of SDA in order to time. Aborting an operation using the START condition will ready
assert a STOP condition. the FM24C16B for a new operation.
If during operation the power supply drops below the specified
VDD minimum, the system should issue a START condition prior
to performing another operation.

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 FM24C16B

Figure 3. START and STOP Conditions

full pagewidth

SDA SDA

SCL SCL
S P

START Condition STOP Condition

Figure 4. Data Transfer on the I2C Bus

handbook, full pagewidth P
SDA

MSB Acknowledgement Acknowledgement S

signal from slave signal from receiver

SCL S
S 1 2 7 8 9 1 2 3 4-8 9 or
P
ACK ACK
START STOP or
condition Byte complete START
condition

Data/Address Transfer The receiver would fail to acknowledge for two distinct reasons.
All data transfers (including addresses) take place while the SCL First is that a byte transfer fails. In this case, the no-acknowledge
signal is HIGH. Except under the two conditions described ceases the current operation so that the device can be
above, the SDA signal should not change while SCL is HIGH. addressed again. This allows the last byte to be recovered in the
event of a communication error.
Acknowledge/No-acknowledge Second and most common, the receiver does not acknowledge
The acknowledge takes place after the 8th data bit has been to deliberately end an operation. For example, during a read
transferred in any transaction. During this state the transmitter operation, the FM24C16B will continue to place data onto the
should release the SDA bus to allow the receiver to drive it. The bus as long as the receiver sends acknowledges (and clocks).
receiver drives the SDA signal LOW to acknowledge receipt of When a read operation is complete and no more data is needed,
the byte. If the receiver does not drive SDA LOW, the condition the receiver must not acknowledge the last byte. If the receiver
is a no-acknowledge and the operation is aborted. acknowledges the last byte, this will cause the FM24C16B to
attempt to drive the bus on the next clock while the master is
sending a new command such as STOP.

Figure 5. Acknowledge on the I2C Bus

handbook, full pagewidth

DATA OUTPUT
BY MASTER

No Acknowledge
DATA OUTPUT
BY SLAVE
Acknowledge

SCL FROM 1 2 8 9
MASTER
S
Clock pulse for
START acknowledgement
Condition

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 FM24C16B

Slave Device Address sequential byte. If the acknowledge is not sent, the FM24C16B
will end the read operation. For a write operation, the FM24C16B
The first byte that the FM24C16B expects after a START
will accept 8 data bits from the master then send an
condition is the slave address. As shown in Figure 6, the slave
acknowledge. All data transfer occurs MSB (most significant bit)
address contains the device type, the page of memory to be
first.
accessed, and a bit that specifies if the transaction is a read or
a write.
Memory Operation
Bits 7–4 are the device type and should be set to 1010b for the
FM24C16B. These bits allow other function types to reside on The FM24C16B is designed to operate in a manner very similar
the I2C bus within an identical address range. Bits 3–1 are the to other I2C interface memory products. The major differences
page select. It specifies the 256-byte block of memory that is result from the higher performance write capability of F-RAM
targeted for the current operation. Bit 0 is the read/write bit technology. These improvements result in some differences
(R/W). R/W = ‘1’ indicates a read operation and R/W = ‘0’ between the FM24C16B and a similar configuration EEPROM
indicates a write operation. during writes. The complete operation for both writes and reads
is explained below.
Figure 6. Memory Slave Device Address Write Operation
MSB
handbook, halfpage LSB All writes begin with a slave address, then a word address. The
bus master indicates a write operation by setting the LSB of the
1 0 1 0 A2 A1 A0 R/W
slave address (R/W bit) to a ‘0’. After addressing, the bus master
sends each byte of data to the memory and the memory
Slave ID Page Select generates an acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range is reached
Addressing Overview (Word Address) internally, the address counter will wrap from 7FFh to 000h.
After the FM24C16B (as receiver) acknowledges the slave Unlike other nonvolatile memory technologies, there is no
address, the master can place the word address on the bus for effective write delay with F-RAM. Since the read and write
a write operation. The word address is the lower 8-bits of the access times of the underlying memory are the same, the user
address to be combined with the 3-bits page select to specify experiences no delay through the bus. The entire memory cycle
exactly the byte to be written. The complete 11-bit address is occurs in less time than a single bus clock. Therefore, any
latched internally. No word address occurs for a read operation, operation including read or write can occur immediately following
though the 3-bit page select is latched internally. Reads always a write. Acknowledge polling, a technique used with EEPROMs
use the lower 8-bits that are held internally in the address latch. to determine if a write is complete is unnecessary and will always
That is, reads always begin at the address following the previous return a ready condition.
access. A random read address can be loaded by doing a write Internally, an actual memory write occurs after the 8th data bit is
operation as explained below. transferred. It will be complete before the acknowledge is sent.
After transmission of each data byte, just prior to the Therefore, if the user desires to abort a write without altering the
acknowledge, the FM24C16B increments the internal address memory contents, this should be done using START or STOP
latch. This allows the next sequential byte to be accessed with condition prior to the 8th data bit. The FM24C16B uses no page
no additional addressing. After the last address (7FFh) is buffering.
reached, the address latch will roll over to 000h. There is no limit The memory array can be write-protected using the WP pin.
to the number of bytes that can be accessed with a single read Setting the WP pin to a HIGH condition (VDD) will write-protect
or write operation. all addresses. The FM24C16B will not acknowledge data bytes
that are written to protected addresses. In addition, the address
Data Transfer
counter will not increment if writes are attempted to these
After the address bytes have been transmitted, data transfer addresses. Setting WP to a LOW state (VSS) will disable the write
between the bus master and the FM24C16B can begin. For a protect. WP is pulled down internally.
read operation the FM24C16B will place 8 data bits on the bus
Figure 7 and Figure 8 on page 7 below illustrate a single-byte
then wait for an acknowledge from the master. If the
and multiple-byte write cycles.
acknowledge occurs, the FM24C16B will transfer the next

Figure 7. Single-Byte Write

Start Address & Data Stop
By Master

S Slave Address 0 A Word Address A Data Byte A P

By F-RAM
Acknowledge

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 FM24C16B

Figure 8. Multi-Byte Write

Start Address & Data Stop

By Master

S Slave Address 0 A Word Address A Data Byte A Data Byte A P

By F-RAM
Acknowledge

Read Operation Beginning with the current address, the bus master can read any
number of bytes. Thus, a sequential read is simply a current
There are two basic types of read operations. They are current
address read with multiple byte transfers. After each byte the
address read and selective address read. In a current address
internal address counter will be incremented.
read, the FM24C16B uses the internal address latch to supply
the lower 8 address bits. In a selective read, the user performs a Note Each time the bus master acknowledges a byte, this
procedure to set these lower address bits to a specific value. indicates that the FM24C16B should read out the next sequential
byte.
Current Address & Sequential Read
There are four ways to properly terminate a read operation.
As mentioned above the FM24C16B uses an internal latch to Failing to properly terminate the read will most likely create a bus
supply the lower 8 address bits for a read operation. A current contention as the FM24C16B attempts to read out additional
address read uses the existing value in the address latch as a data onto the bus. The four valid methods are:
starting place for the read operation. The system reads from the 1. The bus master issues a no-acknowledge in the 9th clock
address immediately following that of the last operation. cycle and a STOP in the 10th clock cycle. This is illustrated in
To perform a current address read, the bus master supplies a the diagrams below. This is preferred.
slave address with the LSB set to a ‘1’. This indicates that a read 2. The bus master issues a no-acknowledge in the 9th clock
operation is requested. The three page select bits in the slave cycle and a START in the 10th.
address specifies the block of memory that is used for the read
operation. After receiving the complete slave address, the 3. The bus master issues a STOP in the 9th clock cycle.
FM24C16B will begin shifting out data from the current address 4. The bus master issues a START in the 9th clock cycle.
on the next clock. The current address is the 3-bits from the slave If the internal address reaches 7FFh, it will wrap around to 000h
address combined with the 8-bits that were in the internal on the next read cycle. Figure 9 and Figure 10 below show the
address latch. proper operation for current address reads.

Figure 9. Current Address Read

No
By Master Start Address Acknowledge
Stop

S Slave Address 1 A Data Byte 1 P

By F-RAM Acknowledge Data

Figure 10. Sequential Read

No
Start Address Acknowledge Acknowledge
By Master
Stop

S Slave Address 1 A Data Byte A Data Byte 1 P

By F-RAM Acknowledge Data

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 FM24C16B

Selective (Random) Read operation. According to the write protocol, the bus master then
There is a simple technique that allows a user to select a random sends the word address byte that is loaded into the internal
address location as the starting point for a read operation. This address latch. After the FM24C16B acknowledges the word
involves using the first two bytes of a write operation to set the address, the bus master issues a START condition. This simul-
internal address followed by subsequent read operations. taneously aborts the write operation and allows the read
command to be issued with the slave address LSB set to a ‘1’.
To perform a selective read, the bus master sends out the slave The operation is now a current address read.
address with the LSB (R/W) set to 0. This specifies a write

Figure 11. Selective (Random) Read

No
Start Address Start Address Acknowledge Acknowledge
By Master
Stop

S Slave Address 0 A Word Address A S Slave Address 1 A Data Byte A Data Byte 1 P

By F-RAM Acknowledge Data

Endurance row. Endurance can be optimized by ensuring frequently

accessed data is located in different rows. Regardless, FRAM
The FM24C16B internally operates with a read and restore read and write endurance is effectively unlimited at the 1MHz I2C
mechanism. Therefore, endurance cycles are applied for each speed. Even at 3000 accesses per second to the same row,
read or write cycle. The memory architecture is based on an 10 years time will elapse before 1 trillion endurance cycles occur.
array of rows and columns. Each read or write access causes an
endurance cycle for an entire row. In the FM24C16B, a row is 64
bits wide. Every 8-byte boundary marks the beginning of a new

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 FM24C16B

Maximum Ratings Package power dissipation capability

(TA = 25 °C) ................................................................. 1.0 W
Exceeding maximum ratings may shorten the useful life of the
Surface mount lead soldering temperature
device. These user guidelines are not tested.
(10 seconds) ............................................................ +260 °C
Storage temperature ................................ –65 °C to +125 °C
Electrostatic Discharge Voltage [1]
Maximum accumulated storage time Human Body Model (AEC-Q100-002 Rev. E) ..................... 2 kV
At 125 °C ambient temperature ................................. 1000 h Charged Device Model (AEC-Q100-011 Rev. B) ................ 500 V
At 85 °C ambient temperature ................................ 10 Years
Latch-up current .................................................... > 140 mA
Ambient temperature
* Exception: The “VIN < VDD + 1.0 V” restriction does not apply
with power applied ................................... –55 °C to +125 °C
to the SCL and SDA inputs.
Supply voltage on VDD relative to VSS .........–1.0 V to +7.0 V
Input voltage .......... –1.0 V to + 7.0 V and VIN < VDD + 1.0 V Operating Range
DC voltage applied to outputs Range Ambient Temperature (TA) VDD
in High-Z state .................................... –0.5 V to VDD + 0.5 V Industrial –40 C to +85 C 4.5 V to 5.5 V
Transient voltage (< 20 ns)
on any pin to ground potential ............ –2.0 V to VDD + 2.0 V

DC Electrical Characteristics
Over the Operating Range

Parameter Description Test Conditions Min Typ [2] Max Unit

VDD Power supply 4.5 5.0 5.5 V
IDD Average VDD current SCL toggling fSCL = 100 kHz – – 100 A
between
fSCL = 400 kHz – – 200 A
VDD – 0.3 V and VSS,
other inputs VSS or fSCL = 1 MHz – – 400 A
VDD – 0.3 V.
ISB Standby current SCL = SDA = VDD. All other inputs VSS – 4 10 A
or VDD. Stop command issued.
ILI Input leakage current VSS < VIN < VDD –1 – +1 A
(Except WP)
Input leakage current (for WP) VSS < VIN < VDD –1 – +100 A
ILO Output leakage current VSS < VIN < VDD –1 – +1 A
VIH Input HIGH voltage 0.7 × VDD – VDD + 0.3 V
VIL Input LOW voltage –0.3 – 0.3 × VDD V
VOL Output LOW voltage IOL = 3 mA – – 0.4 V
[3]
Rin Input resistance (WP) For VIN = VIL (Max) 40 – – k
For VIN = VIH (Min) 1 – – M
VHYS[4] Input Hysteresis 0.05 × VDD – – V

Notes
1. Electrostatic Discharge voltages specified in the datasheet are the JEDEC standard limits used for qualifying the device. To know the maximum value device passes
for, please refer to the device qualification report available on the website.
2. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
3. The input pull-down circuit is strong (40 k) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH.
4. These parameters are guaranteed by design and are not tested.

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 FM24C16B

Data Retention and Endurance

Parameter Description Test condition Min Max Unit
TDR Data retention TA = 85 C 10 – Years
TA = 75 C 38 –
TA = 65 C 151 –
14
NVC Endurance Over operating temperature 10 – Cycles

Capacitance
Parameter [5] Description Test Conditions Max Unit
CO Output pin capacitance (SDA) TA = 25 C, f = 1 MHz, VDD = VDD(typ) 8 pF
CI Input pin capacitance 6 pF

Thermal Resistance
Parameter [5] Description Test Conditions 8-pin SOIC Unit
JA Thermal resistance Test conditions follow standard test methods and 147 C/W
(junction to ambient) procedures for measuring thermal impedance, per
EIA/JESD51.
JC Thermal resistance 47 C/W
(junction to case)

AC Test Loads and Waveforms

Figure 12. AC Test Loads and Waveforms

5.5 V

1.7 k

OUTPUT

100 pF

AC Test Conditions
Input pulse levels .................................10% and 90% of VDD
Input rise and fall times .................................................10 ns
Input and output timing reference levels ................0.5 × VDD
Output load capacitance ............................................ 100 pF

Note
5. These parameters are guaranteed by design and are not tested.

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 FM24C16B

AC Switching Characteristics
Over the Operating Range
Parameter [6]
Cypress Alt. Description Min Max Min Max Min Max Unit
Parameter Parameter
fSCL[7] SCL clock frequency – 0.1 – 0.4 – 1.0 MHz
tSU; STA Start condition setup for repeated Start 4.7 – 0.6 – 0.25 – µs
tHD;STA Start condition hold time 4.0 – 0.6 – 0.25 – µs
tLOW Clock LOW period 4.7 – 1.3 – 0.6 – µs
tHIGH Clock HIGH period 4.0 – 0.6 – 0.4 – µs
tSU;DAT tSU;DATA Data in setup 250 – 100 – 100 – ns
tHD;DAT tHD;DATA Data in hold 0 – 0 – 0 – ns
tDH Data output hold (from SCL @ VIL) 0 – 0 – 0 – ns
tR [8] tr Input rise time – 1000 – 300 – 300 ns
tF[8] tf Input fall time – 300 – 300 – 100 ns
tSU;STO STOP condition setup 4.0 – 0.6 – 0.25 – µs
tAA tVD;DATA SCL LOW to SDA Data Out Valid – 3 – 0.9 – 0.55 µs
tBUF Bus free before new transmission 4.7 – 1.3 – 0.5 – µs
tSP Noise suppression time constant on SCL, SDA – 50 – 50 – 50 ns

Figure 13. Read Bus Timing Diagram

tHIGH
tR tF tLOW tSP tSP
`
SCL
tSU:SDA 1/fSCL
tBUF tHD:DAT
tSU:DAT
SDA
tAA tDH
Start Stop Start Acknowledge
Figure 14. Write Bus Timing Diagram
tHD:DAT

SCL
tHD:STA tSU:DAT tAA
tSU:STO

SDA

Start Stop Start Acknowledge

Notes
6. Test conditions assume signal transition time of 10 ns or less, timing reference levels of VDD/2, input pulse levels of 0 to VDD(typ), and output loading of the specified
IOL and load capacitance shown in Figure 12.
7. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL (max).
8. These parameters are guaranteed by design and are not tested.

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 FM24C16B

Power Cycle Timing

Over the Operating Range

Parameter Description Min Max Unit

tPU Power-up VDD(min) to first access (START condition) 1 – ms

tPD Last access (STOP condition) to power-down (VDD(min)) 0 – µs

tVR [9, 10] VDD power-up ramp rate 3.3 – µs/V

tVF [9, 10] VDD power-down ramp rate 3.3 – µs/V

Figure 15. Power Cycle Timing

~
~
VDD(min) VDD(min)
tVR tVF
VDD

tPU tPD

SDA
~
~

I2 C START I2 C STOP

Notes
9. Slope measured at any point on the VDD waveform.
10. Guaranteed by design.

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 FM24C16B

Ordering Information
Package Operating
Ordering Code Package Type
Diagram Range
FM24C16B-G 51-85066 8-pin SOIC Industrial
FM24C16B-GTR
All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.

Ordering Code Definitions

FM 24 C 16 B - G X

Option: X = blank or TR
blank = Standard; T = Tape and Reel

Package Type: G = 8-pin SOIC

Die Revision = B
Density: 16 = 16-kbit
Voltage: C = 4.5 V to 5.5 V
I2C F-RAM
Cypress

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 FM24C16B

Package Diagram
Figure 16. 8-pin SOIC (150 Mils) Package Outline, 51-85066

51-85066 *I

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 FM24C16B

Acronyms Document Conventions

Acronym Description Units of Measure
ACK Acknowledge Symbol Unit of Measure
CMOS Complementary Metal Oxide Semiconductor °C degree Celsius
EIA Electronic Industries Alliance Hz hertz
I2C Inter-Integrated Circuit Kb kilobit
I/O Input/Output kHz kilohertz

JEDEC Joint Electron Devices Engineering Council k kilohm

MHz megahertz
LSB Least Significant Bit
M megaohm
MSB Most Significant Bit
A microampere
NACK No Acknowledge
s microsecond
RoHS Restriction of Hazardous Substances
mA milliampere
R/W Read/Write
ms millisecond
SCL Serial Clock Line ns nanosecond
SDA Serial Data Access  ohm
SOIC Small Outline Integrated Circuit % percent
WP Write Protect pF picofarad
V volt
W watt

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 FM24C16B

Document History Page

Document Title: FM24C16B, 16-Kbit (2K × 8) Serial (I2C) F-RAM
Document Number: 001-84450
Orig. of Submission
Rev. ECN No. Description of Change
Change Date
** 3902082 GVCH 02/25/2013 New spec.
*A 3924523 GVCH 03/07/2013 Updated Power Cycle Timing:
Changed minimum value of tPU parameter from 10 ms to 1 ms.
*B 3996669 GVCH 05/13/2013 Added Appendix A - Errata for FM24C16B.
*C 4045469 GVCH 06/30/2013 All errata items are fixed and the errata is removed.
*D 4283418 GVCH 02/19/2014 Updated Features:
Replaced “High Endurance (1012) Read/Write Cycles” with “High-endurance
100 trillion (1014) read/writes”.
Updated Maximum Ratings:
Added “Maximum junction temperature” and its corresponding details.
Added “DC voltage applied to outputs in High-Z state” and its corresponding
details.
Added “Transient voltage (< 20 ns) on any pin to ground potential” and its
corresponding details.
Added “Package power dissipation capability (TA = 25 °C)” and its
corresponding details.
Removed “Package Moisture Sensitivity Level (MSL)” and its corresponding
details.
Added “Latch-up current” and its corresponding details.
Updated DC Electrical Characteristics:
Removed existing details of ILI parameter and splitted ILI parameter into two
rows namely “Input leakage current (Except WP)” and “Input leakage current
(for WP)” and added corresponding values.
Updated Data Retention and Endurance:
Removed details of TDR parameter corresponding to “TA = +80 °C”.
Added details of TDR parameter corresponding to “TA = 65 °C”.
Added NVC parameter and its corresponding details.
Added Thermal Resistance.
Updated Package Diagram:
Removed Package Marking Scheme (top mark).
Removed “Ramtron Revision History”.
Updated to Cypress template.
Completing Sunset Review.
*E 4272607 GVCH 03/11/2014 Updated AC Switching Characteristics:
Fixed typo (Replaced “ns” with “μs” in “Unit” column for tSU:STA, tHD:STA, tLOW,
tHIGH, tSU:STO, tAA and tBUF parameters).
*F 4343617 GVCH 04/21/2014 Updated DC Electrical Characteristics:
Fixed typo (Replaced “C” with “V” in “Unit” column for VOL parameter).
*G 4566147 GVCH 11/10/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*H 4782742 GVCH 06/01/2015 Updated Ordering Information:
Fixed Typo (Replaced “001-85066” with “51-85066” in “Package Diagram”
column).
Updated Package Diagram:
spec 51-85066 – Changed revision from *F to *G.
Updated to new template.

Document Number: 001-84450 Rev. *M Page 16 of 18

 FM24C16B

Document History Page (continued)

Document Title: FM24C16B, 16-Kbit (2K × 8) Serial (I2C) F-RAM
Document Number: 001-84450
Orig. of Submission
Rev. ECN No. Description of Change
Change Date
*I 4874535 ZSK / PSR 08/06/2015 Updated Maximum Ratings:
Removed “Maximum junction temperature” and its corresponding details.
Added “Maximum accumulated storage time” and its corresponding details.
Added “Ambient temperature with power applied” and its corresponding
details.
*J 5606370 GVCH 01/27/2017 Updated Maximum Ratings:
Updated Electrostatic Discharge Voltage (in compliance with AEC-Q100
standard):
Changed value of “Human Body Model” from 4 kV to 2 kV.
Changed value of “Charged Device Model” from 1.25 kV to 500 V.
Removed “Machine Model” related information.
Updated Package Diagram:
spec 51-85066 – Changed revision from *G to *H.
Updated to new template.
Completing Sunset Review.
*K 5700082 GVCH 04/19/2017 Updated Maximum Ratings:
Added Note 1 and referred the same note in “Electrostatic Discharge Voltage”.
Updated to new template.
*L 6034128 ZSK 02/12/2018 Updated Power Cycle Timing:
Changed minimum value of tVR parameter from 30 µs/V to 3.3 µs/V.
Changed minimum value of tVF parameter from 30 µs/V to 3.3 µs/V.
Updated Package Diagram:
spec 51-85066 – Changed revision from *H to *I.
Updated to new template.
*M 6320819 GVCH 12/05/2018 Updated Maximum Ratings:
Replaced “–55 °C to +125 °C” with “–65 °C to +125 °C” in ratings corresponding
to “Storage temperature”.

Document Number: 001-84450 Rev. *M Page 17 of 18

 FM24C16B

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