X90CP154.xx-00 en V1.02
X90CP154.xx-00 en V1.02
X90CP154.xx-00 en V1.02
xx-00
Data sheet
1.02 (07.2024)
Publishing information
B&R Industrial Automation GmbH
B&R Strasse 1
5142 Eggelsberg
Austria
Telephone: +43 7748 6586-0
Fax: +43 7748 6586-26
[email protected]
Disclaimer
All information in this document is current as of its creation. The contents of this document are subject to
change without notice. B&R Industrial Automation GmbH assumes unlimited liability in particular for tech-
nical or editorial errors in this document only (i) in the event of gross negligence or (ii) for culpably inflicted
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mance and use of this material.
B&R Industrial Automation GmbH notes that the software and hardware designations and brand names
of the respective companies used in this document are subject to general trademark, brand or patent pro-
tection.
Hardware and software from third-party suppliers referenced in this document is subject exclusively to the
respective terms of use of these third-party providers. B&R Industrial Automation GmbH assumes no lia-
bility in this regard. Any recommendations made by B&R Industrial Automation GmbH are not contractual
content, but merely non-binding information for which no liability is assumed. When using hardware and
software from third-party suppliers, the relevant user documentation of these third-party suppliers must
additionally be consulted and, in particular, the safety guidelines and technical specifications contained
therein must be observed. The compatibility of the products from B&R Industrial Automation GmbH de-
scribed in this document with hardware and software from third-party suppliers is not contractual content
unless this has been separately agreed in individual cases; in this respect, warranty for such compatibility is
excluded in any case, and it is the sole responsibility of the customer to verify this compatibility in advance.
1652015512331-1.02.1
Version history
B&R makes every effort to keep documents as current as possible. The most current versions are available
for download on the B&R website (www.br-automation.com).
1 General information
Information:
For the permissible temperature range for using the cables, see the data sheet.
Customized logos
The X90 mobile controller can be delivered with a customized logo instead of the B&R logo. For additional
information about the exact ordering procedure, please contact the local sales office.
PVG outputs
The controller is equipped with 8 PVG-capable outputs. These can be used to control special electrohy-
draulic valves.
PWM outputs
The controller is equipped with 22 PWM outputs. 6 of these outputs are PWM-capable power outputs in an
H bridge configuration. The power outputs in the H bridge configuration can be individually connected in
parallel
Current measurement
For the digital and PWM outputs, currents can be measured as instantaneous values, root mean square or
arithmetic mean values.
Temperature management
The temperature is measured on the controller at various points and provided as special data points.
Operating management
Special data points are available in Automation Studio for monitoring the operating parameters in the con-
troller. These include:
• Sensor and supply voltages
• Controller currents with overload monitoring
• Status bits for sensor power supply, output enable, ignition and enable relay
Standby mode
The controller can be set to sleep mode so that energy can be saved when the machines are at a standstill
for longer periods.
LIN interface
The Local Interconnect Network (LIN) bus is a serial communication system for networking sensors and
actuators used primarily in vehicles. It is an open standard and a cost-effective alternative to the CAN bus.
2 Technical description
Information:
The device has immunity-related functions in accordance with Regulation No. 10 of the
United Nations Economic Commission for Europe (UN/ECE).
RDY/F
RDY/F Yellow On Mode SERVICE2) or BOOT2)
S/E Blinking If LED "RDY/F" blinks yellow and LED "R/E" blinks red, a license violation has
PLK occurred.
ETH S/E Green/Red Status/Error LED, see "LED "S/E" (status/error LED)" on page 12.
PLK Green On The link to the POWERLINK remote station is established.
Blinking The link to the POWERLINK remote station is established. The LED blinks
when POWERLINK activity is taking place on the bus.
ETH Green On The link to the Ethernet remote station is established.
Blinking The link to the Ethernet remote station is established. The LED blinks if Eth-
ernet activity is taking place on the bus.
1) This procedure can also take several minutes depending on the configuration.
2) The operating states are described in "Real-time operating system - Method of operation - Operating states" in Automation Help.
3) The project installation (initial installation or update) via USB flash drive was aborted with an error.
This LED is a green/red dual LED and indicates the state of the POWERLINK interface. The LED states have
a different meaning depending on the operating mode of the POWERLINK interface.
Error message
LED "S/E"
Green Red Description
Off On The interface is in error mode (failed Ethernet frames, increased number of collisions on the network, etc.).
Note:
Several red blinking signals are displayed immediately after the device is switched on. These are not errors, however.
Blinking On If an error occurs in the following modes, then the green LED blinks over the red LED:
• PRE_OPERATIONAL_1
• PRE_OPERATIONAL_2
• READY_TO_OPERATE
Status
green
t
Error
red
t
LED "S/E"
Interface status
LED "S/E"
Green Red Description
Off Off Mode: NOT_ACTIVE
The interface is either in mode NOT_ACTIVE or one of the following modes or errors is present:
• The device is switched off.
• The device is in the startup phase.
• The interface or device is not configured correctly in Automation Studio.
• The interface or device is defective.
LED "S/E"
Green Red Description
Triple flash Off Mode: READY_TO_OPERATE
(approx. 1 Hz) The interface is in mode READY_TO_OPERATE.
Blink times
Triple flash
200 200 200 200 200 1000
Double flash
200 200 200 1000
Single flash
200 1000
Blinking
200 200
Flickering
All times in ms
A system stop error can occur due to incorrect configuration or defective hardware.
The error code is indicated by LED "S/E" blinking red. The blinking signal of the error code consists of 4
switch-on phases with short (150 ms) or long (600 ms) duration. The error code is repeated every 2 seconds.
RAM error
Hardware error
600 300 150 300 150 300 600 2000 All times in ms
2.3 Dimensions
43.5 mm
225 mm
189.7 mm
219.5 mm
203.7 mm
189.9 mm
Information:
M6 screws are not included in delivery.
IF4 - USB
IF3 - POWERLINK
IF2 - Ethernet
I/O
I/O - CAN bus - LIN bus - RS232
Reset button
The button must be pressed for less than 2 seconds to trigger a reset. This triggers a hardware reset on
the controller, which means that:
• All application programs are stopped.
• All outputs are set to zero.
The controller then boots into service mode by default. The boot mode that follows after pressing the reset
button can be defined in Automation Studio.
• Service mode (default)
• Warm restart
• Cold restart
• Diagnostic mode
Information:
The reset button function can also be triggered by using the "Mode" connection (X1.A.D2).
The controllers have no battery and are maintenance-free. Eliminating the backup battery was made pos-
sible by the following measures:
Data and real-time clock buffering Type of buffering Note
Remanent variables FRAM This FRAM stores its contents ferroelectrically. Unlike normal SRAM, this
does not require a battery.
Real-time clock Gold foil capacitor The real-time clock is backed up by a gold foil capacitor. The gold foil capac-
itor is charged via the I/O power supply (V_I/O) and is fully charged after a
continuous operating time of 3 hours.
Pinout
Interface Pinout
Pin Name Assignment
1 Tx+ Transmit data +
2 Rx+ Receive data+
3 Tx- Transmit data-
4 Rx- Receive data -
Pinout
Interface Pinout
Pin Name Assignment
1 Tx+ Transmit data +
2 Rx+ Receive data+
3 Tx- Transmit data-
4 Rx- Receive data -
USB
Interface IF4 is a non-galvanically isolated USB interface. The connection is made via a USB interface
(1.1/2.0).
Information:
USB peripheral devices can be connected to the USB interfaces. Automation Runtime sup-
ports a selection of USB peripheral devices. For the supported USB classes, see the AR help
documentation.
Information:
The following must be taken into account when using a USB peripheral device and grounded
controller power supply (PELV):
• Only USB peripheral devices with no connection between GND and ground are permit-
ted to be connected. This is the case, e.g. with the USB dongle from B&R.
Only the following file formats are supported for USB storage devices:
• FAT12
• FAT16
• FAT32
Access to NTFS file formats is NOT supported!
For additional information, see section "Accessories - Multi-connector accessories" in the X90 user's man-
ual.
2.4.8.1 Pinout
The interface and control/status pin connections are implemented on CMC multi-header X1.A.
Pin Channel
CAN1
B1 CAN_L
C1 CAN_H
CAN3 CAN2
CAN2 B2 CAN_L
CAN1 C2 CAN_H
CAN3 1)
D1 CAN_L
E1 CAN_H
1) The connection can be used as a wake-up source (see "Standby mode" on page 63).
Pin Channel
A1 LIN bus
LIN
Pin Channel
D4 RS232 TxD
E4 RS232 RxD
RS232
The controller is equipped with 3 special digital inputs that can be used to influence the behavior of the
controller as well as a digital output for status and diagnostic information from the controller.
Pin Direction Channel
K2 Input Ignition
C3 Input Enable signal
Enable
D2 Input Mode
Mode
A2 Output Status
Status
Ignition
2.4.8.2.4.1 Ignition
A digital input (K2) is available on the X90 mobile system that allows the controller to respond using soft-
ware when the vehicle ignition is switched on or off. This connection is optional and can be wired via the
ignition (terminal 15), wired permanently to the power source or not wired, depending on the application.
2.4.8.2.4.3 Mode
Mode (D2) is functionally identical to pressing the reset button (see "Reset button" on page 16). The CPU
or I/O voltage should be applied as the reference voltage. If not used, the connection must be connected
to GND.
2.4.8.2.4.4 Status
The status (A2) can be used to connect an external LED (max. 20 mA) that can be used as a status indicator
or for diagnostics. For the connection, see "Power supply" on page 24.
LED status indicators Explanation
Off Application running
Blinking (1 Hz) System startup:
The controller is initializing the application, all bus systems and I/O modules.
Blinking (10 Hz) Overtemperature or overvoltage
Flashing Standby mode
Double flash System startup (during firmware update)1)
On2) Mode SERVICE or FAILSAFE3)
1) This procedure can also take several minutes depending on the configuration.
2) On system startup, it lights up for about 1 second at the beginning, but this is not an error message.
3) The operating states are described in "Real-time operating system - Method of operation - Operating states" in Automation Help.
Blink times
Double flash
Blinking 1 Hz
Blinking 10 Hz.
1s 1s
Flashing
5s
ECU
V_CPU
To the
A/D converter
5/10 V Sensor Power
sensor power supply power supply supply
1 to 8 MF-AI (AT)
1 to 8 MF-AI (PVG)
1 to 4 MF-AI (std)
1 to 8 MF-DI (CI)
1 to 2 MF-DI (std)
RS-232
Vcc
Mode
Status Reset controller
Ignition
To the
V_Relay
A/D converter
Enable signal
To the CAN1
A/D converter CAN2
V_I/O CAN3
V_I/O CPU
V_I/O LIN
Ethernet
1 to 8 MF-DO (std) POWERLINK
1 to 16 MF-PWM
(std)
1 to 6 MF-PWM
(bridge)
RTC
GND To the Vcc
A/D converter
GND
GND
USB LED Reset
Analog GND status indicators
ECU
5 A slow-blow V_CPU A: K3
1 A slow-blow
1) A: D2
Mode
2) A: A2
Status
1 A slow-blow
A: K2
3) 15 Ignition
1 A slow-blow
A: C3
4) Approval
10 A slow-blow V_I/O A: L3
10 A slow-blow V_I/O A: M4
10 A slow-blow V_I/O B: G1
30
12/24 V
31 GND A: L2
GND A: L4
GND B: G3
Analog GND A: G3
For additional details, see "External fuse protection" on page 34 and "Fuse protection for lines" on page
34.
Notice!
National regulations must also be observed with the fuse protection and wiring of the de-
vice. In addition, it must be ensured when working on the device or the wiring that the en-
tire device is disconnected from the power supply.
ECU
V_CPU
R 1)
DI SP 2)
10 nF
GND
ECU
V_CPU
SP 1)
DI
10 nF R 2)
1) Signal processing
2) Resistance according to the configuration
2.5.2.2 Multifunction analog input MF-AI (AT) / MF-AI (PVG) / MF-AI (std)
ECU
V_CPU
R 1)
AI SP 2)
10 nF
GND
ECU
V_CPU
SP 1)
AI
10 nF R 2)
1) Signal processing
2) Resistance according to the configuration
ECU
V_CPU
R 1)
AI SP 2)
1 kΩ
10 nF
10 kΩ
GND
ECU
5 V 1)
1 kΩ
10 kΩ
SP 2)
AI
10 nF
Voltage input
ECU
AI
SP 2)
1) 10 nF
Analog GND
Current input
ECU
AI
SP 2)
1) 10 nF
Analog GND
Information:
The sensor power supply must be configured to 10 V to ensure functionality.
ECU
10 V 1)
t
2)
AI SP 3)
10 nF
ECU
V_I/O
Relay active
DO → DI 1) SP 2)
22 nF
GND
ECU
V_I/O
SI 3)
MF-DO (std)
MF-PWM (std)
Relay active CI 4)
MF-PWM (bridge)
Not DO 1)
permitted
SP 5)
DO → DI 2)
22 nF
Information:
It is important to note that in the event of power failure or if the enable relay is cut off, then
the power supply for the sensor is also cut off. This is because the controller is provided
with a power supply via the freewheeling diode, which means the enable relay is bridged.
For this reason, current-sourcing inputs must be supplied via an output (MF-DO or MF-
PWM).
ECU
V_I/O
Relay active
PWM → DI 1) SP 2)
22 nF
GND
ECU
V_I/O
SI 3)
MF-DO (std)
MF-PWM (std)
Relay active CI 4)
MF-PWM (bridge)
Not PWM → DO 1)
permitted
SP 5)
PWM → DI 2)
22 nF
ECU
V_I/O
Relay active
PWM → DI 1) SP 2)
22 nF
GND
ECU
V_I/O
SI 3)
MF-DO (std)
MF-PWM (std)
Relay active CI 4)
MF-PWM (bridge)
Not PWM → DO 1)
permitted
SP 5)
PWM → DI 2)
22 nF
Information:
It is important to note that in the event of power failure or if the enable relay is cut off, then
the power supply for the sensor is also cut off. This is because the controller is provided
with a power supply via the freewheeling diode, which means the enable relay is bridged.
For this reason, current-sourcing inputs must be supplied via an output (MF-DO or MF-
PWM).
Source circuit
ECU
V_I/O
Relay active CI 1)
DO SI 2)
22 nF
3)
GND
1) Current information
2) Status information
3) See section "Switching inductive loads".
Source circuit
ECU
V_I/O
Relay active
PWM SI 1)
22 nF
GND
CI 2)
1) Status information
2) Current information
Source circuit
ECU
V_I/O
Relay active
PWM SI 1)
22 nF
GND
CI 2)
1) Status information
2) Current information
Sink circuit
ECU
V_I/O
SI 3)
MF-DO (std)
MF-PWM (std)
Relay active CI 4)
MF-PWM (bridge)
DO 1)
PWM 2) SI 3)
22 nF
CI 4)
Information:
It is important to note that in the event of power failure or if the enable relay is cut off, then
the power supply for the actuator is also cut off. This is because the module is supplied
with power via the freewheeling diode, which means the enable relay is bridged. For this
reason, current-sourcing inputs must be supplied via an output (MF-DO or MF-PWM).
H bridge wiring
ECU
V_I/O
Relay active
PWM SI 1)
22 nF
M CI 2)
PWM SI 1)
22 nF
CI 2)
1) Status information
2) Current information
ECU
V_CPU
SI 1)
AI SP 2)
22 nF
GND
1) Status information
2) Signal processing
ECU
V_CPU
AI SP 1)
22 nF 1 µF
GND
1) Signal processing
The power supply lines and power outputs must be protected by suitable circuit breakers or melting fuses
(line protection).
Connector Pin Description Fuse protection
C3 Enable signal 1A
K2 Ignition 1A
X1.A K3 Controller power supply 5A
L3 I/O power supply 10 A
M4 I/O power supply 10 A
X1.B G1 I/O power supply 10 A
The maximum permissible currents and voltages of all components within the system are not permitted
to be exceeded, e.g. current and voltage carrying capacities of the lines or cables, contacts of the CMC
multi-header, etc.
To avoid overloading the lines/cables and contacts on the CMC multi-header, all lined must be dimensioned
according to "Maximum load and line cross sections" on page 35. For the maximum permissible load
carrying capacities of the connector pins and mating connector, see the user's manual or the component
manufacturer's data sheets.
The power supply and GND lines must be connected to the remote stations as short as possible. This is
the only way to ensure safe operation under the maximum permissible operating conditions and to keep
voltage drops that occur as low as possible.
All GND lines should be connected to avoid overloads.
Notice!
The line impedances (line lengths, line cross-sections) and fuses must be selected in such
a way that rapid tripping of the fuse is ensured in the event of fault.
Information:
It must be ensured that the lines cannot be overloaded in the event of fault. See "Maximum
load and line cross sections" on page 35.
Analog inputs
The following conditions must be met in order to achieve the greatest possible measurement accuracy
when recording analog measured values:
• The analog GND connection must be routed separately from the GND connections.
• In the best case, each signal line to be measured should have its own reference signal line.
• The signal and reference signal line (e.g. GND) must be as symmetrical as possible (length, cross sec-
tion, etc.).
Input and output lines
A separate GND connection should be used for each power supply line.
The following parameters must be taken into account when selecting the line cross sections used:
CMC header Maximum load Smallest diameter Largest diameter
of the contacts [mm2] [AWG] [mm2] [AWG]
CP 0.6 terminal 5A 0.35 20 0.75 18
CP 1.5 terminal 10 A 0.5 16 2 24
0.1 H
1H
0.1 H
100 1H 100
0.01 H
0.1 H
0.01 H
Coil resistance 0.1 H Coil resistance
[ohm] [ohm] Coil inductance
Coil inductance
0.01 H
10 0.01 H 10
32 V 32 V
9V 9V
1 1
0.1 1 10 100 0.1 1 10 100
Max. switching cycles / second Max. switching cycles / second
(at 90% duty cycle) (at 90% duty cycle)
Notice!
Possible defect on the output
Exceeding the maximum permissible inductive loads according to the diagram is only per-
mitted if an appropriate external protective circuit (freewheeling diode) has been imple-
mented.
Notice!
Avoiding damage due to voltage feedback
When using current-sourcing sensors or actuators, the power must be supplied via a DO
channel.
2.7 Derating
2.7.1 MF-PWM (bridge)
MF-PWM output
These outputs are implemented as push-pull or "active clamp" outputs. The advantage of these drivers is
the reduced power dissipation when switching inductive loads.
Only consecutive outputs can be configured for parallel operation (e.g. 2, 3, 4). When used as an input, the
driver is switched to a high resistance level (default).
MF-PWM output:
Output current = [1000 / PWM frequency (Hz)] * Nominal output current
With parallel connection:
PWM frequency (Hz) = 3000 / Maximum current per output
30
20
connected in parallel
Number of outputs
10
load current [A]
Maximum
6
1 output
6
4
3
1
100 1000 4000
PWM frequency [Hz]
V_I/O
Ipk
30 Buffer capacitor
Power supply unit /
Battery Vdrop
31 GND
GND
Distribution terminal block
Sensor/Actuator GND
Information:
The functionality of the controller depends on the battery state of the vehicle and can
therefore not be ensured during motor startup.
3 Function description
For the exact pinout of the channels on the CMC multi-header, see "Pinout" on page 19.
Information:
These two channels are not available when using the RS232 interface.
Channels 19 to 26 can be configured as both digital or analog inputs as well as PVG-capable outputs.
Functions
• Analog input
- Voltage measurement range from 0 to 10 V or 0 to 32 V
- Current measurement range from 0 to 20 mA or 4 to 20 mA
- Resistance measurement from 0 to 4 kΩ
- Temperature measurement -200 to 850°C (Pt1000 characteristic curve)
• Digital input, configurable in 6 ways
- Sink/Source configuration
- High/Low resistance
- Diagnostics for current/voltage measurement
• PVG output
- Proportional valve control
- Frequency 25 kHz
- Supported types PVEA, H, S
• Analog output
Values Information
0 Off (default)
50 Digital input with voltage measurement diagnostics
51 Digital input with current measurement diagnostics
61 Digital input in source configuration, low resistance
62 Digital input in source configuration, power-saving (high resistance)
71 Digital input, sink configuration, low resistance
72 Digital input, sink configuration, power-saving (high resistance)
80 Analog input 0 to 10 V
81 Analog input 0 to 32 V
82 Analog input 0 to 20 mA
83 Analog input 4 to 20 mA
85 Temperature measurement
86 Analog input 0 to 4000 Ω
100 PVG
101 Analog output (ratiometric)
Channels 39 to 44 can be configured as both digital or analog inputs as well as PWM-capable power outputs.
Parallel connection is possible when configured as a digital output. A parallel connection is only possible
with adjacent outputs. This approach begins with the pin with the smallest number.
The output information is always used by the main output and all outputs connected in parallel. Parallel
connections are not possible via inputs.
Functions
• PWM output
- Maximum output current 6 A
- Maximum frequency 4 kHz
- H bridge
- Channels can be connected in parallel.
• Digital output
- Channels can be connected in parallel.
• Digital input, configurable in 2 ways
- Sink/Source configuration
Values Information
0 Off (default)
1 Digital output
12 PWM
15 PWM, H bridge + with next channel
16 PWM, H bridge - from previous channel
20 Digital output, parallel to previous channel
31 Digital input, source configuration
41 Digital input, sink configuration
Channels 45 to 60 can be configured as both digital or analog inputs as well as PWM-capable outputs.
A maximum of 2 adjacent outputs are permitted to be connected in parallel on the outputs (1 main output,
1 parallel output). In addition, only uneven channel numbers can be main outputs. Parallel connections are
not possible via inputs.
Functions
• PWM output
- Maximum output current 4 A
- Maximum frequency 1 kHz
- Channels can be connected in parallel in pairs.
• Digital output
- Channels can be connected in parallel in pairs.
• Digital input, configurable in 2 ways
- Sink/Source configuration
Values Information
0 Off (default)
1 Digital output
12 PWM
20 Digital output, parallel to previous channel1)
31 Digital input, source configuration
41 Digital input, sink configuration
Information:
Digital inputs 9 and 10 cannot be used when using the RS232 interface.
An input filter is available for each input. Disturbance pulses that are shorter than the input delay are sup-
pressed by the input filter.
Input
signal
Time
Time
The filter is implemented as a ramp filter, and the filter value is configured in 100 μs increments.
Values Information
0 No software filter
1 0.1 ms
...
10 1 ms (default)
...
250 25 ms - Higher values are limited to this value.
Information:
The register is described in "Digital input filter" on page 77.
A switching threshold with associated hysteresis can be configured for channels 11 to 30.
Configuration options
• Absolute value
The value is set in mV.
• Ratiometric
The value is set in percent.
Threshold value
Absolute or ratiometrically adjustable. When taking into account the configured hysteresis, a voltage level
under the threshold value results in "0" on the corresponding bit; a voltage level above the threshold value
results in "1".
Values Information
0 to 31000 Corresponds to 0 to 31000 mV if an absolute switching threshold is configured.
0 to 1000 Corresponds to 0 to 100.0% if a ratiometric switching threshold is configured.
Example
Desired level with absolute switching threshold: 16 V configuration value: 16000
Desired level with ratiometric switching threshold: 50% configuration value: 500
Hysteresis
Absolute or ratiometrically adjustable. Hysteresis is used to avoid frequent state changes in the measuring
range near the threshold. When taking into account the configured threshold value, a voltage level below
threshold value Switching threshold - Hysteresis results in "0" on the corresponding bit. A voltage level above
threshold value Switching threshold + Hysteresis results in "1".
Values Information
0 to 15000 Corresponds to 0 to 15000 mV if an absolute switching threshold is configured.
0 to 400 Corresponds to 0 to 40.0% if a ratiometric switching threshold is configured.
Example
Desired hysteresis range with absolute switching threshold: ±5 V configuration value: 5000
Desired hysteresis range with ratiometric switching threshold: ±10% configuration value: 100
Information:
Supply voltage V_CPU is used as a reference voltage for the ratiometric switching thresh-
old.
Information:
The sum of hysteresis and threshold is not permitted to exceed the limit of >32 V or >100%.
The difference between hysteresis and threshold is not permitted to be negative.
Information:
The register is described in "Configurable switching threshold" on page 78.
Digital inputs 1 to 8 can be used for high-speed edge detection. This runs parallel to all other functions such
as counters, etc. This function does not use the digital input filter.
The edge detection function allows edges to be measured with microsecond precision. 8 edge detection
units are available.
Edge selection
A master and a slave edge can be configured for each edge detection unit. Either the rising or falling edge
of one of the 8 high-speed digital input channels can be selected. Only one edge can be selected for each
edge detection unit.
Master and slave edge
Period measurement can be implemented using a master and slave edge, for example. To do this, enable
master and slave edge detection on the same channel. The edge direction for the master and slave edge
must be identical in order to obtain exactly one period.
For evaluation, read out MasterTime0x and SlaveTime0x from the I/O mapping (0x stands for the number
of the channel). The period in microseconds is the delta between the two values.
Example: Measurement on rising edge
U
Master edge Slave edge Master edge
Channel 0x
P1 P2 t [µs]
Timestamp
At each master edge, the timestamp of the master edge and the timestamp of the previous slave edge are
logged. Data points "Master count" and "Slave count" can always be used to determine how many edges have
been detected since the last task class cycle. The timestamp is based on the system time of the controller.
• When multiple edges occur within a sampling cycle (task class), the time of the last edge in each case
is displayed.
• If multiple slave edges occur before a master edge, then only the timestamp of the last edge is stored.
Error evaluation
Detected edges are stored in a ring buffer for all 8 edge detection units. Edges are lost when the ring buffer
overflows. The loss of one or more edges in the last system tick is detected.
Edges that could not be evaluated within the last system tick are recorded. The edges that are not evaluated
are evaluated in the next system tick.
Information:
The registers are described in "Edge detection" on page 80.
High-speed digital inputs 1 to 8 can be used for counter functions. This function does not use the digital
input filter. There are 4 counters available with 2 channels each.
The following functions are available:
• Event counters
• AB incremental counter
• DF counter function
• ABR counter function
Configuration options
Information:
1 to 4 channels are allocated depending on the counter mode used. An ABR or DF counter, for
example, can therefore only be configured on channel 1 (counter 1) or channel 5 (counter 3).
Channel Counters Event counters AB incremental counter DF counter function ABR counter function
1 1 - Mode = 1 A Mode = 3 D1) Mode = 4 A Mode = 5
2 - Mode = 2 B F2) B
3 2 - Mode = 1 A Mode = 3 R R
4 - Mode = 2 B E3) E3)
5 3 - Mode = 1 A Mode = 3 D1) Mode = 4 A Mode = 5
6 - Mode = 2 B F2) B
7 4 - Mode = 1 A Mode = 3 R R
8 - Mode = 2 B E3) E3)
1) Direction
2) Frequency
3) Enable reference
Information:
The registers are described in "Counter functions" on page 82.
Information:
In single shot mode, the latch is only enabled on a rising edge (0 → 1).
Information:
The registers are described in "Counter functions" on page 82.
Channels 11 to 26 are equipped with open-circuit and short-circuit detection. An evaluation is only per-
formed in the configurations "Digital input with voltage or current diagnostics measurement". The results
of diagnostics are displayed in the status register.
For open-circuit and short-circuit detection, the sensor must be connected with resistors. The resistors are
connected in series or parallel to the sensor. The following values are defined for the resistances:
Resistance Value
Serial (RS) 1 kΩ
Parallel (RP) 10 kΩ
R 1)
AI SP 2)
1 kΩ
10 nF
10 kΩ
GND
1 kΩ
10 kΩ
SP 2)
AI
10 nF
Information:
The register is described in "Status of the digital inputs" on page 79.
A configurable input filter with input ramp limiting is available for each input.
Information:
The register is described in "Input filter" on page 84.
Filter level
A filter can be defined to prevent large input steps. This filter is used to bring the input value closer to the
actual analog value over a period of several milliseconds.
Filtering takes place after any input ramp limiting has been carried out.
Formula for calculating the input value:
Value Old Input value
Value New = Value Old - +
Filter level Filter level
Adjustable filter levels:
Value Filter level
0 Filter switched off
1 Filter level 2
2 Filter level 4
3 Filter level 8
4 Filter level 16
5 Filter level 32
6 Filter level 64
7 Filter level 128
The following examples show the functionality of the filter based on an input step and a disturbance.
Example 1
The input value jumps from 8000 to 16000. The diagram shows the calculated value with the following
settings:
Input ramp limiting = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4
16000
8000
0
1 2 3 4 5 6 7 8 Conversion cycle of
analog input (160 µs)
Input jump
Example 2
A disturbance interferes with the input value. The diagram shows the calculated value with the following
settings:
Input ramp limiting = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4
16000
Disturbance (spike)
8000
0
1 2 3 4 5 6 7 8 Conversion cycle of
analog input (160 µs)
Input ramp limiting is well suited for suppressing disturbances (spikes). The following examples show the
functionality of input ramp limiting based on an input step and a disturbance.
Example 1
The input value jumps from 8000 to 17000. The diagram shows the tracked input value with the following
settings:
Input ramp limiting = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally tracked input value before the filter
17000
8000
0
1 2 3 4 5 6 7 8 Conversion cycle of
analog input
Input jump (160 µs)
16000
Disturbance (spike)
8000
0
1 2 3 4 5 6 7 8 Conversion cycle of
analog input
(160 µs)
The input signal of the analog inputs is monitored against the upper and lower limit values. These depend
on the operating mode that is set in each case.
If required, other limit values can be set for each channel individually. These are enabled automatically by
writing to the limit value registers. From this point on, the analog values will be monitored and limited
according to the new limits. The results of monitoring are displayed in the status register.
Operating mode Lower limit value Upper limit value
Analog input 0 to 10 or 32 VDC 0 32767
Analog input 0 to 20 mA 0 32767
Analog input 4 to 20 mA -8192 32767
Resistance measurement 0 to 4000 Ω 0 4000
Temperature measurement -2000 8500
Information:
If type "Analog input 0-20 mA", "Analog input 4 - 20 mA" or "DI diagnostic current mea-
surement" is configured, the shunt and therefore the analog input are cut off after the up-
per measurement range is exceeded for 0.5 s (ramp filter). After 5 s, the analog input is
switched on again. During the cutoff time, the corresponding measurement range exceed-
ed bit is set.
Information:
If the input is configured to 4 to 20 mA, the measurement information is checked for <2 mA
(open circuit). In this case, the "OutOfRangeAnalogInput'x'" bit is set to value 1.
Information:
The registers are described in "Analog input - Upper and lower limit value" on page 85
and "Status of the analog inputs" on page 86.
Information:
The registers are described in "Status of the digital outputs" on page 87.
If the switched output level of a digital output does not correspond to the read-back value taking the set
delay time into account, then an error bit is set. The delay time is rounded up to a multiple of the system tick.
As soon as the switched output level again corresponds to the read-back value taking the set error state
filter ① into account, the corresponding bit will be reset again.
Error state
Before the filter
True
False
Time
After the filter
① ① ① ① ① ①
True
False
Time
If the channel is shut down due to overload, this bit is permanently set until the overload is acknowledged.
If a pin is configured as PWM or DI, then the corresponding bit is not maintained.
The digital outputs of channels 31 to 38 can be connected in parallel. A maximum of 2 adjacent outputs
are permitted to be connected in parallel on the outputs (1 main output, 1 parallel output). In addition, only
uneven channel numbers can be main outputs.
Information:
Parallel outputs are switched with the corresponding digital output.
3.4.3 Overload
Overload monitoring
Overload protection is necessary for the circuit board traces and current measuring shunt. The driver com-
ponents protect themselves against overload, and the temperature development in the housing is moni-
tored separately.
The power dissipation on the circuit board traces and shunt is proportional to the quadratic current. The
mean value of the quadratic current should not significantly exceed INom (+5% or 12.5% tolerance) in t sec-
onds. An integral is calculated over the quadratic current for the last 2 seconds, and as soon as this let-
through energy value is exceeded, the output is cut off.
Pin with 6 A continuous current:
INom = 6 A, t = 2 s
Let-through energy value = (6 A x 1.05)² x 2 s = 79.4 A²s
Pin with 4 A continuous current:
INom = 4 A, t = 2 s
Let-through energy value = (4 A x 1.05)² x 2 s = 35.3 A²s
Maximum cutoff time after the occurrence of an overload 1.5 ms + system tick time.
The user can also protect his load with this functionality. Using a configuration register, it is possible to
configure another "current value" instead of INom. If the let-through energy value based on this current value
exceeds that of the nominal current, the let-through energy value used is that of the nominal current.
If a measured value is outside the measurement range, 25 A is used for the further calculation of this mea-
sured value.
If more current (iboost) is required for a certain time (tboost), a smaller current (irest) must flow for the remaining
time (trest) to maintain the let-through energy. 1)
Let-through energy Multifunction outputs
79.4 A2s MF-PWM (bridge)
35.3 A2s MF-PWM (std)
40.5 A2s MF-DO
Example
1) If a current >10 A (MF-PWM) or >20 A (MF-DO) flows, 25 A is used for the calculation.
Overload protection
The response threshold of the overload shutdown can be configured. If the default value of lNom is changed,
the configured value is used to calculate the maximum let-through energy.
If the calculated let-through energy exceeds the limit value of the channel, the configuration is ignored and
limited to the limit value of the pin.
This value also defines the maximum current of the pin in parallel configurations.
Information:
The configured current value is provided with a tolerance of 5% or 12.5%.
Overload shutdown
If the output is cut off due to an overload, then the corresponding bit in the register is set. After an overload
shutdown has taken place, the output will only be re-enabled after acknowledgment by the application. In
addition, the minimum cutoff duration must be observed by the driver (5 s).
Information:
If acknowledgment is carried out before the minimum cutoff duration has elapsed, the ac-
knowledgment will be accepted; however, a DO set by the application is set by the driver
– and consequently the respective status bit (OverloadDigitalOutput31 to OverloadDigi-
talOutput60) is reset – only after the minimum cutoff duration (5 s) has elapsed.
Information:
The register is described in "Analog and PVG outputs" on page 89.
3.6 PVG
Digital output channels 19 to 26 can be configured as PVG outputs. PVG is a variant of pulse width modula-
tion for special electrohydraulic valves.
The PVG signal is defined by the two period and pulse width parameters.
Pulse width
U
V_IO
Period (frequency)
• Period (frequency)
The period is fixed at 25 kHz.
• Pulse width (DutyCyle)
This defines the switch-on time (t1) within a period (T).
Example
At fixed period duration T = 4000 [µs] (25 kHz) with a duty cycle of 25%, switch-on time t1 corresponds to
1000 [µs].
Switch-on time depending on the period duration and duty cycle:
U
V_IO
t1 t
t1
= 0.25 = 25%
T
Information:
The registers are described in "Analog and PVG outputs" on page 89.
3.6.1 Options
V_IO
Period (frequency)
• Period (frequency)
The period duration is defined in microseconds. The period duration can be changed during operation
using a data point or register.
• Pulse width (DutyCyle)
This defines the switch-on time (t1) in 0.1% increments within a period (T).
Example
Period duration T = 4000 [µs] with a duty cycle of 25% corresponds to switch-on time t1 of 1000 [µs].
Switch-on time depending on the period duration and duty cycle:
U
V_IO
t1 t
t1
= 0.25 = 25%
T
Information:
The registers are described in "Pulse width modulation (PWM)" on page 90.
H bridge functionality is configured and operated in the same way as PWM functionality. Negative pulse
widths can also be set so that movements in the opposite direction are also possible on the DC motor.
The PWM of the two channels is synchronized and modulated so that the resulting PWM frequency at the
load doubles. Frequencies up to 8 kHz are therefore possible in this mode.
The rising edge of the voltage curve at the load is regarded as the period start.
The period length or pulse width set by the user always refers to the voltage curve at the load. Frequencies
up to 8 kHz are possible.
Output H bridge
forward channel
Output H bridge
reverse channel
Voltage curve
load
Output H bridge
forward channel
Output H bridge
reverse channel
Voltage curve
load
Configuration
The H bridge reverse channel and its parallel pins apply all configurations from the H bridge forward channel
pin. The only exception is the overload protection current value (cfgOverloadLimitCurrentxx).
3.7.2 Options
Phase shift
In order to give the user the possibility to distribute load currents "more evenly", it is possible to set a phase
shift.
If a phase shift of the PWM outputs is desired, the period length must be set via the I/O configuration.
Parallel configuration
Possible error bits, such as overload monitoring, are operated together. This means that if an overload
occurs on the parallel output, the overload bit of the main output and of the other parallel outputs is also
set and all are cut off.
Acknowledgment can be carried out on any output of the parallel configuration.
Overload monitoring
For additional information, see "Overload" on page 54.
3.7.4 Dither
Using two configuration data points, a dither can be configured with an amplitude and period length. The
amplitude is a relative value to the PWM period length. The dither is applied in cosine form.
Example: PWM with 2-ms period length / 50%
Duty dither with 50-ms period length / 10% amplitude
The duty cycle will "dither" within 50 ms starting at 1.2 ms after 0.8 ms and back again to 1.2 ms.
2x dither amplitude
Period length
Information:
The registers are described in "Dither" on page 92.
Instantaneous value
For each system tick, the current measured value for the current provided by the hardware is published as
the input value.
Measurement range
If the square or arithmetic mean value was selected, the recording duration must also be defined. This
defines how far back the last current value to be included for the calculation lies.
Information:
The registers are described in "Current measurement" on page 93.
Using a configuration entry, the user can define whether the period should be kept synchronous to the
current measurement.
It is possible to establish a time reference from the PWM period to the system tick using a cyclic I/O data
point and thus subsequently to the current measurement cycle (synchronized to the system tick moment).
Information:
The register is described in "Period duration of the PWM outputs" on page 90.
Information:
The registers are described in "Temperature management" on page 95.
3.9.1 Overtemperature
Due to no air circulation, insufficient air circulation or heating resulting from heavy loads on the power
outputs (depending on the number of simultaneously used outputs, current, PWM frequency, etc.), the X90
mobile systems may heat up considerably.
Direct sunlight or external heat sources (e.g. combustion engines) can also have a negative effect on tem-
perature management.
The temperature of the housing can therefore be over 40°C higher than the ambient temperature. It is rec-
ommended to monitor the existing temperature sensors to be able to react in good time if necessary (e.g.
reduction of summation current by lowering the working speed). If the maximum permissible temperature
is exceeded, the system may shut down automatically to prevent damage to the control system.
Information:
The maximum housing temperature is not permitted to be exceeded!
Information:
The registers are described in "Operating management" on page 94.
cfgPWMPeriodxx
This defines the period duration, i.e. the time base for the respective PWM output.
• If "PWM period length source" is configured to this register, the value is applied at the next possible
moment.
• If the phase shift is enabled, the current period is aborted at the moment of application (system tick)
and resumed with the new configuration.
• If the phase shift is disabled, the system resumes with the new period length after the end of the current
period.
cfgPWMOptionsxx
In this register, 3 configuration bits can be reconfigured via the library:
Bit 1: Synchronize period start to current measurement
For details, see "Synchronizing PWM periods to current measurement" on page 61.
• The value is applied at the next possible moment. At the moment of application (system tick), the cur-
rent period is aborted and the next period is started with the new configuration.
Bit 2: Source of the period length
• The value is applied at the next possible moment.
• If the phase shift is enabled, the current period is aborted at the moment of application (system tick)
and resumed with the new configuration.
• If the phase shift is disabled (bit 3), the system resumes with the new period length after the end of
the current period.
Bit 3: Phase shift of the period start time
For details, see "Phase shift" on page 59.
• If the PWM period length source = "PWM period'x'", the configuration is noted but no further actions
are performed.
• If the PWM period length source = "cfgPWMPeriod'x'", the value is applied at the next possible moment.
• At the moment of application (system tick), the current period is aborted and the next period is started
with the new configuration.
cfgPWMDisplacementxx
This allows a more even load to be configured on the outputs.
• If the phase shift is enabled, the current period is aborted at the moment of application (system tick),
the next possible period start is determined with the new configuration and the period is started at
this time.
Information:
To be able to use the LIN interface, it must first be enabled. See "DO and power supply
configuration" on page 95.
Information:
Library "CpLin" is required to use the LIN interface.
Since the application only runs on CPU core "ID 0", more computing time can be created for the application
by offloading I/O tasks to CPU core "ID 1". The increase in computing time gained by offloading depends
on the I/O configuration and ranges from approx. 8 to 30% (default to maximum X1 I/O configuration).
Offloading to the second core increases the response time of the inputs. The response time of the outputs
is not affected by offloading to the second core (ID 1).
Advantages and disadvantages
• Only using CPU core "ID 0"
➯ + Faster evaluation of inputs
➯ - Less computing time for the application
• Using CPU cores "ID 0" and "ID 1"
➯ + More computing time for the application
➯ - Longer response times for inputs
Information:
If POWERLINK is enabled, the POWERLINK cycle time and the system time must be
set to the same value. See "System startup limitation" on page 71.
3.14.1 Inputs
The response time of the inputs is influenced by the "CPU core" I/O configuration.
The input data is evaluated and processed on CPU core "ID 0". Task "tX90io" evaluates the data. This task
also interprets the output values of the application and prepares them for the hardware.
Response time of the inputs
• Minimum: Hardware response time
• Maximum: Hardware response time + 1x system tick cycle time
The hardware input data of the period from the minimum to the maximum response time is used to prepare
the input values of the I/O mapping, such as counters and edge detection, or for the calculation of filters,
current values, etc.
Example (with 1000 µs system tick)
Pin Setting in the I/O configuration Action
1 to 3 Digital input, input filter 0 Levels on pins 1 to 3 change from "Low" to "High".
Task "tX90io" receives all state changes of the input signals or data and processes them for the application.
The I/O scheduler makes the input data available to the tasks via the I/O mapping.
n n+1
System tick
I/O scheduler
tX90io
Evaluation period
Conversion cycle
of current measurement
Pin 1 High
Low
Pin 2 High
Low
Pin 3 High
Low
The input data is evaluated and processed on the second CPU core (ID 1). The evaluation is handled by tasks
"tX90ioIn" and "tX90IoEdge". These tasks are not visible in a profiling since only CPU core "ID 0", which is
essential for the application, is recorded by the Profiler.
On CPU core "ID 0", only the output values of the application are interpreted and prepared for the hardware.
This is executed by task "tX90ioOut".
Response time of the inputs
• Minimum: Hardware response time + 9 x Conversion cycle time of current measurement
• Maximum: Hardware response time + 9 x Conversion cycle time of current measurement + 1 x System
tick cycle time
The hardware input data of the period from the minimum to the maximum response time is used to prepare
the input values of the I/O mapping, such as counters and edge detection, or for the calculation of filters,
current values, etc.
Example (with 1000 µs system tick)
Pin Setting in the I/O configuration Action
1 Digital input, input filter 0 The level on pin 1 changes from "Low" to "High" and drops back to "Low" just before
system tick "n+1".
2 Digital input, input filter 0 The level on pin 2 changes from "Low" to "High".
3 Digital input, input filter 0 The level on pin 3 changes from "Low" to "High".
Tasks "tX90ioln" and "tX90ioEdge" receive all state changes of the input signals or data and process them
for the application. The I/O scheduler makes the input data available to the tasks via the I/O mapping.
n n+1
System tick
I/O scheduler
tX90ioOut
CPU core ID 1
tX90ioIn
tX90ioEdge
Conversion cycle
of current measurement
Pin 1 High
Low
Pin 2 High
Low
Pin 3 High
Low
3.14.2 Outputs
The response time of the outputs is not influenced by the "CPU core" I/O configuration.
Level changes of outputs are performed as soon as possible. The output timing of the output is affected
by events in the runtime system, however, such as interrupts, priority preemption, etc. This can cause jitter
in the output timing of an output from system tick to system tick.
Response time
• 40 to 400 μs + Hardware response time
Example
Pin Configuration Action
31 Digital main output (without parallel output) The process variable assigned to register DigitalOutput25 changes cyclically be-
tween "True" and "False" over several task cycles.
The following diagram shows the possible course of the rising edge on the output over several system
cycles. In relation to the system tick, the output time fluctuates by jitter caused by the runtime system.
Falling edges behave identically.
System tick
I/O scheduler
tX90io / tX90ioOut
Tristate
Low
A level change of a digital main output is always performed with the same offset to the system tick. In the
same way, a PWM period is always started with the same offset to the system tick. A configured phase shift
is also provided with this offset.
This offset is 9.5 conversion cycles of the current measurement. With a system tick of 1 ms, this corresponds
to 380 µs. The offset minimizes the jitter of the output timing of an MF-PWM output from system tick to
system tick. The delay of the hardware must be taken into account, however.
Response time
• 9.5 x Conversion cycle time of current measurement + Hardware response time
The following diagram shows the possible course of the rising edge on the output over several system
cycles. The jitter caused by the runtime system does not affect the output timing of the outputs. Falling
edges behave identically.
System tick
I/O scheduler
tX90io / tX90ioOut
Conversion cycle
of current measurement
Output delay ②
Hardware response time
Pin 39 High
Tristate
Low
Tristate
Low
Tristate
Low
Hardware response time
Pin 42 High
Hardware response time
Tristate
Low
In certain cases, a limitation can occur during startup of the X90 mobile controller, which cannot be pre-
vented due to the system.
System only starting in service mode
Possible causes I/O configuration "CPU core ID 1" is being used, and the POWERLINK cycle time is not equal to the controller cycle time.
Workaround • Use configuration I/O configuration "CPU core ID 0"
or
• Set identical cycle times. For details, see Automation Help.1)
1) For POWERLINK configuration: Communication → POWERLINK → AR configuration → POWERLINK interface configuration (SG4) → Cycle time
For controller configuration: Programming → Editors → Configuration editors → Hardware configuration → CPU configuration → SG4 → CPU prop-
erties - Timing characteristics
4 Register description
Name:
cfgDigitalFilter01 to cfgDigitalFilter60
This register can be used to specify the filter value for all digital inputs in steps of 100 μs. The filter is
implemented as a ramp filter.
Data type Values Information
USINT 0 No software filter
1 0.1 ms
...
10 1 ms (default)
...
250 25 ms - Higher values are limited to this value.
Name:
cfgThreshold11 to cfgThreshold30
cfgHysteresis11 to cfgHysteresis30
The switching threshold with the associated hysteresis is configured in these registers.
Registers cfgThreshold11 to cfgThreshold30:
Data type Values Information
UINT 0 to 31000 Corresponds to 0 to 31000 mV if an absolute switching threshold is configured.
0 to 1000 Corresponds to 0 to 100.0% if a ratiometric switching threshold is configured.
Name:
DigitalInput01 to DigitalInput10
DigitalInput11 to DigitalInput26
DigitalInput27 to DigitalInput30
DigitalInput31 to DigitalInput38
DigitalInput39 to DigitalInput44
DigitalInput45 to DigitalInput60
These registers contain the input states of digital inputs 1 to 60.
Data type Values
USINT See bit structure registers 1113, 2049 and 3074.
UINT See bit structure registers 2, 1026 and 3354.
Bit structure:
Register 2
Bit Description Value Information
0 DigitalInput01 0 or 1 Input status of digital input 01
... ... ... ...
9 DigitalInput101) 0 or 1 Input status of digital input 10
1) Channels 9 and 10 are not available when using the RS232 interface. They always contain value "0".
Register 1026
Bit Description Value Information
0 DigitalInput11 0 or 1 Input status of digital input 11
... ... ... ...
15 DigitalInput26 0 or 1 Input status of digital input 26
Register 1113
Bit Description Value Information
0 DigitalInput27 0 or 1 Input status of digital input 27
... ... ... ...
3 DigitalInput30 0 or 1 Input status of digital input 30
Register 2049
Bit Description Value Information
0 DigitalInput31 0 or 1 Input status of digital input 31
... ... ... ...
7 DigitalInput38 0 or 1 Input status of digital input 38
Register 3074
Bit Description Value Information
0 DigitalInput39 0 or 1 Input status of digital input 39
... ... ... ...
5 DigitalInput44 0 or 1 Input status of digital input 44
Register 3354
Bit Description Value Information
0 DigitalInput45 0 or 1 Input status of digital input 45
... ... ... ...
15 DigitalInput60 0 or 1 Input status of digital input 60
Name:
ShortCircuitDigitalInput11 to ShortCircuitDigitalInput26
ShortCircuitDigitalInput27 to ShortCircuitDigitalInput30
WirebreakDigitalInput11 to WirebreakDigitalInput26
WirebreakDigitalInput27 to WirebreakDigitalInput30
These registers contain the input states of digital input channels 11 to 30.
Data type Values
UINT See bit structure registers 1094 and 1098.
USINT See bit structure registers 1182 and 1186.
Bit structure:
ShortCircuitDigitalInput
Register1094
Bit Description Value Information
0 ShortCircuitDigitalInput11 0 No short circuit
1 Short circuit
... ... ... ...
15 ShortCircuitDigitalInput26 0 No short circuit
1 Short circuit
Register 1182
Bit Description Value Information
0 ShortCircuitDigitalInput27 0 No short circuit
1 Short circuit
... ... ... ...
3 ShortCircuitDigitalInput30 0 No short circuit
1 Short circuit
WirebreakDigitalInput
Register 1098
Bit Description Value Information
0 WirebreakDigitalInput11 0 No open circuit
1 Open circuit
... ... ... ...
15 WirebreakDigitalInput26 0 No open circuit
1 Open circuit
Register 1186
Bit Description Value Information
0 WirebreakDigitalInput27 0 No open circuit
1 Open circuit
... ... ... ...
3 WirebreakDigitalInput30 0 No open circuit
1 Open circuit
Name:
cfgEdgeDetectModeUnit01 to cfgEdgeDetectModeUnit08
These registers configure the mode of the basic function for either just the master edge or both master
and slave edges.
Data type Values Information
USINT 0x00 Disabled
0x80 Reaction to master edge
0xC0 Reaction to master/slave edge
Name:
MasterCount01 to MasterCount08
SlaveCount01 to SlaveCount08
The counter value of detected master and slave edges is stored in these registers. The counter value is used
to detect new measurements.
Data type Values Information
DINT -2,147,483,648 Number of detected master/slave edges
to 2,147,483,647
Name:
cfgEdgeDetectMasterUnit01 to cfgEdgeDetectMasterUnit08
These registers are used to define the source of the master edge for the edge detection unit.
Data type Values Information
USINT 0 Rising edge on channel 1
1 Falling edge on channel 1
2 Rising edge on channel 2
3 Falling edge on channel 2
... ...
14 Rising edge on channel 8
15 Falling edge on channel 8
255 Disabled
Name:
cfgEdgeDetectSlaveUnit01 to cfgEdgeDetectSlaveUnit08
These registers define the source of the slave edge for the edge detection unit.
Data type Values Information
USINT 0 Rising edge on channel 1
1 Falling edge on channel 1
2 Rising edge on channel 2
3 Falling edge on channel 2
... ...
14 Rising edge on channel 8
15 Falling edge on channel 8
255 Disabled
Name:
MasterTime01 to MasterTime08
SlaveTime01 to SlaveTime08
The exact controller system time of the respective edge detection unit is saved to registers MasterTime01
to MasterTime08 when a master edge occurs.
The exact controller system time of a possible previous slave edge is copied to registers SlaveTime01 to
SlaveTime08 when a master edge occurs.
Data type Values Information
DINT -2,147,483,648 System time of the slave/master edge
to 2,147,483,647
Name:
EdgeLostErrorCount
If one or more edges are lost in the last system tick, the value of this register is increased.
Data type Values
INT -32768 to 32767
Name:
EdgeLateErrorcount
This register is incremented if not all edges of the last system tick could be evaluated.
Data type Values
INT -32768 to 32767
Name:
cfgCounterModeUnit01 to cfgCounterModeUnit04
The counter mode can be set for each counter in these registers. For details, see "Counter functions" on
page 47.
Data type Values
USINT See the bit structure.
Bit structure:
Mode value Information
0 Disabled
1 Edge counter of channel 1, 3, 5 or 7
2 Edge counter of channel 2, 4, 6 or 8
3 AB counter on channel 1, 3, 5 or 7
4 DF counter on channel 1 or 5
5 ABR counter on channel 1 or 5
Name:
Counter01 to Counter04
Encoder01 to Encoder04
The current counter values or current encoder values are saved in these registers.
Data type Values Information
INT -32768 to 32767 Current counter value
4.7.3 Counter functions - Clear counter value and enable/disable latch function
Name:
CounterReset01 to CounterReset04
LatchEnable01
LatchEnable03
These registers clear the counter value or start the latch procedure based on the corresponding bit.
Data type Values
USINT See the bit structure.
Bit structure:
Bit Description Value Information
0 CounterReset01 0 Do not clear the counter value
1 Reset the counter
1 CounterReset02 0 Do not clear the counter value
1 Reset the counter
2 CounterReset03 0 Do not clear the counter value
1 Reset the counter
3 CounterReset04 0 Do not clear the counter value
1 Reset the counter
4 LatchEnable01 0 Disabled
1 Enabled
5 Reserved -
6 LatchEnable03 0 Disabled
1 Enabled
7 Reserved -
Name:
Latch01CounterValue
Latch03CounterValue
As soon as the latch conditions have been met, the contents of the respective counter are copied to these
registers.
Data type Values Information
INT -32768 to 32767 Latched counter value
Name:
Latch01EventsCount
Latch03EventsCount
The counter value of the recorded latch events is stored in these registers. This detects whether a new latch
event has been saved. If several latch events occur during a system tick, the counter value is only increased
by 1.
Data type Values Information
INT -32768 to 32767 Latch events that have occurred
Name:
cfgLatchModeUnit01
cfgLatchModeUnit03
These registers determine the states at which the latch registers associated with the counters are applied.
Data type Values
UINT See the bit structure.
Bit structure:
Register cfgLatchModeUnit01
Bit Description Value Information
0 Counter 01: Input 01 high level 0 Disabled
1 Enabled
1 Counter 01: Input 02 high level 0 Disabled
1 Enabled
2 Counter 01: Input 03 high level 0 Disabled
1 Enabled
3 Counter 01: Input 04 high level 0 Disabled
1 Enabled
4 Counter 01: Input 01 low level 0 Disabled
1 Enabled
5 Counter 01: Input 02 low level 0 Disabled
1 Enabled
6 Counter 01: Input 03 low level 0 Disabled
1 Enabled
7 Counter 01: Input 04 low level 0 Disabled
1 Enabled
8 to 15 Latch mode of counter 01 0 Single shot
1 Continuous
2 to 254 Reserved
255 Disabled
Register cfgLatchModeUnit03
Bit Description Value Information
0 Counter 03: Input 05 high level 0 Disabled
1 Enabled
1 Counter 03: Input 06 high level 0 Disabled
1 Enabled
2 Counter 03: Input 07 high level 0 Disabled
1 Enabled
3 Counter 03: Input 08 high level 0 Disabled
1 Enabled
4 Counter 03: Input 05 low level 0 Disabled
1 Enabled
5 Counter 03: Input 06 low level 0 Disabled
1 Enabled
6 Counter 03: Input 07 low level 0 Disabled
1 Enabled
7 Counter 03: Input 08 low level 0 Disabled
1 Enabled
8 to 15 Latch mode of counter 03 0 Single shot
1 Continuous
2 to 254 Reserved
255 Disabled
Name:
cfgAnalogFilter11 to cfgAnalogFilter30
A filter can be defined to prevent large input steps.
Data type Values
USINT See the bit structure.
Bit structure:
Bit Description Value Information
0 to 3 Filter level 0 Disabled (default)
1 Filter level 2
2 Filter level 4
3 Filter level 8
4 Filter level 16
5 Filter level 32
6 Filter level 64
7 Filter level 128
4 to 7 Input ramp limitation 0 Disabled (default)
1 Limit value = 16383
2 Limit value = 8191
3 Limit value = 4095
4 Limit value = 2047
5 Limit value = 1023
6 Limit value = 511
7 Limit value = 255
Name:
cfgAnalogUpperLimit11 to cfgAnalogUpperLimit30
cfgAnalogLowerLimit11 to cfgAnalogLowerLimit30
The lower/upper limit value of the analog value is set in these registers. If the analog value goes above or
below the respective limit value, it is frozen at this value and the corresponding error status bits are set.
Analog input 0 to 20 mA
Data type Values Information
INT 0 to 32767 cfgAnalogUpperLimit: Upper limit value of the associated analog input
cfgAnalogLowerLimit: Lower limit value of the associated analog input
Analog input 4 to 20 mA
Data type Values Information
INT -8192 to 32767 cfgAnalogUpperLimit: Upper limit value of the associated analog input
cfgAnalogLowerLimit: Lower limit value of the associated analog input
Name:
AnalogInput11 to AnalogInput30
Resistor11 to Resistor30
Temperature11 to Temperature30
The analog input value is mapped in these registers depending on the configured operating mode.
Data type Values Information
INT 0 to 32767 0 to 5 VDC 1)
0 to 10 VDC
0 to 32 VDC 2)
0 to 20 mA
-8191 to 32767 4 to 20 mA (-8191 = 0 mA, 0 = 4 mA, 32767 = 20 mA)
-2000 to 8500 temperature measurement (-200 to 850°C)
UINT 1 to 4000 Resistance measurement 1 to 4000 Ω
Name:
UnderflowAnalogInput11 to UnderflowAnalogInput26
UnderflowAnalogInput27 to UnderflowAnalogInput30
OverflowAnalogInput11 to OverflowAnalogInput26
OverflowAnalogInput27 to OverflowAnalogInput30
OutOfRangeAnalogInput11 to OutOfRangeAnalogInput26
OutOfRangeAnalogInput27 to OutOfRangeAnalogInput30
The state of the analog inputs is stored in these registers.
Data type Values
USINT See bit structure registers 1190, 1194 and 1198.
UINT See bit structure registers 1102, 1106 and 1110.
Bit structure:
UnderflowAnalogInput
Register 1102
Bit Description Value Information
0 UnderflowAnalogInput11 0 Limit value not undershot
1 Limit value undershot
... ... ... ...
15 UnderflowAnalogInput26 0 Limit value not undershot
1 Limit value undershot
Register 1190
Bit Description Value Information
0 UnderflowAnalogInput27 0 Limit value not undershot
1 Limit value undershot
... ... ... ...
3 UnderflowAnalogInput30 0 Limit value not undershot
1 Limit value undershot
OverflowAnalogInput
Register 1106
Bit Description Value Information
0 OverflowAnalogInput11 0 Limit value not overshot
1 Limit value overshot
... ... ... ...
15 OverflowAnalogInput26 0 Limit value not overshot
1 Limit value overshot
Register 1194
Bit Description Value Information
0 OverflowAnalogInput27 0 Limit value not overshot
1 Limit value overshot
... ... ... ...
3 OverflowAnalogInput30 0 Limit value not overshot
1 Limit value overshot
OutOfRangeAnalogInput
Register 1110
Bit Description Value Information
0 OutOfRangeAnalogInput11 0 Measured value not outside measurement range
1 Measured value outside measurement range
... ... ... ...
15 OutOfRangeAnalogInput26 0 Measured value not outside measurement range
1 Measured value outside measurement range
Register 1198
Bit Description Value Information
0 OutOfRangeAnalogInput27 0 Measured value not outside measurement range
1 Measured value outside measurement range
... ... ... ...
3 OutOfRangeAnalogInput30 0 Measured value not outside measurement range
1 Measured value outside measurement range
Name:
DigitalOutput31 to DigitalOutput38
DigitalOutput39 to DigitalOutput44
DigitalOutput45 to DigitalOutput60
These registers contain the output state of digital outputs 31 to 60.
Data type Values
USINT See bit structure registers 18433 and 19458.
UINT See bit structure register 19602.
Bit structure:
Register 18433
Bit Description Value Information
0 DigitalOutput31 0 or 1 Output state of digital output 31
... ... ... ...
7 DigitalOutput38 0 or 1 Output state of digital output 38
Register 19458
Bit Description Value Information
0 DigitalOutput39 0 or 1 Output state of digital output 39
... ... ... ...
5 DigitalOutput44 0 or 1 Output state of digital output 44
Register 19602
Bit Description Value Information
0 DigitalOutput45 0 or 1 Output state of digital output 45
... ... ... ...
15 DigitalOutput60 0 or 1 Output state of digital output 60
Name:
ErrorDigitalOutput31 to ErrorDigitalOutput38
ErrorDigitalOutput39 to ErrorDigitalOutput44
ErrorDigitalOutput45 to ErrorDigitalOutput60
These registers contain the state of digital outputs 31 to 60.
Data type Values
USINT See bit structure registers 2051 and 3078.
UINT See bit structure register 3358.
Bit structure:
Register 2051
Bit Description Value Information
0 ErrorDigitalOutput31 0 No error
1 Error
... ... ... ...
7 ErrorDigitalOutput38 0 No error
1 Error
Register 3078
Bit Description Value Information
0 ErrorDigitalOutput39 0 No error
1 Error
... ... ...
5 ErrorDigitalOutput44 0 No error
1 Error
Register 3374
Bit Description Value Information
0 ErrorDigitalOutput45 0 No error
1 Error
... ... ...
15 ErrorDigitalOutput60 0 No error
1 Error
Name:
OverloadDigitalOutput31 to OverloadDigitalOutput38
OverloadDigitalOutput39 to OverloadDigitalOutput44
OverloadDigitalOutput45 to OverloadDigitalOutput60
For additional information, see "Overload" on page 54.
If a pin is configured as DI, then the corresponding bit is not maintained.
Data type Values
USINT See bit structure registers 2059 and 3094.
UINT See bit structure register 3374.
Bit structure:
Register 2059
Bit Description Value Information
0 OverloadDigitalOutput31 0 Not shut down
1 Shut down due to overload
... ... ...
7 OverloadDigitalOutput38 0 Not shut down
1 Shut down due to overload
Register 3094
Bit Description Value Information
0 OverloadDigitalOutput39 0 Not shut down
1 Shut down due to overload
... ... ...
5 OverloadDigitalOutput44 0 Not shut down
1 Shut down due to overload
Register 3374
Bit Description Value Information
0 OverloadDigitalOutput45 0 Not shut down
1 Shut down due to overload
... ... ...
15 OverloadDigitalOutput60 0 Not shut down
1 Shut down due to overload
Name:
cfgStatusFilter31 to cfgStatusFilter60
If the switched output level of an output does not correspond to the read-back value, this is detected as
an error. This configuration register can be used to set how long an error state must be present for the
corresponding error bit to be set.
Data type Values Information
UINT 0 to 65535 Corresponds to 0 to 6553.5 ms, delay time of the error state bit in 0.1 ms.
Name:
cfgOverloadLimitCurrent31 to cfgOverloadLimitCurrent44
cfgOverloadLimitCurrent45 to cfgOverloadLimitCurrent60
The maximum current value that should be used for limiting (absolute value) is set in these registers.
For additional information, see "Overload protection" on page 55.
Data type Values Information
UINT 0 to 4000 Channels 31 to 44: Corresponds to 0 to 4000 mA (+5% or +12.5%).
0 to 6000 Channels 45 to 60: Corresponds to 0 to 6000 mA (+5% or +12.5%)
Name:
OverloadClear31 to OverloadClear38
OverloadClear39 to OverloadClear44
OverloadClear45 to OverloadClear60
For additional information, see "Overload" on page 54.
Data type Values
USINT See bit structure registers 18435 and 19462.
UINT See bit structure register 19606.
Bit structure:
Register 18435
Bit Description Value Information
0 OverloadClear31 0 No acknowledgment
1 Acknowledges the overcurrent error
... ... ... ...
7 OverloadClear38 0 No acknowledgment
1 Acknowledges the overcurrent error
Register 19462
Bit Description Value Information
0 OverloadClear39 0 No acknowledgment
1 Acknowledges the overcurrent error
... ... ... ...
5 OverloadClear44 0 No acknowledgment
1 Acknowledges the overcurrent error
Register 19606
Bit Description Value Information
0 OverloadClear45 0 No acknowledgment
1 Acknowledges the overcurrent error
... ... ... ...
15 OverloadClear60 0 No acknowledgment
1 Acknowledges the overcurrent error
Name:
AnalogOutput19 to AnalogOutput26
The ratiometric output value of the respective analog output is specified in these registers.
Data type Values Information
UINT 0 to 32767 Corresponds to 0 to 100% of the supply voltage
Name:
PVGDuty19 to PVGDuty26
The ratio of the duty cycle of the respective PVG output in relation to the period duration is set in these
registers.
Data type Values Information
UINT 0 to 32767 Duty cycle of the output in 0 to 100%
Name:
PVGStatus19 to PVGStatus26
The bits of this register are set if the feedback voltage is not within the range of ±20% of the duty cycle 10
ms (ramp filter) after a PVG change.
Data type Values
UINT See the bit structure.
Bit structure:
Bit Description Value Information
8 PVGStatus19 0 Feedback voltage OK
1 Feedback voltage out of range
... ... ... ...
15 PVGStatus26 0 Feedback voltage OK
1 Feedback voltage out of range
Name:
OutputEnable19 to OutputEnable26
Register "OutputEnable" is only needed for the channels that are configured as outputs.
The individual bits are used to switch the respective channels on/off. The respective bit is only evaluated
if it has been configured as a PVG or analog output.
Data type Values
UINT See the bit structure.
Bit structure:
Register 17474
Bit Name Value Information
8 OutputEnable19 0 Channel 19 output disabled
1 Output enabled (high/low)
... ... ... ...
15 OutputEnable26 0 Channel 26 output disabled
1 Output enabled (high/low)
Name:
PWMPeriod39 to PWMPeriod60
cfgPWMPeriod39 to cfgPWMPeriod60
These registers define the period duration, i.e. the time base for the respective PWM output. This time
represents the 100% value, which can be incremented in 0.1% steps through the duty cycle.
"PWM" configuration
Mode "Synchronous period"
Data type Values Information
UINT 1 to 239 Period duration 240 µs
240 to 65535 Period duration in microseconds
Name:
PWMOutput39 to PWMOutput60
The ratio of the duty cycle of the respective PWM output in relation to the period duration is set in these
registers.
Data type Values Information
INT -32768 to 32767 Duty cycle of the output in -100 to 100%
Name:
cfgPWMOptions39 to cfgPWMOptions60
Data type Values
USINT See the bit structure.
Bit structure:
Bit Name Value Information
0 Evaluate bit from cyclic I/O data point "OutputEnable" 0 Disabled
1 Enabled
1 Synchronize PWM period start for current measurement 0 Disabled = Asynchronous period
1 Enabled = Synchronous period
2 PWM period length source 0 "PWMPeriod'x'"
1 "cfgPWMPeriod'x'"
3 Phase shift of the PWM period start 0 Disabled
1 Enabled
4 to 7 Reserved -
Bit 1:
For additional information, see "Synchronizing PWM periods to current measurement" on page 61.
Bit 2:
The source of the period length is configured here.
Bit 3:
For information about the phase shift of the period start times, see "Phase shift" on page 59.
Name:
cfgPWMDisplacement39 to cfgPWMDisplacement60
In order to give the user the possibility to distribute load currents "more evenly", it is possible to set a phase
shift.
Data type Values Information
UINT 0 to 15 Corresponds to 0 to 65535 µs, phase shift of the PWM period start of MF-PWM pin "x"
Name:
OutputEnable39 to OutputEnable44
Register "OutputEnable" is only needed for the channels that are configured as outputs.
The individual bits are used to switch the respective channels on/off. The respective bit is only evaluated
if it has been enabled with configuration register cfgPWMOptions bit 0 and the pin has been configured
as PWM or digital output.
Data type Values
USINT See the bit structure.
Bit structure:
Bit Name Value Information
0 OutputEnable39 0 Output channel 39 disabled (tristate)
1 Output enabled (high/low)
... ... ... ...
5 OutputEnable44 0 Output channel 44 disabled (tristate)
1 Output enabled (high/low)
Name:
PWMPeriodReal39 to PWMPeriodReal44
Data type Values Information
UINT 0 to 65535 Corresponds to 0 to 65535 µs, actual period [µs] of the PWM output on MF-PWM pin "x"
For additional information, see "Synchronizing PWM periods to current measurement" on page 61.
Name:
PWMPeriodStartTime39 to PWMPeriodStartTime44
Data type Values Information
UINT -2,147,483,648 System time of the last period start before the system tick [µs] of MF-PWM pin "x".
to 2,147,483,647
For additional information, see "Synchronizing PWM periods to current measurement" on page 61.
4.11.8 Dither
Using two configuration data points, a dither can be configured with an amplitude and period length.
Name:
DitherDisable39 to DitherDisable44
DitherDisable45 to DitherDisable60
Data type Values
USINT See bit structure register 19598.
UINT See bit structure register 19738.
Bit structure:
Register 19598
Bit Name Value Information
0 DitherDisable39 0 Enable dither
1 Disabling dither
... ... ... ...
5 DitherDisable44 0 Enable dither
1 Disabling dither
Register 19738
Bit Name Value Information
0 DitherDisable45 0 Enable dither
1 Disabling dither
... ... ... ...
15 DitherDisable60 0 Enable dither
1 Disabling dither
Name:
cfgDitherAmplitude39 to cfgDitherAmplitude60
Data type Values Information
UINT 0 to 255 Corresponds to 0 to 25.5% of the PWM period length, dither amplitude of MF-PWM pin "x"
Name:
cfgDitherPeriod39 to cfgDitherPeriod60
Data type Values Information
UINT 0 Corresponds to 0 µs, dither period length of MF-PWM pin "x"
1 to 999 Corresponds to 1000 µs, dither period length of MF-PWM pin "x"
1000 to 65535 Corresponds to 1000 to 65535 µs, dither period length of MF-PWM pin "x"
Name:
Current31 to Current38
These registers contain the analog measured current value of the MF-DO power outputs measurement
range 0 to 20 A.
1 LSB of the INT value corresponds to 610 µA.
Data type Values Information
INT 0 to 32767 Measured current
Name:
Current39 to Current60
These registers contain the analog current measured value of the MF PWM power outputs:
• Channels 39 to 44: -10 to 10 A
• Channels 45 to 60: 0 to 10 A
1 LSB of the INT value corresponds to 305 µA.
Data type Values Information
INT -32768 to 32767 Measured current
Reading
Name:
CurrentOverloadShutdown
StatusSensorSupply
OutputEnabled
StatusIgnition
OutputReleased
SensorSupplyErr
Data type Values
USINT See the bit structure.
Bit structure:
Bit Description Value Information
0 to 1 Reserved -
2 CurrentOverloadShutdown 0 No error
1 All outputs cut off (overcurrent)
3 StatusSensorSupply 0 Error in sensor power supply
1 Sensor power supply OK
4 OutputEnabled 0 Disables external enabling
1 Enables external enabling
5 StatusIgnition 0 Ignition plus off
1 Ignition plus on
6 OutputReleased 0 Enable relay not activated
1 Enable relay activated
7 SensorSupplyErr1) 0 Error occurred in the sensor power supply (must be ac-
knowledged)
1 Sensor power supply OK
Writing
Name:
CurrentOverloadShutdownClear
OutputEnable
SensorSupplyErrClear
Data type Values
USINT See the bit structure.
Bit structure:
Bit Description Value Information
0 to 1 Reserved -
2 CurrentOverloadShutdownClear 0 -
1 Rising edge:
Digital outputs are re-enabled after summation current
monitoring is disabled.
3 OutputEnable 0 Outputs disabled
1 Outputs enabled
4 SensorSupplyErrClear1) 0 -
1 The sensor power supply is switched on again after the au-
tomatic switch-off due to an error.
5 to 7 Reserved -
Name:
TotalCurrentPositiv
TotalCurrentNegativ
These data points return the sum of the positive/negative currents of the output pins. The total currents
are arithmetically averaged over 500 ms.
Data type Values Measured current
INT 0 to 32767 0 to 45 A
Name:
SupplyVoltageOutput01, SupplyVoltageOutput02
SupplyVoltageCPU
These data points return the measured supply voltages.
Data type Values Measured voltage
INT 0 to 32767 0 to 40 V
Name:
SupplyVoltageSensor01
These data points return the measured sensor voltage.
Data type Values Measured voltage
INT 0 to 32767 0 to 11 V
Name:
cfgOpMgmt_Mode
Data type Values
USINT See the bit structure.
Bit structure:
Bit Description Value Information
0 Voltage selection of sensor power supply 01 0 5 V sensor power supply
1 10 V sensor power supply
1 Activate data point enable 0 Enabling the outputs is controlled externally.
1 Enabling the outputs is controlled by data point "OutputEn-
able" and externally.
2 Enable sensor power supply 0 Enabled
1 Disabled
3 Enable LIN power supply 0 Enabled
1 Disabled
4 to 7 Reserved -
Name:
ReleasePinVoltage
These data points provide the measured voltage on the enable line.
Data type Values Measured voltage
INT 0 to 32767 0 to 40 V
4.14.1 TemperatureCPU
Name:
TemperatureCPU
The internal temperature of the CPU can be read from this data point.
The temperature is not permitted to exceed 120°C.
Data type Values Information
INT -32768 to 32767 Temperature in 1/10°C
4.14.2 TemperatureENV1
Name:
TemperatureENV1
The temperature of the memory module on the mainboard can be read from this data point.
The temperature is not permitted to exceed 125°C.
Data type Values Information
INT -32768 to 32767 Temperature in 1/10°C
4.14.3 TemperatureENV2
Name:
TemperatureENV2
This data point can be used to read the temperature of the printed circuit board in the are of the processors.
The temperature is not permitted to exceed 95°C. Exceeding this results in automatic shutdown of the
system. After the controller has cooled down by at least 10°C, the system starts up again and sets a logbook
entry.
Data type Values Information
INT -32768 to 32767 Temperature in 1/10°C
Standard operation
No
Temperature
≥ 95°C
Yes
Overtemperature
Restart
shutdown
No
Temperature Generating
< 85°C logbook entry
Yes
4.14.4 TemperatureENV3
Name:
TemperatureENV3
The temperature of the main relay can be read from this data point.
The temperature is not permitted to exceed 125°C.
Data type Values Information
INT -32768 to 32767 Temperature in 1/10°C
4.14.5 TemperatureENV4
Name:
TemperatureENV4
The temperature near connector X1.B can be read from this data point.
The temperature is not permitted to exceed 125°C.
Data type Values Information
INT -32768 to 32767 Temperature in 1/10°C