Digital VLSI Design

Lecture 3: Logic Synthesis

Part 1
Semester A, 2018-19
Lecturer: Dr. Adam Teman
November 7, 2018

Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited;
however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed,
please feel free to email [email protected] and I will address this as soon as possible.
 Lecture Outline

2 © Adam Teman, 2018

 1 2 3 4 5 6
Introduction Compilation Library Def. LEF Liberty Other

Syntax
Analysis
Library
Definition
Elaboration
and Binding
Pre-mapping
Optimization

Introduction
Constraint
Definition
Technology
Mapping

…what is logic synthesis? Post-mapping

Optimization
Report and
export
 What is Logic Synthesis? module counter(
input clk, rstn, load,
input [1:0] in,
• Synthesis is the process that converts RTL into a technology- output reg [1:0] out);
always @(posedge clk)
specific gate-level netlist, optimized for a set of pre-defined if (!rstn) out <= 2'b0;
constraints. tối ưu hóa cho 1 tập hợp các ràng buộc được xác định trước else if (load) out <= in;
else out <= out + 1;
• You start with: endmodule
• A behavioral RTL design

Synthesis
• A standard cell library Standard Cell Library
• A set of design constraints Design Constraints
ràng buộc
• You finish with: danh sách các cổng logic và kết nối giữa chúng
• A gate-level netlist, mapped to the module counter ( clk, rstn, load, in, out );
input [1:0] in;
standard cell library ánh xạ vào thư viện standard cell output [1:0] out;
input clk, rstn, load;
• (For FPGAs: LUTs, flip-flops, and RAM blocks) wire N6, N7, n5, n6, n7, n8;

• Hopefully, it’s also efficient in terms of speed, FFPQ1 out_reg_1 (.D(N7),.CK(clk),.Q(out[1]));

FFPQ1 out_reg_0 (.D(N6),.CK(clk),.Q(out[0]));
area, power, etc. Hiệu suất, diện tích và tiết kiệm năng lượng NAN2D1 U8 (.A1(out[0]),.A2(n5),.Z(n8));
NAN2D1 U9 (.A1(n5),.A2(n7),.Z(n6));
INVD1 U10 (.A(load),.Z(n5));
OA211D1 U11 (.A1(in[0]),.A2(n5),.B(rstn),.C(n8),.Z(N6));
OA211D1 U12 (.A1(in[1]),.A2(n5),.B(rstn),.C(n6),.Z(N7));
EXNOR2D1 U13 (.A1(out[1]),.A2(out[0]),.Z(n7));

© Adam Teman, 2018

endmodule
4
 What is Logic Synthesis?
• Given: Finite-State Machine F(X, Y, Z, λ, δ)
where: chuyển đổi FSM thành 1 mạch logic được tối ưu hóa
• X: Input alphabet
• Y: Output alphabet
• Z: Set of internal states
• λ: X × Z → Z (next state function)
• δ: X × Z → Y (output function)
Phân tích FSM => ánh xạ FSM vào mạch logic => tối ưu hóa mạch logic => kiểm tra và xác nhận

• Target: Circuit C(G, W) where:

• G: set of circuit components
G = {Boolean gates, flip-flops, etc.}
• W: set of wires connecting G

5 © Adam Teman, 2018

 Motivation
thực hiện
• Why perform logic synthesis?
• Automatically manages many details of the design process:
• Fewer bugs
• Improves productivity trừu tượng hóa mô tả thiết kế từ ngôn ngữ mô tả phần cứng (HDL) so với bất kỳ công nghệ cụ thể nào.
• Abstracts the design data (HDL description) from any particular implementation technology
• Designs can be re-synthesized targeting different chip technologies;
• E.g.: first implement in FPGA then later in ASIC tái tổ chức dễ dàng vào các công nghệ chip khác

• In some cases, leads to a more optimal design than could be achieved by

manual means (e.g.: logic optimization) tối ưu hóa logic, giảm diện tích, tối ưu độ trễ, tối ưu năng lượng tiêu thụ

• Why not logic synthesis?

• May lead to less than optimal designs in some cases
Có thể mất đi khả năng tinh chỉnh và tối ưu hóa thủ công của mạch, đặc biệt là đối với các thiết kế đặc biệt phức tạp hoặc đòi hỏi kiến thức
chuyên sâu về kiến trúc mạch.

6 © Adam Teman, 2018

Simple Example
module foo (a,b,s0,s1,f);
input [3:0] a;
input [3:0] b;
input s0,s1;
output [3:0] f;
reg f;

always @ (a or b or s0 or s1)
if (!s0 && s1 || s0)
f=a;
else
f=b;
endmodule

© Adam Teman, 2017

 Goals of Logic Synthesis
• Minimize area
• In terms of literal count, cell count, register count, etc.
• Minimize power
• In terms of switching activity in individual gates,
deactivated circuit blocks, etc.
• Maximize performance
• In terms of maximal clock frequency of synchronous
systems, throughput for asynchronous systems
• Any combination of the above
• Combined with different weights
• Formulated as a constraint problem
• “Minimize area for a clock speed > 300MHz”
• More global objectives
• Feedback from layout
• Actual physical sizes, delays, placement and routing
8 © Adam Teman, 2018
 How does it work?
Variety of general and ad-hoc (special case) methods:
• Instantiation:
• Maintains a library of primitive modules (AND, OR, etc.) and user defined modules
• “Macro expansion”/substitution:
• A large set of language operators (+, -, Boolean operators, etc.)
and constructs (if-else, case) expand into special circuits
• Inference:
• Special patterns are detected in the language description and treated specially
(e.g.,: inferring memory blocks from variable declaration and read/write statements, FSM detection
and generation from always@(posedge clk) blocks)
• Logic optimization:
• Boolean operations are grouped and optimized with logic minimization techniques
• Structural reorganization:
• Advanced techniques including sharing of operators, and retiming of circuits (moving FFs), and
others
9 © Adam Teman, 2018
 Basic Synthesis Flow
Syntax Analysis

• Syntax Analysis: Library Definition

• Read in HDL files and check for syntax errors.
read_hdl –verilog sourceCode/toplevel.v Elaboration and
Binding
• Library Definition:
• Provide standard cells and IP Libraries.
Constraint Definition
read_libs “/design/data/my_fab/digital/lib/TT1V25C.lib”

• Elaboration and Binding:

• Convert RTL into Boolean structure.
• State reduction, encoding, register infering.
• Bind all leaf cells to provided libraries.
elaborate toplevel

• Constraint Definition:
• Define clock frequency and other design constraints.
read_sdc sdc/constraints.sdc

10 © Adam Teman, 2018

 Basic Synthesis Flow
Syntax Analysis

• Pre-mapping Optimization: Library Definition

• Map to generic cells and perform additional heuristics.
syn_generic Elaboration and
Binding
• Technology Mapping:
• Map generic logic to technology libraries.
Constraint Definition
syn_map

• Post-mapping Optimization: Pre-mapping

• Iterate over design, changing gate sizes, Boolean literals, Optimization
architectural approaches to try and meet constraints.
syn_opt Technology Mapping
• Report and export
• Report final results with an emphasis on timing reports. Post-mapping
report timing –num paths 10 > reports/timing_reports.rpt Optimization

• Export netlist and other results for further use.

Report and export
write_hdl > export/netlist.v
11 © Adam Teman, 2018
 1 2 3 4 5 6
Introduction Compilation Library Def. LEF Liberty Other

Syntax
Analysis
Library
Definition
Elaboration
and Binding
Pre-mapping
Optimization

Compilation
Constraint
Definition
Technology
Mapping

…but aren’t we talking about synthesis? Post-mapping

Optimization
Report and
export
 Syntax
Analysis

Compilation in the synthesis flow Library

Definition
Elaboration
and Binding

• Before starting to synthesize, Pre-mapping

Optimization
we need to check the syntax for correctness. Constraint
Definition
• Synthesis vs. Compilation: Technology
Mapping
• Compiler Post-mapping
• Recognizes all possible constructs in a formally defined program language Optimization
Report and
• Translates them to a machine language representation export
of execution process
• Synthesis
• Recognizes a target dependent subset of a hardware
description language
• Maps to collection of concrete hardware resources
• Iterative tool in the design flow

13 © Adam Teman, 2018

 Syntax
Analysis

Compilation with NC-Verilog Library

Definition
Elaboration
and Binding

• To compile your Verilog code for syntax checking, Pre-mapping

Optimization
use the NC-Verilog tool: Constraint
Definition
ncvlog <filename.v> Technology
Mapping
• This will quickly run compilation on your Verilog source code Post-mapping
and point you to syntax errors. Optimization
Report and
• Alternatively, use the irun super command: export

irun -compile <filename.v>

14 © Adam Teman, 2018

 1 2 3 4 5 6
Introduction Compilation Library Def. LEF Liberty Other

Syntax
Analysis
Library
Definition
Elaboration
and Binding
Pre-mapping
Optimization

Library Definition
Constraint
Definition
Technology
Mapping
Post-mapping
Optimization
Report and
export

15
 Syntax
Analysis

It’s all about the standard cells… Library

Definition
Elaboration
and Binding

• The library definition stage tells the synthesizer where to look for Pre-mapping
Optimization
leaf cells for binding and the target library for technology mapping. Constraint
Definition
• We can provide a list of paths to search for libraries in: Technology
Mapping
set_db init_lib_search_path “/design/data/my_fab/digital/lib/”
Post-mapping
• And we have to provide the name of a specific library, Optimization
Report and
usually characterized for a single corner: export

read_libs “TT1V25C.lib”

• We also need to provide .lib files for IPs,

such as memory macros, I/Os, and others.

Make sure you understand all the warnings about the libs that the
synthesizer spits out, even though you probably can’t fix them.

16 © Adam Teman, 2018

 Syntax
Analysis

But what is a library? Library

Definition
Elaboration
and Binding

• A standard cell library is a collection of well defined and appropriately Pre-mapping

Optimization
characterized logic gates that can be used to implement a digital design. Constraint
Definition
• Similar to LEGO, standard cells must meet predefined specifications to Technology

be flawlessly manipulated by synthesis, place, and route algorithms.

Mapping
Post-mapping
Optimization
• Therefore, a standard cell library is Report and

delivered with a collection of files

export

that provide all the information needed

by the various EDA tools.

17 © Adam Teman, 2018

 Syntax
Cell Width Analysis

Example Library
Definition
Elaboration
and Binding

• NAND standard cell layout Pre-mapping

Optimization

• Pay attention to: Constraint

Definition

• Cell height Technology

Mapping
•

Cell Height
Cell width Post-mapping
Optimization
• Voltage rails Report and
• Well definition export

• Pin Placement
• PR Boundary
• Metal layers

Ideally, Standard Cells should

be routed entirely in M1 !

18 © Adam Teman, 2018

 Syntax
Analysis

What cells are in a standard cell library? Library

Definition
Elaboration
• Combinational logic cells (NAND, NOR, INV, etc.): and Binding
Pre-mapping
• Variety of drive strengths for all cells. Optimization
• Complex cells (AOI, OAI, etc.) Constraint
• Fan-In <= 4 Definition

• ECO Cells Technology

Mapping

• Buffers/Inverters AND-OR Post-mapping

Optimization
• Larger variety of drive strengths. INVERT
Report and
• “Clock cells” with balanced rise and fall delays. (AOI) export

• Delay cells
• Level Shifters
• Sequential Cells:
• Many types of flip flops: pos/negedge, set/reset, Q/QB, enable
• Latches
• Integrated Clock Gating cells
• Scan enabled cells for ATPG.
• Physical Cells:
19 • Fillers, Tap cells, Antennas, DeCaps, EndCaps, Tie Cells © Adam Teman, 2018
 Syntax
Analysis

Multiple Drive Strengths and VTs Library

Definition
Elaboration
and Binding

• Multiple Drive Strength Pre-mapping

Optimization
• Each cell will have various sized output stages. Constraint
• Larger output stage → Definition
Technology
better at driving fanouts/loads. Mapping

• Smaller drive strength → Post-mapping

Optimization
less area, leakage, input cap. Report and
• Often called X2, X3, or D2, D3, etc. export

• Multiple Threshold (MT-CMOS)

• A single additional mask can provide more or less doping
in a transistor channel, shifting the threshold voltage.
• Most libraries provide equivalent cells with
three or more VTs: SVT, HVT, LVT
This enables tradeoff between speed vs. leakage.
• All threshold varieties have same footprint and therefore
can be swapped without any placement/routing iterations.
20 © Adam Teman, 2018
 Syntax
Analysis

Clock Cells Library

Definition
Elaboration
and Binding

• General standard cells are optimized for speed. Pre-mapping

Optimization
• That doesn’t mean they’re balanced… Constraint

 tp,LH + tp,HL  Definition

min tpd = min    tp,LH = tp,HL Technology

Mapping
• This isn’t good for clock nets…  2  Post-mapping
Optimization
• Unbalanced rising/falling delays will result in unwanted skew. Report and
• Special “clock cells” are designed with balanced rising/falling delays to export

minimize skew.
• These cells are usually less optimal for data and so should not be used.
• In general, only buffers/inverters should be used on clock nets
• But sometimes, we need gating logic.
• Special cells, such as integrated clock gates,
provide logic for the clock networks.

21 © Adam Teman, 2018

 Syntax
Analysis

Sequentials Library
Definition
Elaboration
and Binding

• Flip Flops and Latches, including Pre-mapping

Optimization
• Positive/Negative Edge Triggered Constraint
Definition
• Synchronous/Asynchronous Reset/Set Technology

• Q/QB Outputs Mapping

Post-mapping
• Enable Optimization

•
Report and
Scan export

• etc., etc.

22 © Adam Teman, 2018

 Syntax
Analysis

Level Shifters Library

Definition
Elaboration
and Binding

• Level shifter cells are placed between voltage domains to pass Pre-mapping
Optimization
signals from one voltage to another. Constraint
Definition
VDDH Technology
Mapping

• HL (high-to-low) shifter Post-mapping

Optimization
• Requires only one voltage INH OUTH
Report and
export
• Single height cell VDDH
VSS

• LH (low-to-high) shifter
OUTH

• Needs 2 voltages
VSS
• Often double height
INL

VDDL

23 © Adam Teman, 2018

 Syntax
Analysis

Filler and Tap Cells Library

Definition
Elaboration

• Filler cells Must be inserted in empty areas in rows and Binding

Pre-mapping
• Ensure well and diffusion mask continuity Optimization

• Ensure density rules on bottom layers Constraint

Definition
• Provide dummy poly for scaled technologies Technology
• Sometimes, special cells are needed at the Mapping
Post-mapping
boundaries of rows - “End Caps” Optimization

• Other fillers may include MOSCAPs Report and

export
between VDD and GND for voltage stability - “DeCAP cells”
• Well Taps needed to ensure local body voltage
• Eliminate latch-up
• No need to tap every single cell
• Back or forward biasing for performance/leakage optimization
• N-well voltage different from VDD
• Substrate or P-well (triple well process) voltage different from VSS
• Bias voltage routed as signal pin or special power net
24 © Adam Teman, 2018
 Syntax
Analysis

Engineering Change Order (ECO) Cells Library

Definition
Elaboration
and Binding

• An Engineering Change Order (ECO) is a very late change in the design. Pre-mapping
Optimization
• ECOs usually are done after place and route. Constraint
• However, re-spins of a chip are often done without Definition

recreating all-masks. This is known as a “Metal-Fix”. Technology

Mapping

• ECOs usually require small changes in logic. Post-mapping

Optimization
• How can we do this after placement? Report and
• Or worse – after tapeout??? export

• Solution – Spare (Bonus) Cells!

• Cells without functionality
• Cells are added during design (fill)
• In case of problems (after processing) new metal
and via mask → cells get their wanted functionality
• Cell combinations can create more complex functions
• Ex. AND,NAND,NOR,XOR,FF,MUX,INV,..
• Special standard cells are used to differentiate from real cells.
25 © Adam Teman, 2018
 Syntax
Analysis

My favorite word… ABSTRACTION! Library

Definition
Elaboration
and Binding

• So, what is a cell? Pre-mapping

Optimization

• I guess that the detailed layout is sufficient to know (guess) Constraint

Definition
anything and everything about a standard cell. Technology

• Or it would be easier, if we got the whole

Mapping
Post-mapping
Open Access database of the cell… Optimization

• But do we really need to know everything?

Report and
export

• For example, does logic simulation need to know

if your inverter is CMOS or Pseudo-NMOS?
• And does a logic synthesizer need to know
what type of transistors you used?
• No!
• To make life (and calculations) simpler, we will abstract away this info.
• Each tool will get only the data it really needs.
26 © Adam Teman, 2018
 Syntax
Analysis

What files are in a standard cell library? Library

Definition
Elaboration
and Binding
• Behavioral Views: Behavioral (.v) Pre-mapping

• Verilog (or Vital) description used for simulation, Optimization

Constraint
logic equivalence. Abstract (.lef) Definition

• Physical Views: Technology

Mapping
• Layout of the cells (GDSII format) for DRC, LVS, Custom Layout. Layout (.gds)
Post-mapping
• Abstract of the cells (LEF format) for P&R, RC extraction. Optimization

• Transistor Level: Spice (.spi, .cdl)

Report and
export
• Spice/Spectre netlist for LVS, transistor-level simulation.
• Often provided both with parasitics (post-layout) and without. Timing (.lib)
• Timing/Power:
• Liberty files with characterization of timing and power for STA.
• Power Grid Views:
• Needed for IR Drop analysis.
Open Access (.oa)
• Others:
• Symbols for displaying the cells in various tools.
27
• OA Libraries for easy integration with Virtuoso. © Adam Teman, 2018
 1 2 3 4 5 6
Introduction Compilation Library Def. LEF Liberty Other

Syntax
Analysis
Library
Definition
Elaboration
and Binding
Pre-mapping
Optimization
Constraint

Library Exchange Format (LEF)

Definition
Technology
Mapping
Post-mapping
Optimization
Report and
export
 Library Exchange Format (LEF)
VDD
• Abstract description of the layout for P&R
A B
• Readable ASCII Format.
• Contains detailed PIN information for
Y Layout View
connecting.
• Does not include front-end of the line
(poly, diffusion, etc.) data.
GND
VDD
• Abstract views only contain the following:
• Outline of the cell (size and shape) A B Metal
• Pin locations and layer (usually on M1) Pins
• Metal blockages Y
(Areas in a cell where metal of a certain Abstract View
layer is being used, but is not a pin)
NAND_1
29
GND © Adam Teman, 2018
 Syntax
Analysis

Library Exchange Format (LEF) Library

Definition
Elaboration
and Binding
Pre-mapping
Optimization
Constraint
Definition
Technology
Mapping
Post-mapping
Optimization
Report and
export

30 © Adam Teman, 2018

 Syntax
Analysis

Technology LEF Library

Definition
Elaboration
and Binding
• Technology LEF Files contain (simplified) information about Pre-mapping

the technology for use by the placer and router: SITE CORE Optimization
Constraint
CLASS CORE;
• Layers SIZE 0.2 X 12.0;
Definition

• Name, such as M1, M2, etc. END CORE Technology

Mapping
• Layer type, such as routing, cut (via) LAYER MET1 Post-mapping
• Electrical properties (R, C) TYPE ROUTING ; Optimization
PITCH 3.5 ;
• Design Rules WIDTH 1.2 ;
Report and
export
• Antenna data SPACING 1.4 ;
DIRECTION HORIZONTAL ;
• Preferred routing direction RESISTANCE RPERSQ .7E-01 ;
• SITE (x and y grid of the library) CAPACITANCE CPERSQDIST .46E-04 ;
• CORE sites are minimum standard cell size END MET1

• Can have site for double height cells! LAYER VIA

TYPE CUT ;
• IOs have special SITE. END VIA
• Via definitions
• Units Additional files provide parasitic extraction rules. These can be
• Grids for layout and routing basic (“cap tables”) or more detailed (“QRC techfile). These
31
may be provided as part of the PDK. Teman, 2018
© Adam
 VDD Syntax
Analysis

Technology LEF W1
Library
Definition
Elaboration
and Binding

• Cell height is measured in Tracks W4

Pre-mapping
Optimization
• A Track is one M1 pitch Constraint
W3 Definition
• E.g., An 8-Track Cell has room for W2
H
Technology
8 horizontal M1 wires. Mapping
Post-mapping
• The more tracks, the wider the Optimization

transistors, the faster the cells.

Report and
export

• 7-8 low-track libraries for area W1

efficiency VSS

• 11-12 tall-track libraries for

Parameter Symbol
performance, but have high leakage
Cell height (# tracks) H
• 9-10 standard-track libraries for a Power rail width W1
reasonable area-performance tradeoff Vertical grid W2
Horizontal grid W3
N-Well height W4
32 © Adam Teman, 2018
 Syntax
Analysis

Technology LEF Library

Definition
Elaboration
Cell and Binding

• Cells must fit into a predefined grid Origin Pre-mapping

Optimization
• The minimum Height X Width Constraint
Definition
is called a SITE. Technology
• Must be a multiple of the minimum PR Mapping
Boundary Post-mapping
X-grid unit and row height. Optimization

• Cells can be double-height, for example. Report and

export
Horizontal
• Pins should coincide with routing tracks Grid

• This enables easy connection of higher

metals to the cell. Vertical
Grid

SITE CORE
CLASS CORE;
SYMMETRY X Y;
SIZE 0.2 X 12.0;
END CORE

33 © Adam Teman, 2018

The Chip Hall of Fame
• After checking out two Intel chips, we better not forget

wikichip.org

• Racking up Kahoot points on your smartphone?

Then you probably should pay tribute to the granddaddy of that chip inside.
• Release date: April 1985 Manufactured by VLSI Technology
• Transistor Count: 25,000 Process: 3 um CMOS
• 32-bit ARMv1 architecture
• ARM stands for “Acorn RISC Machine”
• The reference design was written in 808 lines of BASIC!
• Never sold as a commercial product, but as a co-processor for BBC Micro.
2017 Inductee to the IEEE Chip Hall of Fame
 1 2 3 4 5 6
Introduction Compilation Library Def. LEF Liberty Other

Syntax
Analysis
Library
Definition
Elaboration
and Binding
Pre-mapping
Optimization
Constraint

Liberty Timing Models (.lib)

Definition
Technology
Mapping
Post-mapping
Optimization
Report and
export
 Syntax
Analysis

Liberty (.lib): Introduction Library

Definition
Elaboration
and Binding

• How do we know the delay through a gate in a logic path? Pre-mapping

Optimization
• Running SPICE is way too complex. Constraint
Definition
• Instead, create a timing model that will simplify the calculation. Technology
Mapping
• Goal: Post-mapping
Optimization
• For every timing arc, calculate:
tpd Report and
• Propagation Delay (tpd) export

• Output transition (trise, tfall)

• Based on:
• Input net transition (trise, tfall) tf
• Output Load Capacitance (Cload)

Note that every .lib will provide timing/power/noise information for a

single corner, i.e., process, voltage, temperature, RCX, etc.
36 © Adam Teman, 2018
 Syntax
Analysis

Liberty (.lib): General Library

Definition
Elaboration
library (nameoflibrary) { and Binding

• Timing data of standard cells is ... /* Library level simple and complex attributes */
Pre-mapping
Optimization
provided in the Liberty format.
/* Cell definitions */
cell (cell_name) { Constraint
... /* cell level simple attributes */ Definition
• Library: /* pin groups within the cell */ Technology
• General information common to pin(pin_name) { Mapping
... /* pin level simple attributes */
all cells in the library. Post-mapping
Optimization
• For example, operating conditions, /* timing group within the pin level */
timing(){ Report and
wire load models, look-up tables ... /* timing level simple attributes */ } export
... /* additional timing groups */
• Cell:
} /* end of pin */
• Specific information about each ... /* more pin descriptions */
} /* end of cell */
standard cell. ... /* more cells */
• For example, function, area. } /* end of library */
• Pin:
• Timing, power, capacitance,
leakage, functionality, etc.
characteristics of
each pin in each cell.
37 © Adam Teman, 2018
 Syntax
Analysis

Liberty (.lib): Timing Models Library

Definition
Elaboration
and Binding

• Non-Linear Delay Model (NLDM) Pre-mapping

Optimization
• Driver model: Constraint
Definition
• Ramp voltage source Technology
• Fixed drive resistance lu_table_template(delay_template_5x5) { Mapping
variable_1 : input_net_transition;
• Receiver model: Post-mapping
variable_2 : total_output_net_capacitance; Optimization
• Min/max rise/fall input caps index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
Report and
index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
export
• Very fast }

• Doesn’t model cap variation during transition.

• Loses accuracy beyond 130nm cell (INVX1) {
pin(Y) {

tpd =f ( tinput , Cload )

timing() {
tpd cell_rise(delay_template_5x5) {
values ( \
"0.147955, 0.218038, 0.359898, 0.922746, 1.76604", \
tf "0.224384, 0.292903, 0.430394, 0.991288, 1.83116", \
"0.365378, 0.448722, 0.584275, 1.13597, 1.97017", \
"0.462096, 0.551586, 0.70164, 1.24437, 2.08131", \
"0.756459, 0.874246, 1.05713, 1.62898, 2.44989"); }
38 © Adam Teman, 2018
 Syntax
Analysis

Liberty (.lib): Timing Models Library

Definition
Elaboration
and Binding

• Non-Linear Delay Model (NLDM) Pre-mapping

Optimization
• Delay calculation Constraint
Definition
interpolation Technology
Mapping
Post-mapping
Optimization
Report and
export

39 © Adam Teman, 2018

 Liberty (.lib): Timing Models
• Current Source Models (CCS, ECSM)
• Model a cell's nonlinear output
behavior as a current source
Courtesy: Cadence
• Driver model:
• Nonlinear current source
• Receiver model:
• Changing capacitance
• Requires many more values
• Requires a bit more calculation
• Essential under 130nm
• Within 2% of SPICE.

Courtesy: Synopsys
40 © Adam Teman, 2018
 Syntax
Analysis

Liberty (.lib): Timing Models Library

Definition
Elaboration
and Binding

• NLDM vs CCS/ECSM Pre-mapping

Optimization
Constraint
Definition
Technology
Mapping
Post-mapping
Optimization
Report and
export

41 Courtesy: Synopsys © Adam Teman, 2018

 Syntax
Analysis

Liberty (.lib): Wire Load Models Library

Definition
Elaboration
and Binding

• How do you estimate the parasitics (RC) of a net Pre-mapping

Optimization
before placement and routing? Constraint
Definition
• Wire Load Models estimate the parasitics based on the fanout of a net. Technology
Mapping
library (myLib) { Post-mapping
wire_load(“WLM1”) Optimization
resistance: 0.0006 ; // R per unit length Report and
capacitance: 0.0001 ; // C per unit length export
area : 0.1 ; // Area per unit length
slope : 1.5 ; // Used for linear extrapolation
fanout_length(1, 0.002) ; // for fo=1, Lwire=0.002
fanout_length(2, 0.006) ; // for fo=2, Lwire=0.006
fanout_length(3, 0.009) ; // for fo=3, Lwire=0.009
fanout_length(4, 0.015) ; // for fo=4, Lwire=0.015
fanout_length(5, 0.020) ; // for fo=5, Lwire=0.020
fanout_length(6, 0.028) ; // for fo=6, Lwire=0.028
}
} /* end of library */

http://www.vlsi-expert.com/
42 © Adam Teman, 2018
 Syntax
Analysis

Physical-Aware Synthesis Library

Definition
Elaboration
and Binding

• Due to the lack of accuracy, wireload models lead to very poor correlation Pre-mapping
Optimization

between synthesis and post-layout in nanometer technologies. Constraint

Definition

• Instead, use physical information during synthesis Technology

Mapping

• Synopsys calls this “Topographical Mode” Post-mapping

Optimization

• Cadence calls this “Physical Synthesis” Report and

export

• Physical-Aware Synthesis basically runs placement inside the synthesizer to

obtain more accurate parasitic estimation:
• Without a floorplan, just using .lef files
• After first iterations, import a floorplan .def to the synthesizer.
syn_opt -physical

43 © Adam Teman, 2018

 1 2 3 4 5 6
Introduction Compilation Library Def. LEF Liberty Other

Syntax
Analysis
Library
Definition
Elaboration
and Binding
Pre-mapping
Optimization
Constraint

Other Contents of SC Library

Definition
Technology
Mapping
Post-mapping
Optimization
Report and
export
 Syntax
Analysis

Other contents of SC Library Library

Definition
Elaboration
and Binding

• Many other files and formats may be provided as part of a Pre-mapping

Optimization
standard cell library: Constraint
Definition
• GDS Technology

• Verilog
Mapping
Post-mapping

• ATPG
Optimization
Report and

• Power Grid Models export

• OA Databases
• Spice Models
• etc.

45 © Adam Teman, 2018

 Syntax
Analysis

Documentation and Datasheets Library

Definition
Elaboration
and Binding

• So, are we just supposed to look through and see what the vendor Pre-mapping
Optimization
decided to provide us with? Constraint
Definition
• Yes! Technology
• However they probably supplied some PDFs describing the library. Mapping
Post-mapping
• And usually there are data sheets with numbers for each corner. Optimization
Report and
export

46 www.vlsi.ce.titech.ac.jp/kunieda/lecture © Adam Teman, 2018

 Syntax
Analysis

And what about other IPs? Library

Definition
Elaboration
and Binding

• All IPs will be provided as a library, including most of the views a Pre-mapping
Optimization
standard cell library will have. Constraint
Definition
• These are required for integration of the hard macros in the standard Technology

design flow (simulation, synthesis, P&R, verification, etc.)

Mapping
Post-mapping
Optimization
• Memories (SRAMs) are a special case, as they usually come with a Report and

memory compiler that generates the particular memory cut the

export

designer requires.

47 © Adam Teman, 2018