The Ninth International Conference on Electronic Measurement & Instruments ICEMI’2009

Research on Metastability based on FPGA

Jie Wu1, Yichao Ma1 Jie Zhang1 Yang Kong1 Hongzhi Song1 Xiaoquan Han2
1 Department of Modern Physics, University of Science and Technology of China,Jin Zhai Road 96, 230026,
Hefei, Anhui, China
2Bureau of Geophysical Prospecting, 072751, Zhuozhou, Hebei, China
Email: [email protected]

Abstract – Multi-clock is commonly used in complex systems. can be defined the output of a flip-flop can not reach its
So if synchronous signals in one clock domain are transferred stable state at an exact time. And the uncertain time will
to another clock domain, they will become asynchronous always cause uncertain troubles [1].
signals. Asynchronous signals will cause metastable state, tCO is the time of clock to output, it relates with the
which will lead to unpredictable results. How metastabilities
setup time (tSU) and hold time (tHD). When tSU and tHD
led to errors in a system is described first. Then a simulation of
RS flip flop using pspice is to show the detail procedure of
meet with a flip-flop, the tCO is the typical output delay of
metastability. To demonstrate how often metastabilities will this flip-flop, which is always given in its datasheet.
happen, a FPGA based experimentation is realized by With the decrease of tSU and tHD, tCO becomes longer.
changing the internal layout of flip flop manually, which When tCO is longer than the maximum value of one
changes the propagation delay between them. flip-flop, the flip-flop turns into metastable state. At this
Keywords –metastability, FPGA, multi-clock domain. point, the time of tSU and tHD are called metastable
window (W). When the input signal edge is close and
I. INTRODUCTION close to the clock edge, tCO becomes long and long, the
time of tCO is an exponential relationship between the tSU
Nowadays digital system is more and more and tHD parameters ( (1) and Fig. 1 [2]). W andW are
complicated, one system always needs to communicate constant values related with a specific flip-flop.
with more than one other systems simultaneously. For 
tCO
W
example, a computer has UART port, parallel port, USB Aperture W *(e ) (1)
port, Ethernet port etc. to exchange data with different
peripherals. And most of the communication buses work
in different clock with the computer’s, so it is important
to make a reliable communication channel between
asynchronous clock domains. There are two kinds of
asynchronous clocks, two clocks with unrelated
frequency and phase, and two clocks with same
frequency but unrelated phase.
Asynchronous signal means the signal has not a stable
phase relation with sample clock. For a local clock
domain, an asynchronous signal means an unstable
signal, because it is very possible that the signal is
sampled when it is changing its state. In another word,
Fig. 1. Metastable window
because an asynchronous signal arrives at random time
related with the local clock, the setup and hold time of a
local flip-flop is violated. When this happens, a flip-flop When signal arrives before aperture window, the
may go to three different states: A) it recognizes the input output time equals with tCO, and if signal arrives between
signal, so a new value is given out; B) it fails to recognize aperture window, the output time is great than tCO.
the input signal, so it keeps the old value; C) it fails to
recognize the input signal, and the flip-flop comes into a II. PROBLEM DEFINITION
metastable state.
When a flip-flop comes into a metastable state, we can From section I, we know how metastability comes.
not tell the exact time when the output will update to a When a flip-flop comes into a metastable state, it can not
new value. The time depends on how closely the to get a stable state at an acceptable time. This will cause
asynchronous signal comes to the local clock, closer and logics behind the flip-flop become disordered. [3]
longer. The time may be one millisecond, one second,
one minute, one hour or even one year. So metastability A. Problem one

_____________________________ First, the state changing of a flip-flop can not happen

978-1-4244-3864-8/09/$25.00 ©2009 IEEE in an exact time will cause the losing of some important

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controls. Let’s take Fig. 2 as an example to show this From the list of Table 1, if it is in the condition
problem. TC-2*TD-TCO<TS<TC-TD-TCO, the output value of REG1
In Fig. 2, four CPUs compose a Symmetrical and REG2 will make a different state, REG2 gives a new
Multi-Processing system (SMP), each of the CPU can state while REG1 keeps old state. If REG1 and REG2 act
build a dedicate communication data channel with any of as the variable of a state machine, the state machine will
other CPU. The cross switch function is build up by a led an error state, which may cause critical error [4]. 
FPGA, if one CPU wants to communicate with other, it
should first assert a REQ signal to indicate it wants to do ċ. PSPICE SIMULATION [5]
some data transfer. If the other CPU was in free, the
FPGA responds with an ACK signal. After catching the RS latch is constituted by two NAND gates or two
ACK signal, the CPU can build a data channel. NOR gates. Fig. 4 is a typical RS latch build up by two
NAND gates, it has two complemental output ports Q
and Q , R and S is the two input ports, R is reset port, S
is set port, both are valid in low voltage.
R
Q

Fig. 2. Multi CPU with cross switch bus

Q
If the FPGA and CPU run in different clock domains, S
the REQ signal maybe arrive too late to FPGA, so CPU
can not get the ACK signal from FPGA and has to keep
Fig. 4. The structure of a RS latch
waiting. When the flip-flop in FPGA reaches its tCO time
from metastable state, the CPU is already time out.
The logic equations of RS latch are:
B. Problem two Q SQ Q RQ (2)
With (2), we can get Table 2 of how RS latch changes
When an asynchronous signal is sampled by more its state.
than one flip-flops, the propagation delay are different, as
in Fig. 3. The first path from A, B, C to D is delayed by Table 2. The state change of RS latch
an AND and NOT logic, so the propagation delay is 2*TD.
The second path from A, E to F is only delayed by a NOR Q Q state RS=00 RS=01 RS=11 RS=10
gate, so the propagation delay is TD, which is short than 11( Last state) 11 10 00 01
the first path. 10( Last state) 11 10 10 11
00( Last state) 11 11 11 11
01(Last state) 11 11 01 01

When Q Q are in state 11, if RS inputs change from

00 to 11 simultaneously, Q Q will turn to 00. But if
Fig. 3. Asynchronous signal feeds different logics feedback delay existed between Q Q outputs and RS
If an asynchronous signal is close enough to the local inputs, then Q Q will change their state between 00 and
clock edge, the first flip-flop REG0 will turn into 11, which generates oscillating circuit.
metastable state, the time of REG0 output (TCO) may vary A RS latch circuit is simulated in PSPICE, the circuit
in wide range. The clock period is TC, and the setup time is shown in Fig. 5. The feedback delay is realized by RC
of flip-flop is TS, so the output of REG1 and REG2 is filter. A stimulate is added at 100ns to the circuit, that is
shown in Table 1. RS change from 00 to 11. The simulation result is Fig. 6.
Table 1. Flip-flop output value versus clock output time
The
QQ outputs changes from high to low at the same
Flip-flop Conditions Output value time when RS changing state, and then they keep
REG1 TC-2*TD-TCO>TS New value oscillating for about 180 ns. The oscillating can not
REG1 TC-2*TD-TCO<TS Old value continue because of the unbalance structure of the model.
REG2 TC-TD-TCO>TS New value In real circuit, the circuits noise and the unmatch of the
REG2 TC-TD-TCO<TS Old value circuits will also prevent the oscillating.

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PARAMETERS:
v ar = 100n

S SN5400 Q
R3

1k
V C1
U6A
20p
V1 = 3.3v V1
V2 = 0v 0
TD = 0
VCC TR = 1n
TF = 1n U6B
V3 PW = 100n /Q R4
5Vdc PER = 400n

R 1k
V C2
SN5400 20p
0 V1 = 3.3v V2
V2 = 0v 0
TD = 0
TR = 1n
TF = 1n
PW = {v ar}
PER = 400n

Fig. 5. PSPICE simulation of RS latch circuit

A global clock net is used to drive all the flip-flops, so

the skew of the clock can be ignored. When a
synchronous signal is fed into DFFA, its output QA may
turn into metastable state and the data output time tCO is
unpredictable.
DFFB connects with DFFA directly, there is no delay
of combine logic, and the propagation delay is minimum.
We can chose a suitable clock period to make it is less
probable that tCO ! tC  t SU  t PROP , so it can be
ignored. QB turns to high at the next positive edge after
Fig. 6. PSPICE simulation result  the arriving of synchronous signal.
DFFC connect with DFFA directly too, but with a
tC
Č. FPGA VERIFICATION OF MTBF reversed clock. When tCO   t SU  t PROP , QC turns
2
to high at the first negative clock edge after the arriving
Since asynchronous signal will cause error to a digital
tC
system, how it is serious must be measured. A parameter of synchronous signal. When tCO !  tSU  t PROP ,
that is called Mean Time Between Failure (MTBF) is 2
always to do this. To demonstrate MTBF, a logic circuit QC turns to high at the second negative clock edge after
in FPGA is built up (Fig. 7) [6]. the arriving of synchronous signal.
The NOR result of QB and QC is latched by DFFD.
tC
When tCO   t SU  t PROP , QD keeps its output
2
t
unchanged; and when tCO ! C  t SU  t PROP , there is a
2
pulse in the output of QD. So the counter that connects
with QD can be used to measure the number, which
means the FPGA has turn into metastable state and
tC
tCO !  tSU  t PROP , in a specific period.
2
By changing the period of clock tC and
tC
 tSU  t PROP , we can get different metastable state
2
counters according to different tCO, so MTBF can be
calculated. But in FPGA, the tC value can not too small,
Fig. 7. MTBF in FPGA which means it is difficult to get enough values. For a
Xilinx Spartan 3E FPGA, the maximum of clock

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frequency is about 300MHz. At 300 MHz, we can not get From (1), if an average period of the asynchronous
any metastable state counter in 30 minutes, but when signal is tC, then the probability of the edge of
clock is high as 310 MHz frequency, we can get only one asynchronous signal drops into metastable window is
metastable state counter per minute, that is almost the p=Aperture / tC. When this happened, tCO is great than
limit of FPGA. tC  tSU  t PROP , a metastable state will cause mistake.
Since we can not get enough values through changing
the clock frequency, we can get them by changing the So the error number ne of one clock period is
ne = n*p = n* (Aperture / tC)
tC
value of  tSU  t PROP . Xilinx ISE software provides n = fd / fC (3)
2 n = how many state changes in one clock period of
a way to change the location of registers in FPGA asynchronous input signal
manually, different locations of register led different fd = the frequency of state changing of input signal
propagation delay. fC = the clock frequency of local flip-flop
So the error counter (Ne) in one period (toperation) can
Table 3. Measurement values
be calculated by (4) [7]
tMET(ns) MTBF(ms) Ne = toperation / tC * ne = toperation * fd * fC *Aperture (4)
0.05 1.7 And the MTBF is
tCO
0.23 13.14
MTBF = 1 / (f d * f C *Aperture) = (e W ) / W *f d * f C (5)
0.57 311
0.73 7545 In Fig. 7, fc = 310MHz, fd =100MHz, the clock
skew between registers is ignored, the register’s
t t
maximum tCO ( CO _ MAX ) is 567ps, the SU is 314ps.
tMET is the time margin at the maximum tCO .
tC
tMET  tCO _ MAX  tPROP  tSU (6)
2
Let’s use t MET to replace tCO , the (5) can be
turned into (7)
t MET
ln(MTBF )  ln(W * f d * f c ) (7)
W
If we can get different value pairs t MET of and MTBF,
then W and W can be get with (8).
t MET 1  t MET 2
W
˄A˅Far layout between registers ln(MTBF1 )  ln(MTBF2 ) (8)
t MET
e W
W
MTBF * f d * f c
The measurement pair values are shown in Table 3.
With Table (3) and (8), we can get the FPGA related
parameter W and W
are W 2.03 u 10 10 ,W 1.5 u 10 18 .

˄B˅Near layout between registers

Fig. 8. Different locations led different propagation delay in FPGA

In Fig.8a, DFFA is placed at a far location from DFFB

and DFFC , so it needs longer propagation delay, while in
Fig. 8b it is much near. So the propagation delay in Fig.
8a is 0.658ns, and the propagation delay in Fig. 8b is
about 0.455ns, these values can get easily from the
FPGA EDITOR of ISE software. Fig.9. The fitting curve of MTBF

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Fig. 9 is the fitting curve of MTBF. When tMET is 0.7ns,
there is about one error per minute; when tMET is 1.5ns,
there is about one error per day; when tMET is 2.2ns, there
is about one error per decade. And when MTBF is about
more than 10 years, the system can be say is stable and
reliable.

č. SUMMARY

Metastability is sure to happen when asynchronous

signal exists. But sometimes it is always been neglected,
because it maybe harmless to one system or it is not
happening every time. Metastability makes a system
looks like unstable, sometimes works well while
sometimes works fail. This paper gives the definition of
metastability, how it is harm to a system and what is
probability metastability happens.

ACKNOWLEDGMENT

The author wishes to thank Dr. Zhuan Yu and Dr.

Mingpu Xie for the verification of metastability in
FPGA.

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