Digital Logic and Computer Arithmetic

Control Unit Design

4.1] Introduction
― Function of Control Unit
The control unit works by getting information as input. It changes
information into control signals, and send these signals to the Central
processing unit (CPU) and other hardware to perform specific
operation in specific order.
a) Coordinate of data moment between processors subunit and its
sequencing.
b) Interpretation of instructions fetched from the memory.
c) Controlling the data flow over the CPU.
d) Conversion of external instruction or commands into sequence
of control signals.
e) Controlling the subunits of the CPU such as ALU registers, data
buffer etc.
f) Scheduling the operations of the CPU in an appropriate flow so
as to complete the execution of instruction.
― Operations of control unit are based on the following inputs.
a) Opcode of instruction
b) The condition codes as status flags
c) The current state of the processor
d) Clock signal
― Different types of control signals
A] External control signals
1) RD: Read control signal
2) WR: Write control signal
B] Internal control signals
1) Register control signals
a) Rx in (Register in)

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 Digital Logic and Computer Arithmetic

b) Rx out (Register out)

c) R0 – RN: General purpose register
d) MAR: Memory address register
e) MDR: Memory data register
f) PC: Program counter
g) SP: Stack pointer
h) IR: Instruction registers
i) TMP, Z: Temporary register
2) ALU (Arithmetic Logical Unit) control signal
a) ALU in
b) ALU out
― Types of Control Units
A] Hardwired Control Unit
B] Micro Programmed Control Unit
4.2] Hardwired Control Unit
i. The Hardwired Control Unit uses a dedicated hardware,
including digital logic and finite state machine, to execute
instruction. It generates control signal based on the instructions
and condition code status, ensuring the proper execution of
task.
ii. Design of Hardwired control unit is guided by following factors:
a) Complexity and amount of hardware used
b) Decide speed of a generation of control signals
c) Costing of design.
iii. Methods of hardwired control unit on the basis of the
technique used for the implementation:
a) State – Table Method
b) Delay – Element Method

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4.2.1] State – Table Method

In a hardwired control unit, a state table guides the generation of
control signals for executing instructions. It transitions between
states based on the current state and inputs, ensuring the right
signals are produced. For instance, when doing unsigned
multiplication, the state table helps create the needed control signals
at each step.
4.2.2] Delay – Element Method
In a hardwired control unit with delay elements, control signals are
made in a sequence. States help identify which signals to make
together, and as the states change, the next set of signals is
produced. To keep things in sync with a clock, we use delay elements,
like D flip-flops, ensuring signals are generated one after the other.

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4.3] Micro Programmed Control Unit

i. Microprogrammed Control Unit simplifies the design of a
control unit. Instead of complex interconnections, it uses
microcode, making it easier to sequence micro-operations,
interpret opcodes, and make decisions based on ALU flags.
ii. This simplifies testing and implementation. Adding new
instructions is also easier with a Microprogrammed Control
Unit.

4.3.1] Functioning of microprogrammed control unit

Microprogrammed Control unit has three inputs namely: ALU flags,
Clock and Instruction Register (IR). It gives two groups of control
signals: one to external system bus and other internal within CPU. To

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perform any operation, the control unit performs the following task
in one clock pulse:
i. Sequencing logic give READ command to control memory.
ii. Instruction from CAR is read into CBR.
iii. CBR generates a control signal for internal and external bus and
information of next address for sequencing unit.
iv. Sequencing logic decides the address of any instruction to be
loaded into CAR depending upon the information given by CBR.
v. There are two decoders present in the Microprogrammed
Control Unit.
vi. The upper decoder is used to translate the opcode of the IR into
address of a control memory.
vii. The lower decoder converts function code to individual signal
to be connected into control lines.

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 Digital Logic and Computer Arithmetic

4.3.1] Advantages and Disadvantages of Microprogrammed Control

Unit
Advantages:
1. It simplifies the control unit design
2. It is cheaper and is less error prone to implement
3. The decoder and sequential logic are simple
4. Used for CISC and mainframes.
Disadvantages:
Microprogrammed Control Unit as slower as compared to
hardwired control unit.
4.3.2] Micro Instruction-Format, Sequencing and Execution
(1) Micro Instruction-Format:
A microinstruction is a set of small, detailed instructions that
guide a computer's control unit through specific tasks. Each
microinstruction has essential components, such as an
operation code (indicating what task to perform) and control
bits (providing specific details). This format ensures that the
computer knows precisely what actions to take during its
operations.
Horizontal micro Vertical micro
Observation.
instruction instruction
Control signals in the
Control signal Individual control
form of function is
generation. signals are generated
generated
Decoder required. No. Yes.
Each control signals Individual control
Connection to are directly signals are
control lines. connected to control connected to control
lines. lines.
Access of individual Possible. Not possible

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control bit and

signal.

(2) Micro Instruction-Sequencing:

Sequencing is referring to the sequence in which the computer
reads and executes microinstructions. Sequencing ensures that
the computer performs tasks in the correct order. A sequencer

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helps keep track of which microinstruction comes next. This

orderly approach is crucial for the computer to execute
instructions accurately and efficiently.
(3) Micro Instruction-Execution:
Execution is when the computer actually does the tasks listed in
the microinstructions. It's the part where the computer doing
things like grabbing data, doing math, or saving results. The
microinstructions act like signals, telling different parts of the
computer what to do.
4.3.3] Micro operations, Examples of microprograms.
1. Micro operations
Micro operations are tiny, fundamental tasks that a computer's
control unit can perform on data stored in its registers. These
micro-operations are the building blocks for more complex
tasks executed by the computer.
2. Example
(1) Data Move:
 Task: Move data from one place to another.
 Microprogram: Instructions that tell the computer where
to take the data from and where to put it.
(2) Addition:
 Task: Add two numbers together.
 Microprogram: Step-by-step instructions for setting up the
numbers, doing the addition, and saving the result.
(3) Logical AND:
 Task: Make a decision based on binary data.
 Microprogram: Instructions that say how to decide things
by looking at the data in the computer.
4.4] Different between Hardwired Control Unit and Micro
Programmed Control Unit

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Hardwired Micro programmed

Observation.
controlling it. control unit.
Chip area. More. Less
Cost. More. Less.
Design process. Complicated. Simple.
Sequencing and
Complex. Easy.
decoding.
Capability to Complete redesign is
Possible to alter.
incorporate changes. required.
Number of
Preferably less. Preferably more
instructions.
Application. RISC processor CISC processors,
main frames.

Memory Organization

Memory:
Memory is an essential component of computer system. The main
internal memory of a computer system along with magnetic disc
from the important RAM, ROM and external storage memories are
required by the processor to perform the task. Memories can be
classified as a primary memory and secondary memory depending
upon their utility and accessibility.
5.1] Classification of Primary Memory and Secondary Memory
5.1.1] Primary Memory
The memory that is directly addressable or accessible on the memory
map of the processor is called primary memory. All types of RAMs
and ROMs are primary memory of a computer system. These
memories are first interacted with computer system with processor.
They form internal memories of a computer system.
• Features of Primary Memory

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 Digital Logic and Computer Arithmetic

1. Primary memory has smaller access time. It is faster than the

secondary memory.
2. It is accessed directly by processor.
3. They have small capacities compared to secondary memories.
4. Few elements of a primary memory are volatile in nature.
5. It is expansive as compared to secondary memory.
6. Every memory reference by the processor for data and code is
performed on the primary memory.

5.1.2] Secondary Memory

The memory that is not directly addressable or accessible on the
memory map of a processor is called a secondary memory. It exists as
the external memory device of the system. All external devices from
the secondary memory. The memory could be incorporated as a fixed
device or a removable device.
Features of Secondary Memory
1. Secondary memory requires more access time. It responds
slower than primary memory.

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2. It cannot be accessed directly by the processor.

3. They have bigger capacities compared to primary memory.
4. Secondary memory is non-volatile in nature.
5. It is cheaper as compared to primary memory.
6. The secondary memory is first read into primary memory and
then accessed.

5.2] Types of RAM and ROM

1) The memories are always accessed randomly irrespective of the
fact that whether they are RAM or ROM.
2) In case of RAM reading as well as writing is performed with the
help of electrical signals. Also, RAMs are volatile. Means that the data
is lost if power is cut to the memories.
3) The read only memory consists of a permanent pattern of data
etched into memory that cannot be modified, but can be read.
Therefore, ROMs are non-volatile i.e., once written, this store data
even without power. the ROMs are therefore used for
microprogramming processors to write a system programmes,
function tables and library sub routines.

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 Digital Logic and Computer Arithmetic

Storage
element Write
Memory type Volatility Read/write Erasure
and mechanism
memory cell
Dynamic
Random
Electrical,
Access Volatile Capacitor Read Write Electrical
Byte Level
memory
(DRAM)
Static Random
Access Flip Flop Electrical,
Volatile Read Write Electrical
Memory Gate Byte Level
(SRAM)
Wired Wired chip
Read Only
during chip Not fabrication
Memory Non volatile Read only
fabrication possible process using
(ROM)
process masks
Wired
Programmable during chip Not
Not volatile. Read only Electrical
ROM (PROM) fabrication possible
process
Erasable
Read UV light,
PROM Non volatile Transistor Electrical
frequently Chip Level
(EPROM)
Electrical
Transistor or Read Electrical,
EPROM Non volatile Electrical
flip flop frequently Byte Level
(EEPROM)
Read Electrical,
Flash memory Non volatile Transistor Electrical
frequently Byte Level

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 Digital Logic and Computer Arithmetic

• Difference between SRAM and DRAM

Observation DRAM SRAM
Memory cell
Simple and small Complex and large
construction
Cell density More Less
Cost Less expensive Costlier as compared
Slightly slower as
Speed Faster as compared
compared
Usage Main memory Cache

5.3] Memory Hierarchy

1) The single memory implementation technology cannot support
the system requirements of a high storage and faster execution.
Hence, a combination of a memory technologies can be used to store
active programmes and data together in a fast, smaller memories,
whereas, a save rest of the data in low cost, slightly slower used
memory device. This technique is termed as hierarchy.
2) The faster smaller memories consist of registers, cash, main
memories. Magnetic discs, CDs, DVDs, tapes, etc. from the auxiliary
are low-cost slower memories.
3)

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4) From top to bottom, following observations occurs:

1. Increase in the capacity
2. Decrease in the cost per bit
3. Increase in the access time
4. Decrease in the frequency of usage of memory by processor
5) Thus, smaller, costlier, faster memories are supplemented by
bigger, cheaper, slower memories.
5.4] Characteristics of Memory
A. Location in Memory hierarchy:
It deals with the location of the specified memory in the
memory hierarchy of the computer system. There are different
possible locations for memories like CPU, cache memory, main
memory, secondary memory.
B. Capacity and addressability:

C. Unit of data transfer:

The maximum number of bits that can be accessed by the
memory at time. Bit/sec.
D. Access method:
It is a fundamental characteristic of a memory or memory
device. It is a method or in which memory element can be
accessed. There are three types of access method
1) Random access 2) Sequential or serial excess 3) Semi random
or pseudo random access
E. Physical type:
The semiconductor memories like RAM - Random Access
Memory and ROM - Read Only Memory.
There are other physical types of memories such as Magnetic
access/Recording type (ex., Hard Disk) or Optical
access/Recording type (ex., CD, DVD, Blu-Ray Disk)
F. Volatility:

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(1) Volatile: The memory that loses its data content of its
location is called volatile memory.
(2) Non-Volatile: The memory that holds on to the data content
of its location is called as non-volatile memory.
G. Writable and write cycles sustenance:
Non-volatile memories usually ROMs are classified based on
the whether they are writable or not. They are referred to as
read mostly memory if they are writable. Such memories show
different number of write cycle that they can sustain. This
property is called write cycle sustenance.
H. Performance parameter
The performance of a memory is determined on parameters
like 1) memory access time 2) Memory cycle time 3) Peak data
transfer rate.
I. Cost
The cost is measured as the cost incurred for some suitable unit
of memory size i.e., cost per bit Cost/MB or Cost/GB.
5.5] Cache Memory
5.5.1] Cache Memory:
Cache memory is a super-fast type of computer memory that helps
the CPU access frequently used data quickly. It sits between the main
memory and the processor, storing important information to speed
up overall performance. The key idea is to keep copies of frequently
accessed data close to the processor, making tasks run faster.
5.5.2] Locality of Reference
Locality of reference is a fundamental concept in computer science,
especially in the design of cache memory. It refers to the tendency of
a program to access a relatively small portion of its address space at
any given time. There are two primary types of localities:
(1) Temporal Locality:

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Definition: Refers to the reuse of the same set of memory locations

within a short period.
Example: Repeatedly accessing the same variables or instructions in a
loop.
(2) Spatial Locality:
Definition: Refers to accessing memory locations that are near each
other.
Example: Fetching a block of data into cache and then accessing
neighbouring elements.
5.5.3] Cache Mapping Techniques
Cache contains less memory lines than the main memory. Hence the
main memory blocks are added to be mapped into the cache.
Different mapping functions are:
A. Direct Mapping
• Concept:
In direct mapping, each block of main memory has placed in
one possible cache line. The mapping is direct and
straightforward.
• Mapping Equation:
Cache Line Number = (Main Memory Block Number) mod
(Number of Cache Lines)
• Advantages:
1) Simple and easy to implement.
2) Low hardware overhead.
• Disadvantages:
1) Limited flexibility; can lead to conflicts if multiple memory
blocks map to the same cache line.
B. Fully Associative mapping
• Concept:

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In fully associative mapping, each block of main memory can be

placed in any line of the cache. There is no restriction on the
mapping; any block can go anywhere in the cache.
• Mapping Equation:
No specific equation; any block can be placed in any cache line.
• Advantages:
Maximum flexibility; no conflicts as any block can go to any
cache line.
• Disadvantages:
1) Higher hardware complexity and cost.
2) Slower search times for a block within the cache due to the
lack of a predetermined mapping.
C. Set associative app.
• Concept:
Set associative mapping is a compromise between direct and
fully associative mapping. The cache is divided into sets, and
each set contains multiple lines. Each block of main memory
can be placed in any line within a specific set.
• Mapping Equation:
Set Number = (Main Memory Block Number) mod (Number of
Sets)
• Advantages:
1) Offers flexibility while reducing hardware complexity
compared to fully associative mapping.
2) Helps mitigate conflicts seen in direct mapping.
• Disadvantages:
1) Some degree of complexity compared to direct mapping.
2) Search times within a set are faster than fully associative
mapping but slower than direct mapping.

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 Digital Logic and Computer Arithmetic

5.5.4] Cache Coherency

Cache coherency refers to the consistency of data stored in different
caches that are supposed to contain copies of the same data. In a
multiprocessor or multi-core system where each processor/core has
its own cache, maintaining coherency ensures that all processors see
a consistent view of shared memory. Cache coherency is a critical
aspect of designing and managing systems with multiple processors
or cores to ensure reliable and correct operation in shared memory
environments.
Significance:
(1) Prevents Data Corruption:
Ensures that multiple caches with copies of the same data stay
updated, preventing inconsistencies and data corruption.
(2) Synchronization:
Facilitates proper synchronization between processors in a
multiprocessor environment, allowing for correct execution of
parallel programs.
(3) Performance Optimization:
While cache coherency introduces overhead, it is essential for
maintaining system stability and allowing efficient parallel processing.

Principles of Advanced Processor and Buses

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6.1] Fynn’s Classification

1) The processor or CPU has primary functionality of a processing the
data by the executing programmes. The programme is a sequence of
instructions. Both the programmes and data are stored in a memory.
When the processors or CPU executive programmes is needed to
fetch instructions in the programme from the memory. Once the
instruction is fetching rates decoded and executed in the processor
or CPU while executing, it reads the input data operands from the
memory, and it stores the output data operands to the memory
2) The flow or moment of instruction from the memory to the CPU is
called instruction stream. The two-way flow of input and output data
operands between the CPU and the memory is called data stream.

3) Based on multiplicity of instruction and data streams, the

computers are classified into four different types. This classification is
called a Fynn’s Classification.

4) The four types are:

A] SISD: Single instruction stream, single data stream
In a SISD architecture, there is a single processor that executes
a single instruction stream and operates on a single data

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stream. This is the simplest type of computer architecture and

is used in most traditional computers.
B] SIMD: Single instruction stream, multiple data stream
In a SIMD architecture, there is a single processor that executes
the same instruction on multiple data streams in parallel. This
type of architecture is used in applications such as image and
signal processing.

C] MISD: Multiple instruction stream, single data stream

In a MISD architecture, multiple processors execute different
instructions on the same data stream. This type of architecture
is not commonly used in practice, as it is difficult to find
applications that can be decomposed into independent
instruction streams.

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 Digital Logic and Computer Arithmetic

D] MIMD: Multiple instructions stream, multiple data stream

In a MIMD architecture, multiple processors execute different
instructions on different data streams. This type of architecture
is used in distributed computing, parallel processing, and other
high-performance computing applications.

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 Digital Logic and Computer Arithmetic

5.2] Bus Arbitration

1) Bus Arbitration is the procedure by which the active bus master
accesses the bus, relinquishes control of it, and then transfers it to a
different bus-seeking processor unit. A bus master is a controller that
can access the bus for a given instance.
2) A conflict could occur if multiple DMA controllers, other
controllers, or processors attempt to access the common bus
simultaneously, yet only one is permitted to access. Bus master
status can only be held by one processor or controller at once. By
coordinating the actions of all devices seeking memory transfers, the
Bus Arbitration method is used to resolve these disputes.
Two approaches are followed for the bus Arbitration:

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Centralized Bus Arbitration - In which the necessary arbitration is

carried out by a lone bus arbitrator.
Distributive Bus Arbitration - In which every device takes part in
choosing the new bus master. A 4bit identification number is
allocated to each device on the bus. The created ID will decide the
device's priority.
(I) Daisy Chaining method: It is a simple and cheaper method where
all the bus masters use the same line for making bus requests. The
bus grant signal serially propagates through each master until it
encounters the first one that is requesting access to the bus. This
master blocks the propagation of the bus grant signal; therefore, any
other requesting module will not receive the grant signal and hence
cannot access the bus.
During any bus cycle, the bus master may be any device – the
processor or any DMA controller unit, connected to the bus.

Advantages:
Simplicity and Scalability.
The user can add more devices anywhere along the chain, up to a
certain maximum value.
Disadvantages:
The value of priority assigned to a device depends on the position of
the master bus.

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Propagation delay arises in this method.

If one device fails then the entire system will stop working.

(II) Polling or Rotating Priority method: In this, the controller is used

to generate the address for the master (unique priority), the number
of address lines required depends on the number of masters
connected in the system. The controller generates a sequence of
master addresses. When the requesting master recognizes its
address, it activates the busy line and begins to use the bus.

Advantages –
This method does not favor any particular device and processor.
The method is also quite simple.
Disadvantages –
Adding bus masters is difficult as increases the number of address
lines of the circuit.
If one device fails then the entire system will not stop working.
(iii) Fixed priority or Independent Request method –
In this, each master has a separate pair of bus request and bus grant
lines and each pair has a priority assigned to it. The built-in priority
decoder within the controller selects the highest priority request and
asserts the corresponding bus grant signal.

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 Digital Logic and Computer Arithmetic

Advantages –
This method generates a fast response.
Disadvantages –
Hardware cost is high as a large no. of control lines is required.

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 Digital Logic and Computer Arithmetic

5.3] PCI Bus++

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PCI was designed by the IVM using international standard for 32 bits
interface for 32-bit system architecture. It connected to the high-
speed processor local bus through bridging device component called
as North Bridge and South Bridge.
Features:
(1) PCI bus is a driver using special component called PCI bridge
(2) It increases burst clock speed and makes efficient use of a CPU
Data Bus
(3) Standard bandwidth of PCI bus is 66 megahertz.
(4) It has auto configuration capability for the switchless
peripherals
(5) The capabilities take care of all address IRQ and TMA uses by
this PCI type of a peripherals
(6) It can work with 32 bit or 64-bit bus width
(7) HPCI bus have 256 devices and it uses 33 volts or 22 volts for
operation
(8) It consumes less power
(9)It supports techniques such as green machine concept

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