VLSI

EEE 475: VLSI

LECTURE 1: Introduction

15 MAY 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
 EEE 475
Gain an understanding of the different design steps
required to carry out a complete digital VLSI design

EEE 476

Design and implement VLSI circuits and systems

(Design in CAD)

© 2024, Mohammad Mahmudul Hasan Tareq

 EEE 475
Gain an understanding of the
required to carry out a complete digital VLSI design

© 2024, Mohammad Mahmudul Hasan Tareq

 What components are needed to How are the logic elements going
achieve the functionality? to be realized using transistors?

What does the chip do? How are the logic gates are What is going to be the physical
going to be connected? geometry of the circuit elements
and interconnections?

© 2024, Mohammad Mahmudul Hasan Tareq

What does the chip do?

❖ They’re at the heart of the devices

❖ A microchip (also called a chip, a computer chip,

an integrated circuit or IC) is a set of electronic
circuits on a small flat piece of silicon

❖ Transistors act as miniature electrical switches

that can turn a current on or off

❖ By adding and removing materials to form a

multilayered latticework of interconnected
shapes

© 2024, Mohammad Mahmudul Hasan Tareq

 What components are needed to How are the logic elements going
achieve the functionality? to be realized using transistors?

What does the chip do? How are the logic gates are What is going to be the physical
going to be connected? geometry of the circuit elements
and interconnections?

© 2024, Mohammad Mahmudul Hasan Tareq

 Transistor Theory
Memory Inverter Characteristics
Sub-system Design Interconnects

Modeling Digital Systems CMOS Logic Gate Design IC Fabrications

using Verilog Combinatorial Logic
Sequential Logic
Dynamic Logic

Is CMOS still relevant?

© 2024, Mohammad Mahmudul Hasan Tareq
 Products
Products of of 2024
2024

© 2024, Mohammad Mahmudul Hasan Tareq

The First Computer*

• Mechanical
• Decimal System
• “Store” and “Mill” Operation

source: google

© 2024, Mohammad Mahmudul Hasan Tareq

The First Computer*

source: google

© 2024, Mohammad Mahmudul Hasan Tareq

The First Computer*

The Difference Engine realized by London Science Museum

© 2024, Mohammad Mahmudul Hasan Tareq

 The First Computer

1940s University of Pennsylvania

What is the full form of ENIAC and UNIVAC? What were they used for?
WHAT were they made with? HOW were they put together?
© 2024, Mohammad Mahmudul Hasan Tareq
 Development Timeline

1908 Vacuum Tubes 1947 Transistor 1959 Integrated Circuits

1946 ENIAC, UNIVAC 1954 Bell Labs, IBM, … 1964 IBM 360
1971 Intel 4004

© 2024, Mohammad Mahmudul Hasan Tareq

Thank you Moore’s Law!
© 2024, Mohammad Mahmudul Hasan Tareq
Moore’s Law

© 2024, Mohammad Mahmudul Hasan Tareq

 Moore’s Law : ITRS

What is channel length?

What does it represent
in today’s world?

© 2024, Mohammad Mahmudul Hasan Tareq

Channel Length

© 2024, Mohammad Mahmudul Hasan Tareq

More than Moore and Beyond Moore

ref: Computing beyond Moore’s Law, John Shalf and Robert Leland, 2015

© 2024, Mohammad Mahmudul Hasan Tareq

More than Moore and Beyond Moore

ref: The future of Computing, John Shalf, 2019 CMOS IS relevant

CMOS will remain relevant
© 2024, Mohammad Mahmudul Hasan Tareq
 Transistor Theory
Memory Inverter Characteristics
Sub-system Design Interconnects

Modeling Digital Systems CMOS Logic Gate Design IC Fabrications

using Verilog Combinatorial Logic
Sequential Logic
Dynamic Logic

© 2024, Mohammad Mahmudul Hasan Tareq

1. Neil Weste & David Harris, CMOS VLSI Design: A Circuits and Systems Perspective
2. Rabaey, Chandrakasan et. al., Digital Integrated Circuits: a Design Perspective (2nd edition)
3. Sung-Mo Kang et. al., CMOS Digital Integrated Circuits

Slides and/or Notes for the lectures will be made available

© 2024, Mohammad Mahmudul Hasan Tareq

 EEE 475: VLSI
LECTURE 2: MOS Transistor

19 MAY 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
 Transistor Theory
Memory Inverter Characteristics
Sub-system Design Interconnects

Modeling Digital Systems CMOS Logic Gate Design IC Fabrications

using Verilog Combinatorial Logic
Sequential Logic
Dynamic Logic

© 2024, Mohammad Mahmudul Hasan Tareq

 Transistor Theory
Inverter Characteristics
Interconnects

© 2024, Mohammad Mahmudul Hasan Tareq

© 2024, Mohammad Mahmudul Hasan Tareq
© 2024, Mohammad Mahmudul Hasan Tareq
© 2024, Mohammad Mahmudul Hasan Tareq
© 2024, Mohammad Mahmudul Hasan Tareq
 4e

• n-type : negative (electron)

• p-type : positive (hole) 3e 5e

© 2024, Mohammad Mahmudul Hasan Tareq

p-substrate

© 2024, Mohammad Mahmudul Hasan Tareq

•

© 2024, Mohammad Mahmudul Hasan Tareq

 •

Checkout Fabrication Animation: https://www.youtube.com/watch?v=bor0qLifjz4

https://www.youtube.com/watch?t=121&v=35jWSQXku74&feature=youtu.be

© 2024, Mohammad Mahmudul Hasan Tareq

 INPUT OUTPUT

0 0 Strong

n-SWITCH

1 1 Weak

WHY?
Stay tuned, we will find out soon

VDD ≈ Logic 𝟏 ,GND ≈ Logic 𝟎

© 2024, Mohammad Mahmudul Hasan Tareq

Why does pmos pass logic 1 strongly but nmos pass
logic 0 strong ? https://www.youtube.com/watch?v=zn_d6_NeMXg

ANS:
 INPUT OUTPUT

0 0 Strong

n-SWITCH

1 1 Weak

0 0 Weak

p-SWITCH
1 1 Strong

© 2024, Mohammad Mahmudul Hasan Tareq

Transmission Gate or Pass Gate

By combining an nMOS and a pMOS transistor in parallel , we obtain a

switch that turns on when a 1 is applied to G(gate) in which 0s and 1s are
both passed Strongly . We term this a transmission gate or pass gate.
Note that both the control input and its complement are required by the
transmission gate. This is called double rail logic.
Here, The inputs drive the gate terminals of nMOS transistors in the pull-
down network and pMOS transistors in the complementary pull-up network.
Thus, the nMOS transistors only need to pass 0s and the pMOS only pass
1s, so the output is always strongly driven and the levels are never
degraded.
• The resistance in OFF state should be infinite
• The resistance in ON state should be zero
• In the ON condition, there is no limit to the current that it carries
• Speed of operation should be instantaneous

Characteristics of MOS Transistors

to predict its performance as a switch
Look at MOSFETS from a circuit designer’s perspective

© 2024, Mohammad Mahmudul Hasan Tareq

 Theoretical Background from : EEE 235 [Sedra-Smith: Chapter 4 (4.1-4.6) ]

We will look at all the theory and equations from a digital circuit designer’s point of view
▪ Consider the physical implications of each parameter as a logic element
▪ Try to understand the ‘behavior’ of element given the physics based equations

© 2024, Mohammad Mahmudul Hasan Tareq

 VGS at which transistor begins to conduct

• 𝑉𝑡𝑛 > 0 • 𝑉 𝑡𝑝 < 0

• 𝐼 𝑑𝑠 > 0 𝑤ℎ𝑒𝑛 𝑉𝑔𝑠 > 𝑉𝑡𝑛 • 𝐼 𝑠𝑑 > 0 𝑤ℎ𝑒𝑛 |𝑉𝑔 𝑠 | > |𝑉 𝑡𝑝 |

Describe the Transistors ‘behavior’ in terms of 𝑉𝑡

© 2024, Mohammad Mahmudul Hasan Tareq

 VGS at which transistor begins to conduct

• 𝑉𝑡𝑛 > 0 • 𝑉 𝑡𝑝 < 0

• 𝐼 𝑑𝑠 > 0 𝑤ℎ𝑒𝑛 𝑉𝑔𝑠 > 𝑉𝑡𝑛 • 𝐼 𝑠𝑑 > 0 𝑤ℎ𝑒𝑛 |𝑉𝑔 𝑠 | > |𝑉 𝑡𝑝 |

What does it depend on?

© 2024, Mohammad Mahmudul Hasan Tareq
 𝑉𝑡 = 𝑉 𝑡𝑚𝑜𝑠 + 𝑉𝑓𝑏

𝑉 𝑡𝑚𝑜𝑠 ideal threshold voltage of MOS-C

𝑄𝑏
𝑉 𝑡𝑚𝑜𝑠 = 2𝜙 𝑏 +
𝐶𝑜𝑥

𝑘𝑇 𝑁𝐴
𝜙𝑏 = ln - bulk potential
𝑞 𝑁𝑖

𝐶𝑜𝑥 ∝ 𝜖 𝑜 𝑥 / 𝑡 𝑜 𝑥

𝑄𝑏 = 2𝜖 𝑆𝑖 𝑞𝑁 𝐴 2𝜙 𝑏 - bulk charge density

© 2024, Mohammad Mahmudul Hasan Tareq

 𝑉𝑡 = 𝑉 𝑡𝑚𝑜𝑠 + 𝑉𝑓𝑏

𝑉 𝑡𝑚𝑜𝑠 ideal threshold voltage of MOS-C 𝑉 𝑓𝑏 is the flat-band voltage

𝑄𝑏 𝑄 𝑓𝑐
𝑉 𝑡𝑚𝑜𝑠 = 2𝜙 𝑏 + 𝑉 𝑓𝑏 = 𝜙 𝑔𝑠 −
𝐶𝑜𝑥 𝐶𝑜 𝑥

𝑘𝑇 𝑁𝐴
𝜙𝑏 = ln - bulk potential 𝑄 𝑓𝑐 = qNf - charge density due to fixed charge at interface
𝑞 𝑁𝑖

𝐶𝑜𝑥 ∝ 𝜖 𝑜 𝑥 / 𝑡 𝑜 𝑥 𝜙 𝑔𝑠 = 𝜙 𝑔 𝑎 𝑡 𝑒 − 𝜙 𝑠 𝑢 𝑏 𝑠 𝑡 𝑟 𝑎 𝑡 𝑒

𝑄𝑏 = 2𝜖 𝑆𝑖 𝑞𝑁 𝐴 2𝜙 𝑏 - bulk charge density Work function diff. between gate and substrate
gate could be metal or poly-si

© 2024, Mohammad Mahmudul Hasan Tareq

 𝑄𝑏 𝑄 𝑓𝑐 𝑉𝑡
𝑉𝑡 = 2𝜙 𝑏 + + 𝜙𝑔 𝑠 −
𝐶𝑜𝑥 𝐶𝑜𝑥

Think about the new FETs and how they target these factors?
© 2024, Mohammad Mahmudul Hasan Tareq
© 2024, Mohammad Mahmudul Hasan Tareq
 VSB

• VSB ≠ 0
• VSB = 0

𝑄𝑏 𝑄 𝑓𝑐 𝑉𝑇 = 𝑉𝑇0 + 𝜸 |2𝜙 𝑏 − 𝑉𝑆𝐵| − |2𝜙 𝑏 |

𝑉𝑇0 = 2𝜙 𝑏 + + 𝜙 𝑔𝑠 −
𝐶 𝑜𝑥 𝐶𝑜𝑥

Bulk Charge Density Bulk Charge Density

• check-out the expression for 𝛾

• Try to derive it

© 2024, Mohammad Mahmudul Hasan Tareq

Instead of deriving the expressions for current flow, let’s try to understand I-V the characteristic behaviors

NMOS is ON (𝑉𝐺𝑆 > 𝑉𝑇)

𝐕𝐃𝐒 applied – what is 𝐈𝐃𝐒?
𝐼𝐷𝑆

0 𝑉𝐺 > 𝑉𝑇 𝑽𝑫

© 2024, Mohammad Mahmudul Hasan Tareq

Instead of deriving the expressions for current flow, let’s try to understand I-V the characteristic behaviors

VT

𝐼𝐷𝑆

𝐼𝐷𝑆 → 0 𝑉𝐷𝑆 = 0, 𝑉𝐺𝑆 < 𝑉𝑇

𝐼𝐷𝑆 ∝ 𝑉𝐷𝑆 𝑉𝐷𝑆 < 𝑉𝐺𝑆 − 𝑉𝑇
𝐼𝐷𝑆 independent of 𝑉𝐷𝑆 𝑉𝐷𝑆 ≥ 𝑉𝐺𝑆 − 𝑉𝑇

© 2024, Mohammad Mahmudul Hasan Tareq

Instead of deriving the expressions for current flow, let’s try to understand I-V the characteristic behaviors
𝐈𝐃 − 𝐕𝐆𝐒 Curve

𝐼𝐷𝑆

𝐼𝐷𝑆 → 0 𝑉𝐷𝑆 = 0, 𝑉𝐺𝑆 < 𝑉𝑇

𝐼𝐷𝑆 ∝ 𝑉𝐷𝑆 𝑉𝐷𝑆 < 𝑉𝐺𝑆 − 𝑉𝑇
𝐼𝐷𝑆 independent of 𝑉𝐷𝑆 𝑉𝐷𝑆 ≥ 𝑉𝐺𝑆 − 𝑉𝑇

© 2024, Mohammad Mahmudul Hasan Tareq

© 2024, Mohammad Mahmudul Hasan Tareq
 D D D

RDS
IDS
𝑅 →∝

S S S

© 2024, Mohammad Mahmudul Hasan Tareq

 CLASSWORK/ASSIGNMENT
• What is the effect?
• Which region does it effect?
• What property does it change?
• What problems does it create?

Create only ONE slide on each topic

Use reference texts [Example: Weste&Harris; Chapter 2]

© 2024, Mohammad Mahmudul Hasan Tareq

 What is the effect of Channel Length Modulation?
Channel Length Modulation (CLM) in MOSFETs causes the drain current (I_D) to increase slightly with increasing drain-source voltage (V_DS) in the
saturation region. This happens because the effective channel length shortens as V_DS increases, resulting in a non-zero output conductance. This effect
impacts the performance of analog circuits by reducing voltage gain.

Which region does it effect?

Channel Length Modulation (CLM) affects the saturation region of a MOSFET.

What property does it change?

Channel Length Modulation (CLM) changes the drain current (I_D) in the saturation region, making it increase slightly with increasing drain-source voltage
(V_DS), resulting in a non-zero output conductance.

What problems does it create?

Channel Length Modulation (CLM) creates the following problems:
● Non-Ideal Behavior: Deviates from the ideal MOSFET model where drain current should remain constant in saturation.
● Output Conductance: Introduces a non-zero output conductance, affecting circuit performance, especially in analog circuits.
● Accuracy Issues: Complicates circuit analysis and design, as simple MOSFET models may not accurately predict device behavior.
 What is the effect of Velocity Saturation?
The effect of Velocity Saturation in MOSFETs is that carriers (electrons or holes) in the channel reach a maximum velocity, even under high electric fields.
This saturation limits the increase in current despite further increases in the applied voltage. As a result, it causes a deviation from the expected linear increase
in current with voltage, impacting the device's overall performance and limiting its speed and efficiency, especially in short-channel devices.

Which region does it effect?

Velocity saturation primarily affects the saturation region of a MOSFET.

What property does it change?

Velocity saturation alters the current-voltage relationship in the saturation region of a MOSFET. Specifically, it limits the increase in current despite higher

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applied voltages, deviating from the expected linear relationship between current and voltage..

What problems does it create?

Velocity saturation in MOSFETs creates the following problems:
● Limitation of Current Increase: Despite higher applied voltages, the current does not increase linearly due to velocity saturation. This limitation
can hinder the performance of high-speed circuits.
● Reduction in Gain: Velocity saturation can reduce the gain of amplifiers and other circuits, impacting their overall performance and efficiency.
● Deviation from Ideal Behavior: It introduces non-idealities into MOSFET operation, complicating circuit design and analysis.
● Short-Channel Effects: Velocity saturation exacerbates short-channel effects in scaled-down MOSFETs, leading to further degradation in
performance and reliability.
 What is the effect of Subthreshold Conduction?
The effect of Subthreshold Conduction in MOSFETs is the presence of leakage current even when the gate-source voltage (V_GS) is below the threshold
voltage (V_TH). This leakage current flows through the channel due to carrier transport mechanisms such as thermionic emission and tunneling. Subthreshold
conduction increases exponentially with V_GS and can significantly impact power consumption, especially in low-power applications where minimizing
leakage currents is crucial for energy efficiency.

Which region does it effect?

Subthreshold conduction primarily affects the subthreshold region of a MOSFET.

What property does it change?

Subthreshold conduction alters the current-voltage relationship of a MOSFET, allowing current flow even when the gate-source voltage is below the threshold
voltage.

What problems does it create?

Subthreshold conduction in MOSFETs creates the following problems:
● Increased Power Consumption: Subthreshold conduction leads to leakage current even when the device is supposed to be off, resulting in higher
power consumption, especially in low-power applications where minimizing leakage currents is critical.
● Reduced Signal Integrity: Leakage currents can interfere with signal integrity in analog circuits and degrade the performance of digital circuits by
affecting the voltage levels and switching speeds.
● Threshold Voltage Variation: Subthreshold conduction can cause variations in the threshold voltage (V_TH) of MOSFETs, impacting circuit
design and performance consistency.
● Impact on Battery Life: In portable devices powered by batteries, subthreshold conduction contributes to power drain, reducing battery life and
overall device runtime.
 What is the effect of Tunneling?
The effect of tunneling in MOSFETs is the phenomenon where charge carriers (electrons or holes) pass through the insulating layer (typically the gate oxide)
of the transistor via quantum mechanical tunneling. This tunneling mechanism allows for leakage currents to flow even when the transistor is supposed to be
in the off state, leading to increased power consumption and potential reliability issues, especially in scaled-down devices with thinner gate oxides. Tunneling
can significantly impact the performance and reliability of MOSFET-based circuits, particularly in low-power applications where minimizing leakage currents
is crucial.

Which region does it effect?

Tunneling primarily affects the off-state or subthreshold region of MOSFETs.

What property does it change?

Tunneling changes the property of insulation or leakage current in a MOSFET. Specifically, it allows charge carriers to tunnel through the insulating layer

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(typically the gate oxide), enabling leakage current to flow even when the transistor is in the off state.

What problems does it create?

Tunneling in MOSFETs creates the following problems:
● Increased Leakage Current: Tunneling allows charge carriers to pass through the gate oxide even when the transistor is off, leading to higher
leakage currents and increased power consumption, particularly in low-power applications.
● Power Dissipation: The presence of tunneling currents contributes to power dissipation, reducing energy efficiency and potentially shortening
battery life in portable devices.
● Reliability Issues: Tunneling can cause reliability concerns, such as oxide breakdown and device degradation over time, especially in scaled-down
transistors with thinner gate oxides.
● Signal Integrity: Tunneling currents can interfere with signal integrity in circuits, affecting performance and reliability, particularly in analog and
mixed-signal applications.
● Process Variability: Variations in tunneling characteristics can lead to process variability, affecting device performance consistency and
manufacturability.
 What is the effect of Temperature?
Temperature affects MOSFETs by:
● Reducing threshold voltage.
● Decreasing carrier mobility.
● Increasing leakage current.
● Influencing breakdown voltage.
● Leading to performance variations across operating conditions.

Which region does it effect?

Temperature affects MOSFETs across all operational regions: subthreshold, linear, and saturation.

What property does it change?

Temperature changes various properties of MOSFETs, including:
● Threshold voltage (V_TH)
● Carrier mobility
● Leakage current
● Breakdown voltage
● Performance consistency

What problems does it create?

Temperature variations in MOSFETs lead to:
● Threshold voltage shifts.
● Performance inconsistencies.
● Increased leakage currents.
● Reliability issues.
● Thermal management challenges.
 L3+L4
MOSCAP
 EEE 475: VLSI
LECTURE 5: MOS Inverter

02 JUN 2024
10 MARCH 2021
2021,
2024, ORCHI HASSAN
Mohammad Mahmudul Hasan Tareq
EEEI BUET
CUET
© 2021, ORCHI HASSAN
EEE
 MOS Scaling

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 REF: Sung-MO Kang

Transistor Theory
Inverter Characteristics
Interconnects

•
•
•

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 Inverter/NOT gate inverts the input signal
(Vin vs Vout)

𝐕𝐢𝐧 𝐕𝐨𝐮𝐭

Logic 1 = VDD
Logic 0 = 0 V
Inverter threshold : 𝑉𝑡ℎ = 𝑉𝐷𝐷/2

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
General Circuit Structure of an nMOS inverter The characteristics of the inverter circuit
actually depend very strongly upon the type
and the characteristics of the load device.
• Resistor
The output terminal of
• nMOS load the inverter shown in
• pMOS Fig. is connected to the
VDD
input of another MOS
inverter. Consequently,
the next circuit seen by
the output node can be
represented as a lumped
capacitance, Cout.

Since the DC gate current of an

MOS transistor is negligible for all
practical purposes, there will be no
current flow into or out of the input
and output terminals of the inverter
in DC steady state.
0
VDD
In static condition:
𝐈𝐃 Vin, Vout = 𝐈𝐋(VL)

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 “5 Critical Voltages”

For very low input voltage levels, the output voltage V is equal to the high
value of VOH. In this case, the driver nMOS transistor is in cut-off, and hence,
does not conduct any current. Consequently, the voltage drop across the load
device is very small in magnitude, and the output voltage level is high. As the
input voltage V increases, the driver transistor starts conducting a certain
drain current, and the output voltage eventually starts to decrease. Notice
that this drop in the output voltage level does not occur abruptly, such as the
vertical drop assumed for the ideal inverter VTC, but rather gradually and
with a finite slope. We identify two critical voltage points on this curve,
where the slope of the VTC becomes equal to -1.
As the input voltage is further increased, the output voltage continues to
drop and reaches a value of VOL when the input voltage is equal to VoH.The
inverter threshold voltage Vth, which is considered as the transition voltage,
is defined as the point where Vin = Vout on the VTC.
 The definition of noise tolerances for digital circuits, called noise
margins and denoted by NM. The noise immunity of the circuit
increases with NM.

Intermediate region or forbidden region

don’t represent digital logic levels.

NML = VIL − VOL Two noise margins will be defined: the noise
margin for low signal levels (NML) and the
NMH = VOH − VIH noise margin for high signal levels (NMH).

Logic Level not a single voltage but a range

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
Unwanted variations of voltages and currents at the logic nodes

Noise from two wires placed side by side

Capacitive Inductive
Supply Noise
Coupling Coupling

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 • Resistor
• nMOS load
• pMOS Resistor
Load

VOUT = VDD − ILRL

IL = IDS(VIN, VOUT)
In static condition:
𝐈𝐃 Vin, Vout = 𝐈𝐋(VL) Find VOH, VOL, VIH,VIL, Vth

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 VOUT = VDD − ILRL

VDD − Vout
IL =
RL
0 𝑉𝑖𝑛 < 𝑉𝑇
In static condition: 𝑊 2
𝑉𝐷𝑆
𝜇𝑛 𝐶𝑜𝑥 𝑉𝑖𝑛 − 𝑉 𝑇 𝑉𝐷𝑆 − 𝑉𝑖𝑛 > 𝑉𝑇, 𝑉𝑜𝑢𝑡 < 𝑉𝐺𝑆 −𝑉𝑇
𝐈𝐃 Vin, Vout = 𝐈𝐋(VL) 𝐼𝐷𝑆 = 𝐿 2
1 𝑊
𝜇𝑛 𝐶𝑜𝑥 𝑉𝑖𝑛 − 𝑉𝑇 2 𝑉𝑖𝑛 > 𝑉𝑇,𝑉𝑜𝑢𝑡 > 𝑉𝑖𝑛 −𝑉𝑇
2 𝐿

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
VOUT = VDD − ILRL

A Vin < VT ∴ IDS = 0

∴ Vout = VDD = 𝐕𝐎𝐇

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
VOUT = VDD − ILRL

C Vin > VT , Vout < Vin − VT Linear region of nMOS

= 𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡 𝑉 = 𝑉𝑂𝐿

Let, 𝑘 𝑛𝑜𝑢𝑡
= 𝜇𝑛𝐶𝑜𝑥 𝑊
𝑅𝐿 𝐿

solve for 𝑉𝑜𝑢𝑡 = 𝑉𝑂𝐿 when 𝑉𝑖𝑛 = 𝑉𝐷𝐷

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 Threshold voltage: 𝑉𝑡ℎ = 𝑉𝑖𝑛 = 𝑉𝑜𝑢𝑡

B Vin > VT , Vout > Vin − VT

Saturation Region of nMOS
𝑊 2 𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡
𝜇𝑛 𝐶𝑜𝑥 𝑉 −𝑉𝑇 =
𝐿 𝑖𝑛 𝑅𝐿

2
1 1 2𝑉𝐷𝐷
𝑉𝑡ℎ = 𝑉𝑇 − + 𝑉𝑇 − − 𝑉𝑇 −
𝑘𝑛𝑅𝐿 𝑘𝑛𝑅𝐿 𝑘𝑛𝑅𝐿

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Mahmudul
 0 𝑉𝑖𝑛 < 𝑉𝑇 A
2
𝑉𝐷𝑆
𝑊
𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝐼𝐿 𝑅𝐿 𝜇𝑛 𝐶𝑜𝑥 𝑉𝑖𝑛 − 𝑉 𝑇 𝑉𝐷𝑆 − 𝑉𝑖𝑛 > 𝑉𝑇,𝑉𝑜𝑢𝑡 < 𝑉𝐺𝑆 −𝑉𝑇
𝐼𝐷𝑆 = 𝐿 2 C
𝑤ℎ𝑒𝑟𝑒, 𝐼𝐿 = 𝐼 𝐷𝑆 1 𝑊
𝜇𝑛𝐶𝑜𝑥 𝑉𝑖𝑛 − 𝑉𝑇 2 𝑉𝑖𝑛 > 𝑉𝑇,𝑉𝑜𝑢𝑡 > 𝑉𝑖𝑛 − 𝑉𝑇 B
2 𝐿

𝐺𝑖𝑣𝑒𝑛, 𝑉𝐷𝐷 = 5𝑉, 𝑘 𝑛 = 40𝜇𝐴/𝑉, 𝑅𝐿 = 100𝑘Ω Can you use matlab to generate the VTC?
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 2
1 1 2𝑉𝐷𝐷
𝑉𝑡ℎ = 𝑉𝑇 − + 𝑉𝑇 − − 𝑉𝑇 −
𝑘𝑛𝑅𝐿 𝑘𝑛𝑅𝐿 𝑘𝑛𝑅𝐿

𝒌𝒏𝑹𝑳 is an
important parameter
How does it affect the VTC?

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Mahmudul
How does Kn.RL affect the VTC?
It can be seen from the preceding discussion that the term (kn RL)
plays an important role in determining the shape of VTC curve, and
that it appears as a critical parameter in expressions for VOL, VIL,
and VIH. Assuming that parameters such as the power supply voltage
VDD and the driver MOSFET threshold voltage V are dictated by
system- and processing-related constraints, the term (kn RL) remains
as the only design parameter which can be adjusted by the circuit
designer to achieve certain design goals.

The figure shows that

for larger KnRL values,
VOL becomes smaller &
because of that the
shape of VTC
approaches that of a
ideal inverter, with
very large transition
slope.
 nMOS in saturation depletion type nMOS

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 pMOS that’s always ON

𝐼𝐷𝑆𝑝 = 𝐼𝐷𝑆𝑛

Following the principle outlined for Resistive Load – Can you analytically derive the VTC?

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Mahmudul
 EEE 475: VLSI
LECTURE 6 : CMOS Inverter

05 JUN 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
 pMOS
nMOS

• Resistor
• PMOS

𝐼𝐿 = 𝐼𝐷

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Mahmudul
 The CMOS inverter has two important Secondly VTC exhibits a full output voltage swing between
Ref: Waste & Harris 0 V and VDD, and that the VTC transition is usually very
advantages over the other inverter
Sung-MO Kang configurations. sharp. Thus, the VTC of the CMOS inverter resembles that
Firstly the steady-state power dissipation of an ideal inverter.
of the CMOS inverter circuit is virtually
negligible, except for small power
dissipation due to leakage currents.

𝐼𝐷𝑝

𝐼𝐷𝑛

In static condition: 𝐈𝐃𝐩 = 𝐈𝐃𝐧 we have to find the values of VOH, VOL, VIH, VIL, Vth

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 𝑉𝑡𝑝 is negative

𝐈𝐃𝐩 = 𝐈𝐃𝐧

𝑉𝐺𝑆𝑝 = 𝑉𝑖𝑛 − 𝑉𝐷𝐷 𝑉𝐺𝑆𝑛 = 𝑉𝑖𝑛

𝑉𝐷𝑆𝑝 = 𝑉 𝑜𝑢𝑡 − 𝑉𝐷𝐷 𝑉𝐷𝑆𝑛 = 𝑉 𝑜𝑢𝑡

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 𝑉 𝑜𝑢𝑡 = 𝑉𝐷𝐷 𝑉 𝑜𝑢𝑡 = 0 V

𝑽𝑶𝑯 = 𝑽𝑫𝑫 𝑉𝑂𝐿 = 0 𝑉

𝐈𝐃𝐩 = 𝐈𝐃𝐧

𝑉𝐺𝑆𝑝 = 𝑉𝑖𝑛 − 𝑉𝐷𝐷

𝑉𝐷𝑆𝑝 = 𝑉 𝑜𝑢𝑡 − 𝑉𝐷𝐷

𝑉𝐺𝑆𝑛 = 𝑉𝑖𝑛
𝑉𝐷𝑆𝑛 = 𝑉 𝑜𝑢𝑡
output voltage swing between 0 V and VDD

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 𝑉 𝑜𝑢𝑡 = 𝑉𝐷𝐷 𝑉 𝑜𝑢𝑡 = 0 V
𝑽𝑶𝑯 = 𝑽𝑫𝑫 𝑉𝑂𝐿 = 0 𝑉
𝐈𝐃𝐩 = 𝐈𝐃𝐧

𝑉𝐺𝑆𝑝 = 𝑉𝑖𝑛 − 𝑉𝐷𝐷

𝑉𝐷𝑆𝑝 = 𝑉 𝑜𝑢𝑡 − 𝑉𝐷𝐷

𝑉𝐺𝑆𝑛 = 𝑉𝑖𝑛
𝑉𝐷𝑆𝑛 = 𝑉 𝑜𝑢𝑡 In which region are the transistors in the region in between?

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 Transistor Regions

𝑉 𝑜𝑢𝑡 = 𝑉𝑖𝑛 − 𝑉𝑡𝑝

𝑉 𝑜𝑢𝑡 = 𝑉𝑖𝑛 − 𝑉𝑡𝑛

𝐈𝐃𝐩 = 𝐈𝐃𝐧

𝑉𝐺𝑆𝑝 = 𝑉𝑖𝑛 − 𝑉𝐷𝐷 Vtp

𝑉𝐷𝑆𝑝 = 𝑉 𝑜𝑢𝑡 − 𝑉𝐷𝐷

𝑉𝐺𝑆𝑛 = 𝑉𝑖𝑛
𝑉𝐷𝑆𝑛 = 𝑉 𝑜𝑢𝑡

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 Transistor Regions

𝐈𝐃𝐩 = 𝐈𝐃𝐧 𝑉 𝑜𝑢𝑡 = 𝑉𝑖𝑛 −

𝑉𝑡𝑝
𝑉 𝑜𝑢𝑡 = 𝑉𝑖𝑛 − 𝑉𝑡𝑛

B C D

VIL VIH
Vtp
Vth

𝑉𝑖𝑛 = 𝑉𝐼𝐿 𝑉𝑖𝑛 = 𝑉𝐼𝐻

𝑉𝑖𝑛 − 𝑉 𝑜𝑢𝑡 = 𝑉𝑡ℎ
𝑑𝑉 𝑜𝑢𝑡 / 𝑑𝑉 𝑖𝑛 = − 1 𝑑𝑉 𝑜𝑢𝑡 / 𝑑𝑉 𝑖𝑛 = − 1

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Region B
Region D
𝐈𝐃 = 𝐈𝐃𝐩 = 𝐈𝐃𝐧

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 𝑉𝑡𝑛, 𝑉𝑡𝑝

𝑘𝑛
𝑘𝑅 =
𝑘𝑝

𝜇 𝑛 𝐶 𝑜𝑥 𝑊/𝐿 𝑛
=
𝜇 𝑝 𝐶 𝑜𝑥 𝑊/𝐿 𝑝

Try to derive this equation from the conditions

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 Region C

The inverter threshold voltage is defined as Vth = Vin = Vout. When the
Vin=Vth, however, we find that Vout can actually attain any value
between (Vth - Vtn) and (Vth - Vtp), without violating the voltage
conditions used in this analysis. This is due to the fact that the VTC
segment corresponding to Region C becomes completely vertical if the
channel-length modulation effect is neglected, i.e., if λ = 0. In more
realistic cases with λ>0, the VTC segment in Region C exhibits a finite,
but very large, slope.
 Why pMOS size is greater then nMOS
size?
 𝑉𝑂𝐻, 𝑉𝑂𝐿, 𝑁𝑀)

© 2021, ORCHI
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The plot(a) shows Idsn and Idsp in terms of Vdsn and Vdsp for various values
of Vgsn and Vgsp . Plot(b) shows the same plot of Idsn and |Idsp | now in
terms of Vout for various values of Vin . The possible operating points of the
inverter, marked with dots, are the values of V out where I dsn = |I dsp | for
a given value of V in . These operating points are plotted on Vout vs. Vin axes
in Plot(c) to show the inverter DC transfer characteristics. The supply
current IDD = Idsn = |I dsp | is also plotted against Vin in plot(d) showing
that both transistors are momentarily ON as V in passes through voltages
between GND and VDD , resulting in a pulse of current drawn from the
power supply.
 EEE 475: VLSI
LECTURE 7 : Inverter Delay

05 JUN 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
 Ref: Waste & Harris
Sung-MO Kang

Here,the delays for the output rising, tpdr /tcdr,

and the output falling, tpdf /tcdf . Rise/fall times
are also sometimes called slopes or edge rates.
Propagation and contamination delay times are also
called max-time and min-time, respectively. The
gate that charges or discharges a node is called
the driver and the gates and wire being driven are
called the load. Propagation delay is usually the
most relevant value of interest, and is often simply
called delay.
 © 2021, ORCHI
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Mahmudul
 sat.
pMOS

where: 𝑉𝑂𝐻 ≠ 𝑉𝐷𝐷 𝑜𝑟 𝑉𝑂𝐿 ≠ 0 𝑉

© 2021, ORCHI
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 sat.
pMOS

where: 𝑉𝑂𝐻 ≠ 𝑉𝐷𝐷 𝑜𝑟 𝑉𝑂𝐿 ≠ 0𝑉

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Mahmudul
 © 2021, ORCHI
© 2024, Mohammad Mahmudul Hasan Tareq
 © 2021, ORCHI
© 2024, MohammadORCHI HASSANHasan Tareq
Mahmudul
 MOS Capacitances

© 2021, ORCHI
© 2024, Mohammad Mahmudul Hasan Tareq
 Here,
Consider the cascade connection of two Cgd and Cgs are primarily due to gate
CMOS inverter. The parasitic
capacitances associated with each overlap with diffusion.
MOSFET are illustrated individually.

Cdb and Csb are voltage-dependent

junction capacitances.

Cgb is due to the thin-oxide

capacitance over the gate area.

Cint is a lumped interconnect

capacitance,which represents the
parasitic capacitance contribution of
the metal or polysilicon connection
between the two inverters.

By combining the capacitances seen here into an equivalent lumped linear

capacitance, connected between the output node of the inverter and the
ground. This combined capacitance at the output node will be called the load
capacitance, Cload
Cload = Cgdn + Cgdp +Cdbn + Cdbp + Cint + Cg

Csbn and Csbp have no effect on the

transient behavior off the circuit
since the source-to-body voltages of
both transistors are always equal to
zero. Then Cgsn and Cgsp are also
not included in Cload as they are
connected between the input node
and the gnd or the Vdd
 https://www.youtube.com/watch?v=ZMkP7yZNFMQ

𝑉𝑖𝑛 𝑉 𝑜𝑢𝑡

𝐶 𝑙𝑜𝑎𝑑

https://www.youtube.com/watch?v=oB-7zeBRG_o

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a. Propagation Delay
b. Rise/Fall Times
V10% = 0 . 1 V DD, V90% = 0 . 9 V DD
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Mahmudul
𝜏 ∝ 𝑅 𝑝,𝑛 𝐶 𝑙𝑜𝑎𝑑

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 Charging and Discharging of the 𝐶𝑙𝑜𝑎𝑑

What is the differential equation?

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Mahmudul
 EEE 475: VLSI
LECTURE 8 : CMOS Inverter (Delay)

09 JUN 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
Vin: 0 → VDD (𝑎𝑏𝑟𝑢𝑝𝑡𝑙𝑦) ⇒ 𝑉 𝑜𝑢𝑡 falls ⇒ 𝝉𝑷𝑯𝑳

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 𝝉𝑷𝑯𝑳

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 𝝉𝑷𝑯𝑳

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 𝝉𝑷𝑯𝑳

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 𝝉𝑷𝑯𝑳

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 𝝉𝑷𝑯𝑳

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 𝝉𝒇𝒂𝒍𝒍

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 © 2021, ORCHI
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 𝝉𝑷𝑳𝑯

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 𝝉𝑷𝑯𝑳

© 2024, Mohammad Mahmudul Hasan Tareq

© 2024, Mohammad Mahmudul Hasan Tareq
© 2024, Mohammad Mahmudul Hasan Tareq
© 2024, Mohammad Mahmudul Hasan Tareq
 𝐶 𝑙𝑜𝑎𝑑
• 𝐶 𝑙𝑜𝑎𝑑 ∝ 𝑊𝐿

𝑊𝑛1 𝑊𝑝1 𝑊𝑛,𝑝2

= C dbn + C dbp + Cint + Cgb

© 2024, Mohammad Mahmudul Hasan Tareq

 𝜅𝑝 ~ 𝜅𝑛(𝜇𝑛/𝜇𝑝)

𝜅 ~1 # for this figure the equivalence C to ground is shown for the pmos

What is it’s equivalent RC Delay Model?

𝑅 𝑢 𝑛 = 𝑅 𝑢𝑝 = 𝑅 and 𝐶𝑔 = 𝐶𝑑 = 𝐶

© 2024, Mohammad Mahmudul Hasan Tareq

© 2024, Mohammad Mahmudul Hasan Tareq
© 2024, Mohammad Mahmudul Hasan Tareq
 2

2
2
2

𝜏𝑃𝐻𝐿 = 𝜏𝑃𝐿𝐻 = 𝜏𝑃
1
𝜇𝑛 = 2𝜇𝑝 →𝑊𝑝 = 2𝑊𝑛

© 2024, Mohammad Mahmudul Hasan Tareq

 EEE 475: VLSI
LECTURE 9 : CMOS Inverter (Delay)

08 SEP 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
© 2024, Mohammad Mahmudul Hasan Tareq
 2

2
2
2

𝜏𝑃𝐻𝐿 = 𝜏𝑃𝐿𝐻 = 𝜏𝑃
1
𝜇𝑛 = 2𝜇𝑝 →𝑊𝑝 = 2𝑊𝑛

© 2024, Mohammad Mahmudul Hasan Tareq

 Gate capacitances of INV 1are irrelevant for 𝐶𝑙𝑜𝑎𝑑
Diffusion capacitances of INV 2 are irrelevant for 𝐶𝑙𝑜𝑎𝑑

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Mahmudul
 Total Capacitance = 6C
When discharging (𝑉𝑖𝑛 = VDD)
When Charging (𝑉𝑖𝑛 = 0)

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Mahmudul
 Total Capacitance = 6C
Effective Rise/Fall Resistance= R
∴ 𝜏𝑃 = 𝑅(6𝐶)

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Mahmudul
 Total Capacitance = 3C+3nC
1 Effective Rise/Fall Resistance= R
∴ 𝜏𝑃 = 3𝑅𝐶(1 + 𝑛)

3C n3C

⋮ ⋮

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Mahmudul
 Choose transistor widths to achieve
effective rise and fall resistance equal 1. Find the fall/rise circuits
to that of a unit inverter (R).
consider, 𝜇𝑛 = 2𝜇𝑝 • Truth Table of NAND Gate

2𝑅 2𝑅 2𝑅
𝑘𝑝 𝑘𝑝 𝑘𝑝

𝑅
A 𝑘𝑛

𝑅
B 𝑘𝑛
𝑅
C 𝑘𝑛 Discharges when all three NMOS are ON and PMOS off
3𝑅
=𝑅 →𝜅𝑛 = 3
𝜅𝑛

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Mahmudul
 Choose transistor widths to achieve
effective rise and fall resistance equal 1. Find the fall/rise circuits
to that of a unit inverter (R).
consider, 𝜇𝑛 = 2𝜇𝑝 • Truth Table of NAND Gate

2𝑅 2𝑅 2𝑅
𝑘𝑝 𝑘𝑝 𝑘𝑝

𝑅
A 3

𝑅
B 3
𝑅
C 3 charges back up when any of the input goes to zero
(1 PMOS on – 1 NMOS OFF)
2𝑅
=𝑅 →𝜅 𝑝 = 2
𝜅𝑝
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Mahmudul
 Choose transistor widths to achieve
effective rise and fall resistance equal What is the effective Capacitance at input A,B,C and output Y?
to that of a unit inverter (R).
consider, 𝜇𝑛 = 2𝜇𝑝

2 2 2

A 3

B 3

C 3

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Mahmudul
 Choose transistor widths to achieve
effective rise and fall resistance equal What is the effective Capacitance at input A,B,C and output Y?
to that of a unit inverter (R).
consider, 𝜇𝑛 = 2𝜇𝑝 3-NAND with connected to another n 3-NAND

2 2 2
+5nC
A 3

B 3

C 3

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Mahmudul
 +5nC
A
B

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 +5nC +5nC
+5nC +5nC
A
B

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 𝜏

+5nC
+5nC +5nC
A
B

3𝐶 𝑅/3 + 3𝐶 𝑅/3 + 𝑅/3 + (9𝐶 + 5𝑛𝐶)(𝑅/3 + 𝑅/3 + 𝑅/3) = 12 + 5𝑛 𝑅𝐶

Elmore Delay
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 Choose transistor widths to achieve
effective rise and fall resistance equal
to that of a unit inverter (R).
consider, 𝜇𝑛 = 2𝜇𝑝

What is the effective Capacitance at input A,B,C and output Y?

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Mahmudul
 Choose transistor widths to achieve
effective rise and fall resistance equal
to that of a unit inverter (R).
consider, 𝜇𝑛 = 2𝜇𝑝
6
What is the effective Capacitance at input A,B,C and output Y?
6

6
Y

1 1 1

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Static CMOS is called "static" because it doesn’t require any
continuous power or refresh signal to maintain its state. Once
a value (either 0 or 1) is stored in a static CMOS circuit, it
remains stable without needing any additional power as long
as the circuit is powered on.
 EEE 475: VLSI
LECTURE 10 : Dynamic Logic Circuit

11 SEP 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
In static logic output is directly connected to VDD or GND

While in dynamic logic output is temporarily connected to VDD or GND

𝑉𝑂𝑈𝑇 (𝑡)

R leak

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Complementary NMOS pull-down
Pull-up network and pseudo
NMOS and PMOS network NMOS pull-up transistor out
networks in out
pull-down
• Robust pull-down in
• Fewer transistors (N+1) network
• Energy-efficient network
• Easy to design • Functionality depends
on transistor sizing

2N transistors in the design Static Power dissipation

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 out
Pull-up
network in pull-down
in out network
out
pull-down
pull-down in
network
network

CMOS needs 2N transistors Ratioed has static power N+2 transistors

No static power

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 Circuit has two phases
clock pre-charge
(i) 𝜙 = 0, Precharge
𝛟
(ii) 𝜙 = 1, Evaluate
out

in pull-down
network

evaluate

PDN is on: Y=0

PDN is off: Y=1

note: during evaluation phase inputs can

Stay stable or go from 0 → 1 during evaluate

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 INVERTER

pre-charge
clock

evaluate

note: during evaluation phase inputs can

Stay stable or go from 0 → 1 during evaluate

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 CASCADED INVERTERs

clock

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
Stick Diagram
 EEE 475: VLSI
LECTURE 12 : CMOS Layout

18 SEP 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
 Layout Diagrams are to Scale →hard to draw quickly
Stick Diagrams →fast way to plan cell layout before finalizing
estimate area from stick diagram

Layout
Circuit Diagram Stick Diagram

VDD
A

GND

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 VDD

C B A

GND

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 VDD

C B A

GND

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 VDD

C B A

GND

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 VDD

C B A

GND

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 VDD

C B A

GND

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 VDD

C B A

GND

• Reduce area →lower cost

Whenever possible we would
• lower capacitance →faster operation
like to share/merge contacts
© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 Isolated Shared-Merged

VDD VDD

B A B A
2 2
Y
A 2 Y Y

B 2

GND GND

What is the equivalent RC model in each case?

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 EEE 475: VLSI
LECTURE 13: Structured Design

25 SEP 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
Subsystem Design refers to breaking down a large system into
smaller, manageable units called "subsystems." Each subsystem
performs a specific function within the overall system.
Example: In a 4-bit microprocessor, the system is divided into
subsystems like:
#Memory: Stores data.
#Control Unit: Manages the operations.
#Datapath: Performs operations like addition or subtraction.
By designing each of these subsystems individually, the overall
system becomes easier to understand, design, and troubleshoot.

Structured Design is a method of designing systems where the

architecture is well-organized and follows a clear, logical
structure.
Example: Let’s take a digital processor. Instead of randomly
connecting gates or transistors, structured design would involve:
#Clearly defining what each part (like an arithmetic logic unit,
ALU) does.
#Organizing how the ALU connects to memory or control units.
#Ensuring regularity and modularity (repeating patterns) in the
design to make the system easy to replicate and debug.
 What components are needed to How are the logic elements going
achieve the functionality? to be realized using transistors?

What does the chip do? How are the logic gates are What is going to be the physical
going to be connected? geometry of the circuit elements
and interconnections?

© 2024, Mohammad Mahmudul Hasan Tareq

 Basic Digital Processor Structure

A system has billions of transistors

Do we design the connections

between the transistors
individually?

Structured Design

Highly regularized structures in each subsystems l!

© 2024, Mohammad Mahmudul Hasan Tareq

• Define the requirements of the system clearly
• Partition the overall architecture into appropriate sub-systems

• Consider the communication paths (interconnects, control signals, etc.)

• Draw a block diagram (floor plan)
• Design the structure to have regularity
• Draw circuit diagram →Stick Diagram →Layout
• Check design rules (DRC) on each cell
• Simulate the performance

Key to success
• Proper partitioning of the system
• Simple regularized design – modularity!

© 2024, Mohammad Mahmudul Hasan Tareq

1. Parity Generator
2. Bus arbitration logic
3. Multiplexer
4. Code Converter (Gray to Binary)
5. ALU Subsystem

© 2024, Mohammad Mahmudul Hasan Tareq

 Ref: Basic VLSI
Design by Plucket

1. Parity Generator
2. Bus arbitration logic
3. Multiplexer
4. Code Converter (Gray to Binary)
5. ALU Subsystem

© 2024, Mohammad Mahmudul Hasan Tareq

 A parity bit generator is a small circuit used to check for errors in
data transmission. It adds an extra bit (called a parity bit) to a group
• Define the requirements of the system clearly of data bits, helping detect if any errors occurred during transmission.
The receiver can check the data by counting the number of 1s. If the
number of 1s doesn't match the expected parity, the receiver knows
What is a parity generator? there was a transmission error.

Parity bits are often added to an n bit word to indicate whether it has even or odd number of 1s.
Parity generators generates or checks that parity bit

Functional Requirements

n is an unknown number
we want to design for regularity

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
we want to design a modular structure which can be cascaded to implement n bit

Parity information is passed from one cell to the next

Information is updated depending on the input at each cell

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 Basic Cell
𝐴𝑖
𝐴𝑖

𝑃𝑖−1
𝑃𝑖
𝑷𝒊 𝑷𝒊

𝑃𝑖
𝑃𝑖−1 Stick Diagram

𝐴𝑖 𝐴𝑖

Requirements: Boolean Expression:

• 𝐴𝑖 = 0 𝑃𝑖 = 𝑃𝑖−1
𝑃𝑖 = 𝐴𝑖 ∙ 𝑃𝑖−1 + 𝐴𝑖 ∙ 𝑃𝑖−1
• 𝐴𝑖 = 1 𝑃𝑖 = 𝑃𝑖−1

© 2024, Mohammad Mahmudul Hasan Tareq

 https://youtu.be/GHUXjkQjWmc?
si=E3zKo8Vjjcw7xvYg

© 2024, Mohammad Mahmudul Hasan Tareq

Functional Requirements

• If input priority line 𝐴𝑛 = 1, then output line 𝐴𝑃𝑛 = 1 irrespective of other inputs
• If input priority line 𝐴𝑛−1 = 1, then output line 𝐴𝑃𝑛−1 = 1 if 𝐴𝑛 = 0
⋮
𝑃
• If input priority line 𝐴1 = 1, then output line 𝐴1 = 1 if all other inputs are 0

Algebraic Expression: 𝐴𝑃4

Simplest unstructured implementation 𝐴𝑃3

pass transistor switches 𝐴𝑃2

𝐴1𝑃

We want regularized structure!

𝐴4 𝐴4 𝐴3 𝐴3 𝐴2 𝐴2 𝐴1 𝐴1

© 2024, Mohammad Mahmudul Hasan Tareq

Functional Requirements Let us define a variable called grant, g
𝑔 𝑖+1 = 1 , indicates no lines before 𝑖 wants access

Boolean Expression:

© 2024, Mohammad Mahmudul Hasan Tareq

Functional Requirements Let us define a variable called grant, g
𝑔 𝑖+1 = 1 , indicates no lines before 𝑖 wants access

Boolean Expression:

© 2024, Mohammad Mahmudul Hasan Tareq

 The basic concept of pass transistor logic is to control the
flow of signals through transistors based on control inputs
Basic Cell
pass transistor logic implementation

Boolean Expression:

*buffers are added every 4 cells

© 2024, Mohammad Mahmudul Hasan Tareq

 Basic Cell
pass transistor logic implementation

Boolean Expression:

𝐴𝑖 = 1
𝐴𝑃𝑖 = 𝑔𝑖+1
𝑔𝑖 = 0

© 2024, Mohammad Mahmudul Hasan Tareq

 Basic Cell
pass transistor logic implementation

Boolean Expression:

𝐴𝑖 = 0
𝐴𝑃𝑖 = 0
𝑔 𝑖 = 𝑔𝑖+1

© 2024, Mohammad Mahmudul Hasan Tareq

Code converter from gray to binary
In gray code consecutive numbers have only 1 bit difference

Binary Gray Converter needs to turn gray codes into binary

No.
𝑨
𝟐𝟐 𝑨
𝟏𝟏 𝑨
𝟎𝟎 𝑮
𝟐𝟐 𝑮
𝟏𝟏 𝑮
𝟎𝟎
𝐴2 = 𝐺2
0 0 0 0 0 0 0 𝐴𝑛 = 𝐺𝑛
𝐴1 = 𝐺1⨁𝐴2
1 0 0 1 0 0 1 𝐴𝑖 = 𝐺𝑖⨁Ai+1
2 0 1 0 0 1 1 𝐴0 = 𝐺0⨁𝐴1
3 0 1 1 0 1 0
4 1 0 0 1 1 0
5 1 0 1 1 1 1
6 1 1 0 1 0 1 4 bit
7 1 1 1 1 0 0

© 2024, Mohammad Mahmudul Hasan Tareq

VLSI design involves carefully partitioning systems into sub-systems and building them modularly

1. Parity Generator Text Book: Basic VLSI Design

David Pucknell and Kamran Eshraghian
2. Bus arbitration logic Chapter 6 (6.1, 6.2, 6.4)
W&H: Chapter 11
3. Multiplexer
4. Code Converter (Gray to Binary)
5. ALU Subsystem

© 2024, Mohammad Mahmudul Hasan Tareq

 EEE 475: VLSI
LECTURE 14: Subsystem Design – I

25 SEP 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
 Digital systems are designed following a top-down approach.
They key is in partitioning smartly!

4-bit Microprocessor control

address

Control
Memory Datapath I/O
Unit

data
Main Sub-systems
1. Memory
• System partitioned into sub-systems according to main function
2. Datapath
• Communication between units is very important
3. Control Unit
• Design the individual sub-systems
4. Input/Output
Breakdown the functions into simpler and simpler forms systematically

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
The data path has been separated out in that
Figure and it will be seen that the structure
comprises a unit which processes data applied at
one port and presents its output at a second port.
Alternatively, the two data ports may be combined
as a single bidirectional port if storage facilities
exist in the data path. Control over the functions
to be performed is effected by control signals as
indicated.

Communications strategy for data path

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 control

1. What does an ALU do?

Performs arithmetic/logic operation on data given to it and produces corresponding output Datapath
4 bit
2. Can we further partition the datapath into sub-systems?

control data

direction selection operation shift control

I/O Register ALU Shifter

data

The datapath is designed to ensure smooth Control Signals: These are like traffic
communication between I/O, registers, the ALU, lights that tell each part of the datapath
and the shifter. This is like setting up a factory what to do and when to do it (e.g., when
line where different workstations (registers, ALU, to store a number in a register, when to
shifter) pass the product (data) from one station perform an addition in the ALU, or when
to another. to shift bits).

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 control

1. What does an ALU do?

Performs arithmetic/logic operation on data given to it and produces corresponding output Datapath
4 bit
2. Can we further partition the datapath into sub-systems?

control data

direction selection operation shift control

I/O Register ALU Shifter

data

• How do the data-path sub-system units communicate and transfer data within themselves?

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 operate on two 4-bit data a and b and produce results

1. One Bus

Data Handling: Only one data transfer can happen at a time. If the ALU needs data from two registers,
it has to fetch one piece of data, perform the operation, and then fetch the other piece of data.
Example: Imagine a one-lane road where cars (data) can only travel in one direction at a time. If two
cars need to reach the same destination, one has to wait for the other to pass first.

© 2024, Mohammad Mahmudul Hasan Tareq

 operate on two 4-bit data a and b and produce results

2. Two Bus

Parallel Operations: For example, the ALU can fetch data from one register on the first bus and from another
register on the second bus at the same time.
Example: Think of this as a two-lane road where cars (data) can travel in both directions simultaneously or reach
different destinations at the same time.

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 operate on two 4-bit data a and b and produce results

3. Three Bus

Maximum Flexibility: This setup allows the ALU to read from two different registers (using two buses) and write the result to a
third register (using the third bus) simultaneously.
Example: Imagine a three-lane highway where cars can travel to three different destinations without any delays. This enables
the fastest data transfer.

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 operate on two 4-bit data a and b and produce results

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 control

control

Datapath
4 bit I/O Register ALU Shifter

data

data
A shifter moves the bits of a number to the left or
right. This is like multiplying
Whator dividing the number by
is a shifter?
powers of 2. For example,What shifting leftitbydo?
does one bit is like
multiplying the number by 2, and shifting right by one
bit is like dividing the number by 2.
© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 This page will help you to understand the Topic

control

control

Datapath
4 bit I/O Register ALU Shifter

data

data

What is a shifter?
What does it do?

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 The General Arrangement of a 4-bit Arithmetic Processor

1. During
Metalthe
candesign
crossprocess, and in particular
polysilicon whenwithout
or diffusion defining the
anyinterconnection strategy
significant effect.
and designing the stick diagrams, care must be taken in allocating the layers to the
various data or control paths. We must remember that:
2. Wherever polysilicon crosses diffusion a transistor will be formed. This
includes the second polysilicon layer for processes that have two.

3. Wherever lines touch on the same level an interconnection is formed.

4. Simple contacts can be used to join diffusion or polysilicon to metal.

5. To join diffusion and polysilicon we must use either a buried contact or a

butting contact (in which case all three layers are joined together at the
contact) or two contacts, diffusion to metal then metal to polysilicon.

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 The General Arrangement of a 4-bit Arithmetic Processor

6. In some processes, a second metal layer is available. This can cross over any
other layers and is conveniently employed for power rails.

7. First and second metal layers may be joined using a via.

8. Each layer has particular electrical properties which must be taken into
account.

9. For CMOS layouts, p- and n-diffusion wires must not directly join each other,
nor may they cross either a p-well or an n-well boundary.

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 Datapath needs an n-bit shifter →Shift data by any number between 0 to (n-1) places

https://youtu.be/By5CccQoCWM?si=sCmnNk9MZcBqJ2MG
4 bit Shifter Requirements
1. Take 4-bit data input (parallel-in)
2. Shift data by 0,1,2, or 3 places as indicated by control signal (serial shift)
3. Output 4-bit data (parallel-out)

in3 in2 in1 in0 out3 out2 out1 out0

1 1 1 0 data 1 1 1 0 sh0
0 1 1 1 sh1
1 0 1 1 sh2
1 1 0 1 sh3 Barrel-Shifter

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
Basics Structure: Crossbar Switch

out3 out2 out1 out0

sw03 sw02 sw01 sw00 in0
sw13 sw12 sw11 sw10 in1
sw23 sw22 sw21 sw20 in2
sw33 sw32 sw31 sw30 in3

সব#েলা সুইচ একসােথ ব- (ON) করেল সব ইনপুট সব আউটপুেটর সােথ

কােন4 হেয় যােব, যা শট9 সা;কে: টর মেতা হেয় যােব।

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
out3 out2 out1 out0
in3 in2 in1 in0 sh0
in0 in3 in2 in1 sh1
in1 in0 in3 in2 sh2
in2 in1 in0 in3 sh3

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
out3 out2 out1 out0
in3 in2 in1 in0 sh0
in0 in3 in2 in1 sh1
in1 in0 in3 in2 sh2
in2 in1 in0 in3 sh3

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
out3 out2 out1 out0
in3 in2 in1 in0 sh0
in0 in3 in2 in1 sh1
in1 in0 in3 in2 sh2
in2 in1 in0 in3 sh3

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
out3 out2 out1 out0
in3 in2 in1 in0 sh0
in0 in3 in2 in1 sh1
in1 in0 in3 in2 sh2
in2 in1 in0 in3 sh3

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 out3 out2 out1 out0
in3 in2 in1 in0 sh0
in0 in3 in2 in1 sh1
in1 in0 in3 in2 sh2
in2 in1 in0 in3 sh3

Simple regularized design

total number of transistors in system

Regularity =
no. of transistors that need to be designed in detail

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 out3 out2 out1 out0
in3 in2 in1 in0 sh0
in0 in3 in2 in1 sh1
in1 in0 in3 in2 sh2
in2 in1 in2 in3 sh3

• Simple regularized design

• Combinatorial Shifter

Design Problem:
Can you implement a Barrel Shifter
with MUX? What is the regularity?

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 https://www.youtube.com/watch?v=BU399v3lAic&t=443s

out3 out2 out1 out0

in3 in2 in1 in0 sh0
in0 in3 in2 in1 sh1
in1 in0 in3 in2 sh2
in2 in1 in2 in3 sh3

• Simple regularized design

• Combinatorial Shifter

Design Problem:
Can you implement a Barrel Shifter
with MUX? What is the regularity?

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 EEE 475: VLSI
LECTURE 15 : Subsystem Design – II

25 SEP 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
 control

control

Datapath
4 bit I/O Register ALU Shifter

data

data

© 2024, Mohammad Mahmudul Hasan Tareq

4-bit Microprocessor

© 2024, Mohammad Mahmudul Hasan Tareq

 4-bit Microprocessor

control

The mathematical brain of

the microprocessor
I/O Register ALU
ALU Shifter

data

© 2024, Mohammad Mahmudul Hasan Tareq

 operation
control [0:1]

A[0:3]

B[0:3]
ALU Result
status
A [0:3]

Result [0:3]
Four Functions: status
B [0:3]
• Bitwise AND
• Bitwise OR
• Addition
• Subtraction

© 2024, Mohammad Mahmudul Hasan Tareq

 Four Functions: A0
• Bitwise AND • Addition Y0
• Bitwise OR • Subtraction B0
A1
Y1 𝐀
B1 𝐘
AND
A2 𝐁
Y2
B2
A3 Y3
B3

© 2024, Mohammad Mahmudul Hasan Tareq

 Four Functions: A0
✓ Bitwise AND • Addition
Y0
• Bitwise OR • Subtraction
B0
A1
Y1 𝐀
B1 OR 𝐘
𝐁
A2 Y2
B2
A3 Y3
B3

© 2024, Mohammad Mahmudul Hasan Tareq

 0
A3 A2 A1 A0 1010
+ B3 B2 B1 B0 1100 A0
Four Functions: 𝐅𝐀 S0
✓Bitwise AND • Addition 𝐂𝐨𝐮𝐭 𝐒 𝟑 𝐒 𝟐 𝐒 𝟏 𝐒 𝟎 10110 B0
✓ Bitwise OR • Subtraction

A1
𝐅𝐀 S1
B1

Cin A2
𝐅𝐀 S2
B2
A
𝐅𝐀 S
B A3
𝐅𝐀 S3
B3
𝐶𝑜𝑢𝑡
Cout

© 2024, Mohammad Mahmudul Hasan Tareq

© 2024, Mohammad Mahmudul Hasan Tareq
 00 AND
control
01 OR
10 ADD
Four Functions: A 11 SUB
✓Bitwise AND ✓ Addition AND
✓ Bitwise OR ✓ Subtraction
B
OR 4: 1
Result
ADD MUX
0

1
SUB

Carry Out

© 2024, Mohammad Mahmudul Hasan Tareq

 0
1

A0 A0
Four Functions: 𝐅𝐀 S0 𝐅𝐀 S0
✓Bitwise AND ✓ Addition B0 B0
✓ Bitwise OR ✓ Subtraction

A1 A1
𝐅𝐀 S1 𝐅𝐀 S1
B1 B1

A2 A2
𝐅𝐀 S2 𝐅𝐀 S2
B2 B2

A3 A3
𝐅𝐀 S3 𝐅𝐀 S3
B3 B3

Cout Cout

© 2024, Mohammad Mahmudul Hasan Tareq

 Four Functions:
✓Bitwise AND ✓ Addition
✓ Bitwise OR ✓ Subtraction

𝐀
𝐒
𝐁 ADD / SUB
𝟎/𝟏 𝐂𝐨𝐮𝐭

© 2024, Mohammad Mahmudul Hasan Tareq

 00 AND
ctrl0 01 OR
Four Functions: 10 ADD
✓Bitwise AND ✓ Addition
✓ Bitwise OR ✓ Subtraction AND 0 11 SUB
ctrl1
1
OR
0
A 𝐑𝐞𝐬𝐮𝐥𝐭
B ADD 1
SUB

𝐶𝑎𝑟𝑟𝑦 𝑂𝑢𝑡

© 2024, Mohammad Mahmudul Hasan Tareq

© 2024, Mohammad Mahmudul Hasan Tareq
© 2024, Mohammad Mahmudul Hasan Tareq
 ctrl0 ctrl1
00 AND
01 OR
AND 0 10 ADD
Four Functions:
✓Bitwise AND ✓ Addition 11 SUB
1
✓ Bitwise OR ✓ Subtraction OR
0
A 𝐑𝐞𝐬𝐮𝐥𝐭
ADD 1
B
SUB
𝑍𝑒𝑟𝑜
S3
𝑁𝑒𝑔𝑎𝑡𝑖𝑣𝑒
𝐶𝑎𝑟𝑟𝑦 𝑂𝑢𝑡
S3
B3
A3 𝑂𝑣𝑒𝑟𝑓𝑙𝑜𝑤

ALU Basic Functionality

© 2024, Mohammad Mahmudul Hasan Tareq
 EEE 475: VLSI
LECTURE 16: Memory – I

29 SEP 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
 Transistor Theory
Memory Inverter Characteristics
Sub-system Design Interconnects

Modeling Digital Systems CMOS Logic Gate Design IC Fabrications

using Verilog Combinatorial Logic Layout
Dynamic Logic
Sequential Logic

What is RTL? Why is this called RTL?

© 2024, Mohammad Mahmudul Hasan Tareq

 CMOS systems are portioned into sub-systems

Data Storage

Exchange Controls what happens

information at a time in processor
exchange (sequential circuit with
standard cells or PLAs)

* Interconnections

Main Computation Unit

basic combinatorial logic (AND,OR, XOR) or
arithmetic operation (add, multi, shift, compare)

© 2021, ORCHI
© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 CMOS systems are portioned into sub-systems

Data Storage

Exchange Controls what happens

information at a time in processor
exchange (sequential circuit with
standard cells or PLAs)

* Interconnections

Main Computation Unit

basic combinatorial logic (AND,OR, XOR) or
arithmetic operation (add, multi, shift, compare)

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Mahmudul
Access memories with an address Sequential Memory gives you the address of
Latency same f or any address (no address) where a certain data is stored
e.g. Shift Registers

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 Store data in Store data by
feedback circuit charge on
capacitor

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Mahmudul
 Fixed at Reprogrammable
fabrication
programmed once
Reprogrammable Reprogrammable
*erased with UV
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Mahmudul
Store data in Store data
feedback by charge on
circuit capacitor

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© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 Row decoder: Turns on word line
from n bit address
16 × 4 Memory Array
Column Circuitry: amplifiers or
16 words with 4 bits per word Buffers to read data
Each bit is stored in a memory cell
Total Memory Cell = 16 ×4 = 64 Column Decoder: selects the 2 𝑚 bits

2 𝑛 words with 2 𝑚 bits

𝑛 = 4, 𝑚 = 2
fold

Usually millions of words

each 8-64 bits each

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Mahmudul
 bit bit_b
• Read and Write data
word
• Hold data as long as VDD is there
• 6T cell

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Mahmudul
 • Initially bit=0
• We want to write 1 word
• Turn on Word 0 →𝟏

NMOS can pass only 𝑉𝐷𝐷 − 𝑉𝑇

bit 0→ 𝟏 1→ 𝟎 bit_b
Why pass-transistors not used here?
1 0
Density is VERY important for Memory

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© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 bit conditioning circuit
𝜙2

• Stored data 1
• Word 0 so transistor OFF
• Bit conditioning circuit charges bit lines to 1 word
• Turn word line on to read 0 →𝟏 ⋮
• column circuitry helps to read bit

bit bit_b
𝜙2 𝟏 𝟏
𝟏 𝟎
word 𝐶𝐵 𝐶𝐵
bit
⋮
bit_b
could be very
slow! out_bit_b column circuitry out_bit

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© 2024, Mohammad HASSANHasan Tareq
Mahmudul
 How do READ and WRITE work in SRAM?
Is this circuit enough? Do you need anything-else? bit conditioning circuit
𝜙2

word

bit bit_b

* Inverter transistor is weaker than NMOS

* Hi-SKEW inverters (fast fall)
sense amplifiers are another popular option out_bit_b column circuitry out_bit

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Mahmudul
• Bit line pre-charged to 1
• Word is raised for reading word
(A1 and A2 ON) 0 →𝟏 ⋮
read stability: D1 ≫A1
A1 A2
bit P1 P2 bit_b
𝟏 𝟏
𝟎 𝟏
𝐶𝐵 D1 D2
𝐶𝐵

out_bit_b column circuitry out_bit

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Mahmudul
• Bit line pre-charged to 1
• Word is raised for reading word
(A1 and A2 ON) 0 →𝟏 ⋮
read stability: D1 ≫A1
A1 A2
bit P1 P2 bit_b
𝟏 𝟎
𝟎 𝟏
• Bit line pre-charged to DATA and DATA_B 𝐶𝐵 D1 D2
𝐶𝐵
• Word is raised for Writing
(A1 and A2 ON) ⋮
write stability: A2 ≫P2
𝑤𝑟𝑖𝑡𝑒

𝑑𝑎𝑡𝑎 𝟏 write driver

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Mahmudul
read stability: D1 ≫A1 word
⋮

A1 A2
write stability: A2 ≫P2 bit P1 P2 bit_b

D1 D2
SRAM Transistor Sizing
NMOS (D1,D2) : strongest
Access (A1.A2) : intermediate ⋮
PMOS (P1,P2) : weakest
W smaller → 𝑤𝑒𝑎𝑘𝑒𝑟 (𝑙𝑜𝑤𝑒𝑟 𝑔 𝑚 )

see W&H: 12.2.1.1-3, Fig.12.4-7

Fig.12.13-14: Physical Layout

© 2024, Mohammad Mahmudul Hasan Tareq

 𝑛 − 𝑘 bit address
selects one of 2 𝑛−𝑘 word line

© 2024, Mohammad Mahmudul Hasan Tareq

 𝑛 − 𝑘 bit address
See layout.
selects one of 2 𝑛−𝑘 word line
Fig.12.22

• simplest decoder : AND gates

• Decoders have to be pitch matched

Requires 2 𝑛−𝑘 AND gates

each with N=n-k inputs
• N>4 gates start to become slow
[recap: avoid fan in greater than 4]

© 2024, Mohammad Mahmudul Hasan Tareq

 𝑛 − 𝑘 bit address
selects one of 2 𝑛−𝑘 word line

• simplest decoder : AND gates

• Decoders have to be pitch matched

• N>4 gates start to become slow

[recap: avoid fan in greater than 4]

4 bit (16 word) decoder made with 2 input NAND

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 𝑘 bit address
selects one of 2 𝑘 word line

16 words with 4 bits

• Usually implemented with MUX

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Store data Store data
in by charge
feedback on
circuit capacitor

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• Data is stored on capacitor
• 1T-1C cell

Capacitor is physically created

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 ➢ Sense amplifies are used
• bit line is pre-charged to VDD/2 ➢ READ is destructive,
• Word line is turned on data needs to be refreshed
• Charge sharing occurs which determines data state

VDD/2

Cbit

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• bit line is forced to Data (VDD, 0)
• Word line is turned on
• Ccell is charge/discharged

What are the major differences between SRAM and DRAM?

VDD/2 Where are they used? What decides which is used where?

Cbit

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 EEE 475: VLSI
LECTURE 17: Memory – II (Register)

29 SEP 2024
2024, Mohammad Mahmudul Hasan Tareq
EEE CUET
What are the major differences between SRAM and DRAM?
Where are they used? What decides which is used where?

• Memory density
• Memory Performance
• Memory Cost

© 2024, Mohammad Mahmudul Hasan Tareq

 Performance and Capacity

32-64 bits FF

SRAM

DRAM

non-volatile memory

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• CPUs fastest and smallest memory unit
• It can hold an instruction, a storage address, or any kind of binary data
• Usually 32 or 64 bit long
• Most common implementation of n bit register →n FF

clock

FF stores the information

Clock edge determines when data is taken →Transfer of new information onto register is loading

© 2024, Mohammad Mahmudul Hasan Tareq

• CPUs fastest and smallest memory unit
• It can hold an instruction, a storage address, or any kind of binary data
• Usually 32 or 64 bit long
• Most common implementation of n bit register →n FF

clock

FF stores the information

Clock edge determines when data is taken clock
Clock is usually a global entity
load

© 2024, Mohammad Mahmudul Hasan Tareq

 • CPUs fastest and smallest memory unit
• It can hold an instruction, a storage address, or any kind of binary data
• Usually 32 or 64 bit long
• Most common implementation of n bit register →n FF

clock
load

FF stores the information

clock
Clock edge determines when data is taken
Logic gates determine information transfer load
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© 2024, Mohammad Mahmudul Hasan Tareq
• Load =1 𝐼0 𝑝𝑎𝑠𝑠𝑒𝑠
• Load =0 𝐴0 retains

All 4 bits are loaded in parallel and can be read in parallel →Parallel In to Parallel Out (PIPO)

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 Takes data input serially, and shifts the data in each clock pulse

right shift register

• Can also have left shift registers

• Or have bidirectional shift registers

Bits are loaded and read serially →Serial In to Serial Out (SISO)
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 Transfer 4 bit data from Register A to Register B

Shift happens on every CLK edge

Data is B is erased after 4 CLK edge word time
Data in A is retained through feedback bit time

© 2024, Mohammad Mahmudul Hasan Tareq

Parallel In to Parallel Out (PIPO)
Serial In to Serial Out (SISO)
Serial In to Parallel Out (SIPO)
* check out the circuits for these ones
Parallel In to Serial Out (PISO)

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Parallel In to Parallel Out (PIPO)
Serial In to Serial Out (SISO)
Serial In to Parallel Out (SIPO)
Parallel In to Serial Out (PISO)

Left Shift/Right Shift

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 𝑨𝟎 Counters are registers that go through known/prescribed sequences

Count Binary Counters go through binary number sequence

4 bit binary counter has 4 flip-flops and can count from 0-15
𝑨𝟏

Count

𝑨𝟎
𝑨𝟐

𝑨𝟏

𝑨𝟐
𝑨𝟑

𝑨𝟑

Reset
© 2024, Mohammad Mahmudul Hasan Tareq
 Counters are registers that go through known/prescribed sequences
Binary Counters go through binary number sequence
4 bit binary counter has 4 flip-flops and can count from 0-15

𝑨𝟎 State Diagram
CLK
CLK
𝑨𝟎
𝑨𝟏

𝑨𝟏
𝑨𝟐
𝑨𝟐

𝑨𝟑 m is the number of states

𝑨𝟑

ripple counter 𝑚 = 𝟏𝟔

© 2024, Mohammad Mahmudul Hasan Tareq

Counters are registers that go through known/prescribed sequences

• Binary Counters go through binary number sequence

• Linear Feedback Shift Registers (LFSR)

Reading Assignment: What is an LFSR? How do LFSRs

work as pseudo-random number generators? See W&H:
Chapter 11, Example 11.1

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 W&H: 12.7
A programmable logic array (PLA) provides a regular structure for implementing combinational logic
• Any logic can be expressed as a sum of products of its input Inputs – literals
• Outputs are the ORs of the ANDs of the inputs AND-products/minterms
OR- output
• PLA consists of an AND plane and an OR plane to compute the outputs.

Full-Adder

A B C S Cout

𝑊&𝐻: 12.7
© 2024, Mohammad Mahmudul Hasan Tareq
A programmable logic array (PLA) provides a regular structure for implementing combinational logic
• Any logic can be expressed as a sum of products of its input
• Outputs are the ORs of the ANDs of the inputs
• PLA consists of an AND plane and an OR plane to compute the outputs.

Full-Adder Sketch a dot diagram f o r

a 2-input XOR using a PLA.

A B C S Cout

© 2024, Mohammad Mahmudul Hasan Tareq

❑
• Memory Classification
• Memory Hierarchy
• Memory Architecture Reference Text A: West & Harris : Chapter 12
Sections: 12.2.1-3, 12.3, 12.5, 12.7
❑
Suggested self-read: 12.4, 12.6
• SRAM
• DRAM
Reference Text B: Morris Mano : Chapter 6
* Topic of Registers was taught from here
❑ (Chapter 6 and 7 are available on Teams)
• Implementation with FF
• Counter & LFSR

❑
• Max-Min Delay
• Clock Frequency

© 2024, Mohammad Mahmudul Hasan Tareq

© 2024, Mohammad Mahmudul Hasan Tareq