Module#2_ Instruction Set Architecture

Memory is a storage component in the computer used to store application programs.

The Memory Chip is divided into equal parts called as “CELLS”.
Each Cell is uniquely identified by a binary number called as “ADDRESS”.
For example, the Memory Chip configuration is represented as ’64 K x 8′ as shown in the figure
below.

1. Data Space in the Chip = 64K X 8

2. Data Space in the Cell = 8 bits
3. Address Space in the Chip = 16 bits
 Difference Between Byte and Word Addressable Memory

Byte Addressable Memory Word Addressable Memory

When the data space in the cell = 8 bits then the corresponding address space is When the data space in the cell = word length of CPU then the
called as Byte Address. corresponding address space is called as Word Address.

Based on this data storage i.e. Bytewise storage, the memory chip configuration Based on this data storage i.e. Word wise storage, the memory chip configuration
is named as Byte Addressable Memory. is named as Word Addressable Memory.

For eg. : 64K X 8 chip has 16 bit Address and cell size = 8 bits (1 Byte) which For eg. : For a 16-bit CPU, 64K X 16 chip has 16 bit Address & cell size = 16 bits
means that in this chip, data is stored byte by byte. (Word Length of CPU) which means that in this chip, data is stored word by word.
 Big-Endian and Little-Endian
Endianness: Ordering /Sequencing of bytes of a word of digital data into the computer memory.

Little and Big endian are two ways of storing multibyte data-types ( int , float, etc).

1) Big-Endian: Lower byte-addresses are used for the most significant bytes of the word or − In this scheme, high-order byte
is stored on the starting address (A) and low-order byte is stored on the next address (A + 1).
2) Little-Endian: Lower byte-addresses are used for the least significant bytes of the word or In this scheme, low-order byte is
stored on the starting address (A) and high-order byte is stored on the next address (A + 1).

• Consider a 32-bit integer (in hex): 0x12345678 which consists of 4 bytes: 12, 34, 56, and 78.
Hence this integer will occupy 4 bytes in memory.
Assume, we store it at memory address starting 1000. On little-endian, memory will look like
Address Value
1000 78
1001 56
1002 34
1003 12
On big-endian, memory will look like
Address Value
1000 12
1001 34
1002 56
1003 78
 • A view of the memory and the register structure , types of data
supported and the ALU operations visible to the programmer is
called the ISA.
• An Instruction is an information that is required by the processor
to execute certain operations such as addition, subtraction, etc.
• The collection of all the Instructions supported by the ISA is
known as the Instruction set of the processor.
Instruction • Elements of an Instruction:
and Operation code
Source operand(s) address
Instruction Destination operand address
Sequencing Next address field
The Source and Destination operands may be :
1. Main or Virtual memory addresses
2. Processor Register
3. I/O device
4. Immediate value
 A computer must have instructions capable
of performing 4 types of operations:
Instruction 1) Data transfers between the memory and
and the registers (MOV, PUSH, POP, XCHG).
2) Arithmetic and logic operations on data
Instruction (ADD, SUB, MUL, DIV, AND, OR, NOT).
Sequencing 3) Program sequencing and control (CALL.RET,
LOOP, INT).
(Contd.) 4) I/0 transfers (IN, OUT).
 Register Transfer Notation:
The information transformed from one register to another register is
represented in symbolic form by replacement operator.
Assembly Language Register Transfer Meaning
Instruction Notation

Add R1,R2 R2  [R1]+ [R2] Add the contents of register R1 with the
contents of R2 and place the result in R2

Mov R1,R2 R2  [R1]

Copy the contents of register R1 into R2.

Mov LocX, R0 R0  [LocX]

Copy the contents of main memory location
LocX into register R0.
 Instruction is of variable length depending upon the number of
Instruction addresses it contains. Generally, CPU organization is of three
types based on the number of address fields:
Formats • Single Accumulator organization
• General register organization
• Stack organization
(Zero, One, Based on the number of addresses, instructions are classified as:
Zero Address Instructions – A stack-based computer does not
Two and use the address field in the instruction. To evaluate an
expression first it is converted to reverse Polish Notation i.e.
Postfix Notation.
Three 1 One Address Instructions –
This uses an implied ACCUMULATOR register for data
Address manipulation. One operand is in the accumulator and the
other is in the register or memory location. Implied means
that the CPU already knows that one operand is in the
Instruction) accumulator so there is no need to specify it.
 Instruction Formats (Zero, One, Two and Three
Two Address Instructions –
This is common in commercial computers.
Here two addresses can be specified in the instruction
Here the result can be stored at different locations rather than just accumulators, but require
more number of bit to represent address.
• Here destination address can also contain operand.

Three Address Instructions –

This has three address field to specify a register or a
memory location.
Program created are much short in size but number of
bits per instruction increase.

Example: X = (A+B)*(C+D)
Addressing Modes
• It refers to the way in which the operand of an
instruction is specified.
• It specifies a rule for interpreting or modifying
the address field of the instruction before the
operand is executed.
• Addressing modes for 8086 instructions are
divided into two categories:
1) Addressing modes for data
2) Addressing modes for branch
• The 8086 memory addressing modes provide
flexible access to memory, allowing you to easily
access variables, arrays, records, pointers, and other
complex data types.
• The key to good assembly language programming
is the proper use of memory addressing modes.
 • Immediate addressing mode (symbol
#):In this mode data is present in
address field of instruction .Designed
Addressing like one address instruction format.
Note:Limitation in the immediate mode
is that the range of constants are
modes restricted by size of address field.

(Contd.):
• Register mode: In register addressing
the operand is placed in one of 8 bit or
16 bit general purpose registers.
• The data is in the register that is
specified by the instruction.Here one
register reference is required to access
the data.
 Addressing Modes(Contd.)
Register Indirect mode: In this addressing the operand’s offset is placed in any one of the registers.
• The effective address of the data is in the base register or an index register that is specified by the instruction.
Here two register reference is required to access the data.

Auto Indexed (increment mode): Effective address of the operand is the contents of a register specified in the instruction. After
accessing the operand, the contents of this register are automatically incremented to point to the next consecutive memory
location.(R1)+.
Here one register reference,one memory reference and one ALU operation is required to access the data.
Example:

• Add R1, (R2)+ // OR

• R1 = R1 +M[R2]
• R2 = R2 + d
• Useful for stepping through arrays in a loop. R2 – start of array d – size of an element
 Addressing Modes(Contd.)
Auto Indexed (increment mode): Effective address of the operand is the contents of a register specified in the instruction.
After accessing the operand, the contents of this register are automatically incremented to point to the next consecutive
memory location.(R1)+.
Here one register reference,one memory reference and one ALU operation is required to access the data.
Example:
• Add R1, (R2)+ // OR
• R1 = R1 +M[R2]
• R2 = R2 + d
• Useful for stepping through arrays in a loop. R2 – start of array d – size of an element
Auto indexed ( decrement mode): Effective address of the operand is the contents of a register specified in the instruction.
Before accessing the operand, the contents of this register are automatically decremented to point to the previous
consecutive memory location. –(R1)
Here one register reference, one memory reference and one ALU operation is required to access the data.
Example:
• Add R1,-(R2) //OR
• R2 = R2-d
• R1 = R1 + M[R2]
• Auto decrement mode is same as auto increment mode. Both can also be used to implement a stack as push and
pop . Auto increment and Auto decrement modes are useful for implementing “Last-In-First-Out” data structures.
 Addressing Modes(Contd.)
Based on Transfer of control, addressing modes are:
PC relative addressing mode: PC relative addressing mode is used to implement intra segment
transfer of control, In this mode effective address is obtained by adding displacement to PC.
• EA= PC + Address field value
• PC= PC + Relative value.
Base register addressing mode:Base register addressing mode is used to implement inter segment
transfer of control.In this mode effective address is obtained by adding base register value to
address field value.
• EA= Base register + Address field value.
• PC= Base register + Relative value.
Explaination Slide